On Thu, Aug 08, 2019 at 02:33:24PM -0600, Jerry Hoemann wrote: > On Fri, Aug 02, 2019 at 06:33:28PM +0200, Peter Zijlstra wrote: > > On Fri, Aug 02, 2019 at 06:20:15PM +0200, Peter Zijlstra wrote: > > > On Fri, Aug 02, 2019 at 02:33:41PM +0000, Lendacky, Thomas wrote: > > > > > > Talking to the hardware folks, they say setting CR8 is a serializing > > > > instruction and has to communicate out to the APIC, so it's better to > > > > use CLI/STI. > > > > > > Bah; the Intel SDM states: "MOV CR* instructions, except for MOV CR8, > > > are serializing instructions", which had given me a little hope. > > > > > > At the same time, all these chips still have the APIC TPR field too, so > > > much like how the TSC DEADLINE MSR is a hidden APIC write, so too is CR8 > > > I suppose :-( > > > > > > I'll still finish the patches I started, just to see what it would look > > > like. > > > > Another 'fun' issue I ran into while doing these patches; STI has a 1 > > instruction shadow, which we rely on, MOV CR8 does not. So things like: > > > > native_safe_halt: > > sti > > hlt > > > > turn into: > > > > native_safe_halt: > > cli > > movl $0, %rax > > movq %rax, %cr8 > > sti > > hlt > > > > Hi Peter, > > What is our the next step here? > > Are you still looking to make this change? > > Do we want to pick up Tom Lendacky's patch on an interim basis while > you're working on the bigger change? (I can say we tested Tom's > patch and it does address the issue we were seeing.) > > Thanks > > Jerry >
Hi Peter, Have you gotten a chance to look into this more? Thanks Jerry -- ----------------------------------------------------------------------------- Jerry Hoemann Software Engineer Hewlett Packard Enterprise -----------------------------------------------------------------------------
