From: Thor Thayer
Add the Arria10 DevKit System Resource Chip register and state
monitoring module to the MFD.
Signed-off-by: Thor Thayer
---
Note: This needs to be applied to the bindings document that
was Acked & Applied but didn't reach the for-next branch.
See https://patchwork.ozlabs.org/p
From: Thor Thayer
This patch adds the Altera Arria10 control & monitoring
functions to the Arria10 System Resource chip.
Signed-off-by: Thor Thayer
---
v2 Change compatible string and filename from -mon to -monitor
Change CONFIG from module to builtin.
Make wm_rst register writeable.
v
From: Thor Thayer
Add the Altera Arria10 DevKit System Resource Monitor functionality
to the MFD device.
Signed-off-by: Thor Thayer
Acked-for-MFD-by: Lee Jones
---
v2 Change from -mon to -monitor for clarity
v3 Shorten driver name (remove altr_).
---
drivers/mfd/altera-a10sr.c | 6 +-
1
From: Thor Thayer
Add the Monitor functionality to the Arria10 DevKit
System Resource chip.
Signed-off-by: Thor Thayer
---
v2 Change from -mon to -monitor for clarity.
v3 Change node name from a10_monitor to monitor.
---
arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 4
1 file changed,
From: Thor Thayer
his patch series adds the Altera Arria10 DevKit System Resource
chip's Status and Control Monitor to the A10SR Multi-Function
Device. An earlier patch added this to the hwmon class which
wasn't the proper place so this functionality is added to the
misc directory.
Version 2 chan
From: Thor Thayer
This patch series adds the Altera Arria10 DevKit System Resource
chip's Status and Control Monitor to the A10SR Multi-Function
Device. An earlier patch added this to the hwmon class which
wasn't the proper place so this functionality is added to the
misc directory.
Version 2 cha
From: Thor Thayer
This patch adds the Altera Arria10 control & monitoring
functions to the Arria10 System Resource chip.
Signed-off-by: Thor Thayer
---
v2 Change compatible string and filename from -mon to -monitor
Change CONFIG from module to builtin.
Make wm_rst register writeable.
-
From: Thor Thayer
Add the Arria10 DevKit System Resource Chip register and state
monitoring module to the MFD.
Signed-off-by: Thor Thayer
---
Note: This needs to be applied to the bindings document that
was Acked & Applied but didn't reach the for-next branch.
See https://patchwork.ozlabs.org/p
From: Thor Thayer
Add the Altera Arria10 DevKit System Resource Monitor functionality
to the MFD device.
Signed-off-by: Thor Thayer
---
v2 Change from -mon to -monitor for clarity
---
drivers/mfd/altera-a10sr.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mfd/altera-a10sr.c
From: Thor Thayer
Add the Monitor functionality to the Arria10 DevKit
System Resource chip.
Signed-off-by: Thor Thayer
---
v2 Change from -mon to -monitor for clarity.
---
arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/so
From: Thor Thayer
Confirm the chip->parent is valid before dereferencing because
the parent parameter is optional.
Signed-off-by: Thor Thayer
---
drivers/gpio/gpiolib-devprop.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpio/gpiolib-devprop.c b/drivers/gpio/gpiolib-devpro
From: Thor Thayer
Disable IRQs while injecting SDRAM errors. The RT patches exposed
a spinlock deadlock where the spinlock taken for the regmap write
deadlocked with the IRQ clear regmap write.
Error injection is not normally enabled for ECC but only for
testing.
Signed-off-by: Thor Thayer
---
From: Thor Thayer
This patch adds the Altera Arria10 control & monitoring
functions to the Arria10 System Resource chip.
Signed-off-by: Thor Thayer
---
MAINTAINERS |1 +
drivers/misc/Kconfig|7 ++
drivers/misc/Makefile |1 +
drivers/misc/al
From: Thor Thayer
Add the Arria10 DevKit System Resource Chip register and state
monitoring module to the MFD.
Signed-off-by: Thor Thayer
---
Note: This needs to be applied to the bindings document that
was Acked & Applied but didn't reach the for-next branch.
See https://patchwork.ozlabs.org/p
From: Thor Thayer
Add the Altera Arria10 DevKit System Resource Monitor functionality
to the MFD device.
Signed-off-by: Thor Thayer
---
drivers/mfd/altera-a10sr.c |4
1 file changed, 4 insertions(+)
diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
index 06e1f7f..0
From: Thor Thayer
This patch series adds the Altera Arria10 DevKit System Resource
chip's Status and Control Monitor to the A10SR Multi-Function
Device. An earlier patch added this to the hwmon class which
wasn't the proper place so this functionality is added to the
misc directory.
Thor Thayer
From: Thor Thayer
Add the Monitor functionality to the Arria10 DevKit
System Resource chip.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10_socdk.dtsi |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
b/arch/arm/boot/dts/s
From: Thor Thayer
Some SPI masters require slave selection before the transfer
can begin [1]. The SPI framework currently selects the chip using
either 1) the internal CS mechanism or 2) the GPIO CS, but not both.
This patch adds a new master->flags define to indicate both the GPIO
CS and the in
From: Thor Thayer
The Designware SPI master requires slave selection before the transfer
can begin [1].
This patch uses the new master flag to indicate both the GPIO CS and
the internal chip select should be used.
Tested On:
Altera CycloneV development kit
Compile tested for build error
From: Thor Thayer
Some SPI masters require the slave to be selected before a
transaction can occur - even in the case of GPIO chip select.
This patch adds a GPIO slave select parameter to indicate
the slave needs to be selected in the GPIO CS case.
Signed-off-by: Thor Thayer
---
v2 Add to SPI
From: Thor Thayer
Some SPI masters require slave selection before the transfer
can begin [1]. The SPI framework currently selects the chip using
either 1) the internal CS mechanism or 2) the GPIO CS, but not both.
This patch adds a boolean variable to indicate both the GPIO CS and
the internal c
From: Thor Thayer
Currently in the GPIO CS case, the transfer is stalled. The DesignWare
IP datasheet points out that the slave must be selected (SER) before the
transfer can start [1]. The SPI framework selects the chip using either
1) the internal CS mechanism or 2) the GPIO CS, but not both.
From: Thor Thayer
Correct the error message sent out in the case of a single
bit error IRQ allocation.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index
From: Thor Thayer
Add the IRQF_ONESHOT and IRQF_TRIGGER_HIGH flags to disable the
IRQ while executing the IRQ handler. Remove the IRQF_SHARED because
these are not shared IRQs in the domain. Exposed when flooding IRQs.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c | 18 ++
From: Thor Thayer
Add the device tree binding needed to support the TX FIFO threshold
parameter.
Signed-off-by: Thor Thayer
---
v2 Change parameter name from tx-loadsz to tx-threshold
---
Documentation/devicetree/bindings/serial/8250.txt |2 ++
1 file changed, 2 insertions(+)
diff --git
From: Thor Thayer
The Altera 16550 soft IP UART requires 2 additional registers for
TX FIFO threshold support. These 2 registers enable the TX FIFO
Low Watermark and set the TX FIFO Low Watermark.
Set the TX FIFO threshold to the FIFO size - tx_loadsz.
Signed-off-by: Thor Thayer
---
v2 Add bou
From: Thor Thayer
Some variants of the 16550 have a programmable TX FIFO threshold that
will trigger an IRQ when the FIFO drops below the threshold. The Altera
16550 compatible soft IP supports programmable TX FIFO thresholds.
This patch series adds the tx-threshold parameter to the device tree.
From: Thor Thayer
The tx-threshold parameter sets the TX FIFO low water threshold
trigger for the Altera 16550-FIFO32 soft IP.
Signed-off-by: Thor Thayer
---
v2 Change from tx-loadsz to tx-threshold
---
arch/nios2/boot/dts/10m50_devboard.dts |1 +
1 file changed, 1 insertion(+)
diff --g
From: Thor Thayer
Initialize the tx_loadsz parameter from passed in devicetree
tx-threshold parameter.
The tx_loadsz is calculated as the number of bytes to fill FIFO
when tx-threshold is triggered.
Signed-off-by: Thor Thayer
---
v2 Change from reading tx-loadsz parameter to reading
tx-thr
From: Thor Thayer
Initialize the tx_loadsz parameter if it is defined in the
device tree.
Signed-off-by: Thor Thayer
---
drivers/tty/serial/8250/8250_of.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_of.c
b/drivers/tty/serial/8250/8250_of.c
index 3
From: Thor Thayer
Add the device tree bindings needed to support the TX FIFO
load size.
Signed-off-by: Thor Thayer
---
Documentation/devicetree/bindings/serial/8250.txt |1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/8250.txt
b/Documentation/dev
From: Thor Thayer
The Altera 16550 soft IP UART requires 2 additional registers for
TX FIFO threshold support. These 2 registers enable the TX FIFO
Low Watermark and set the TX FIFO Low Watermark.
These registers are initialized in serial8350_do_startup(). Set
the TX FIFO threshold to the FIFO si
From: Thor Thayer
The tx-loadsz parameter sets the TX FIFO threshold level of
the Altera 16550-FIFO32 soft IP.
Signed-off-by: Thor Thayer
---
arch/nios2/boot/dts/10m50_devboard.dts |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/nios2/boot/dts/10m50_devboard.dts
b/arch/nios2/boot/
From: Thor Thayer
Some variants of the 16550 have a programmable TX FIFO threshold that
will trigger an IRQ when the FIFO drops below the threshold. The Altera
16550 compatible soft IP supports programmable TX FIFO thresholds.
This patch series adds the tx_loadsz to the device tree. The tx_loads
From: Thor Thayer
Rename the Memory Controller debug trigger to the same common
name as the EDAC devices.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
ind
From: Thor Thayer
The L2 and OCRAM devices have different ecc trigger names than
the other EDAC devices (FIFO peripherals). Make them all the same
and remove the character array from the device structure.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c | 13 +
drivers/e
From: Thor Thayer
Rename the EDAC debug trigger names to "altr_trigger"
for consistency.
Thor Thayer (2):
EDAC, altera: Rename device trigger to common name
EDAC, altera: Rename MC trigger to common name
drivers/edac/altera_edac.c | 15 ++-
drivers/edac/altera_edac.h |1 -
From: Thor Thayer
Add the SD/MMC FIFO EDAC module which is a dual-port RAM as
opposed to the other Arria10 peripheral's single port RAM FIFOs.
Thor Thayer (3):
Documentation: dt: socfpga: Add Arria10 SD-MMC EDAC binding
EDAC, altera: Add Arria10 SD-MMC EDAC support
ARM: dts: Add Arria10 SD
From: Thor Thayer
Add the device tree entries needed to support the Altera SD/MMC
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
Acked-by: Dinh Nguyen
---
v2 No change
---
arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 12
1 file changed, 12 insertions(+
From: Thor Thayer
Add Altera Arria10 SD-MMC FIFO memory EDAC support. The SD-MMC
is a dual port RAM implementation which is different than any
of the other peripherals and therefore requires additional code.
Signed-off-by: Thor Thayer
---
v2 Cleanup PortB initialization by moving device tree s
From: Thor Thayer
Add the device tree bindings needed to support the Altera SD-MMC
FIFO buffers EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
Acked-by: Rob Herring
---
v2 No change
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 19 +++
1 file changed, 19 in
From: Thor Thayer
Add Altera Arria10 SD-MMC FIFO memory EDAC support. The SD-MMC
is a dual port RAM implementation which is different than any
of the other peripherals and therefore requires additional code.
Signed-off-by: Thor Thayer
---
drivers/edac/Kconfig |7 ++
drivers/edac/alte
From: Thor Thayer
This patch series adds the SD/MMC FIFO EDAC module which is a dual-port
RAM as opposed to the other Arria10 peripheral's single port RAM FIFOs.
Thor Thayer (3):
Documentation: dt: socfpga: Add Arria10 SD-MMC EDAC binding
EDAC, altera: Add Arria10 SD-MMC EDAC support
ARM:
From: Thor Thayer
Add the device tree bindings needed to support the Altera SD-MMC
FIFO buffers EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 19 +++
1 file changed, 19 insertions(+)
diff --git a/Documentation/d
From: Thor Thayer
Add the device tree entries needed to support the Altera SD/MMC
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga
From: Thor Thayer
Add the device tree bindings needed to support the Altera NAND
FIFO buffers EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 32
1 file changed, 32 insertions(+)
diff --git a/Documentation/de
From: Thor Thayer
Add Altera Arria10 QSPI FIFO memory EDAC support.
Signed-off-by: Thor Thayer
---
drivers/edac/Kconfig |7 +++
drivers/edac/altera_edac.c | 34 +-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/Kconfi
From: Thor Thayer
Add the device tree bindings needed to support the Altera QSPI
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 16
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicet
From: Thor Thayer
Add Altera Arria10 USB FIFO memory EDAC support.
Signed-off-by: Thor Thayer
---
drivers/edac/Kconfig |7 +++
drivers/edac/altera_edac.c | 34 +-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/Kconfig
From: Thor Thayer
This patch series adds the NAND, DMA, USB and QSPI FIFO EDAC modules.
Thor Thayer (10):
Documentation: dt: socfpga: Add Arria10 NAND EDAC binding
Documentation: dt: socfpga: Add Arria10 DMA EDAC binding
Documentation: dt: socfpga: Add Arria10 USB EDAC binding
Documentat
From: Thor Thayer
Add Altera Arria10 NAND FIFO memory EDAC support.
Signed-off-by: Thor Thayer
---
drivers/edac/Kconfig |7 +++
drivers/edac/altera_edac.c | 34 +-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/Kconfi
From: Thor Thayer
Add the device tree entries needed to support the Altera USB
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi
b/ar
From: Thor Thayer
Add the device tree bindings needed to support the Altera DMA
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 16
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetr
From: Thor Thayer
Add Altera Arria10 DMA FIFO memory EDAC support.
Signed-off-by: Thor Thayer
---
drivers/edac/Kconfig |7 +++
drivers/edac/altera_edac.c | 34 +-
2 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/edac/Kconfig
From: Thor Thayer
Add the device tree entries needed to support the Altera DMA
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi
b/ar
From: Thor Thayer
Add the device tree bindings needed to support the Altera USB
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 15 +++
1 file changed, 15 insertions(+)
diff --git a/Documentation/devicetre
From: Thor Thayer
In preparation for the Arria10 ECC modules, check the status
of the parent in the device tree to ensure the block is enabled.
Skip if no parent phandle is set in the device tree.
Signed-off-by: Thor Thayer
---
v2 No change
v3 Move check into validate_parent_available().
v4
From: Thor Thayer
Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No Change
v3 Change to common compatible string based on maintainer comments
Add local IRQ values.
v4 Add compatible string for parent
From: Thor Thayer
Add the device tree entries needed to support the Altera Ethernet
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No change
v3 Add interrupts for SBERR and DBERR.
v4 No change
v5 Change "parent" phandle to "altr,ecc-parent"
---
arch/arm/boot/dts/so
From: Thor Thayer
In preparation for additional memory module ECCs, the IRQ and
check_deps() functions are being made available to all the memory
buffers. Move them outside of the OCRAM only area.
Signed-off-by: Thor Thayer
---
v2 New patch. Move shared functions outside OCRAM only area.
v3 C
From: Thor Thayer
In preparation for additional memory module ECCs, add the
memory initialization functions and helper functions used
for memory initialization.
Signed-off-by: Thor Thayer
---
v2: Specify INTMODE selection -> IRQ on each ECC error.
Insert functions above memory-specific func
From: Thor Thayer
The device private data structures should be converted from const
struct edac_device_prv_data to static const struct edac_device_prv_data.
Signed-off-by: Thor Thayer
---
v4 New patch added for conversion.
v5 No change
---
drivers/edac/altera_edac.c | 16
From: Thor Thayer
Add Altera Arria10 Ethernet FIFO memory EDAC support. Update
to support a common compatibility string for all Ethernet
FIFOs in the DT.
Signed-off-by: Thor Thayer
---
v2 Remove (void *) cast from altr_edac_device_of_match[]
Addition of panic flag to ethernet private data.
From: Thor Thayer
In preparation for additional memory module ECCs, the
IRQ function will check a panic flag before doing a
kernel panic on double bit errors.
OCRAM uncorrectable errors cause a panic because sleep/resume
functions and FPGA contents during sleep are stored in OCRAM.
ECCs on peri
From: Thor Thayer
This patch set adds the Ethernet EDAC and memory initialization functions
for Altera's Arria10 peripherals. The ECC memory init functions are common
to all the peripheral memory buffers (to follow in later patches).
Version 5 corrects a misunderstanding of the phandle name for
From: Thor Thayer
Add Altera Arria10 Ethernet FIFO memory EDAC support. Update
to support a common compatibility string for all ethernet
FIFOs in the DT.
Signed-off-by: Thor Thayer
---
v2 Remove (void *) cast from altr_edac_device_of_match[]
Addition of panic flag to ethernet private data.
From: Thor Thayer
This patch set adds the Ethernet EDAC and memory initialization functions
for Altera's Arria10 peripherals. The ECC memory init functions are common
to all the peripheral memory buffers (to follow in later patches).
Thor Thayer (7):
EDAC, altera: Add panic flag check to A10 I
From: Thor Thayer
Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No Change
v3 Change to common compatible string based on maintainer comments
Add local IRQ values.
v4 Add compatible string for parent
From: Thor Thayer
In preparation for additional memory module ECCs, the
IRQ function will check a panic flag before doing a
kernel panic on double bit errors.
OCRAM uncorrectable errors cause a panic because sleep/resume
functions and FPGA contents during sleep are stored in OCRAM.
ECCs on peri
From: Thor Thayer
In preparation for additional memory module ECCs, add the
memory initialization functions and helper functions used
for memory initialization.
Signed-off-by: Thor Thayer
---
v2: Specify INTMODE selection -> IRQ on each ECC error.
Insert functions above memory-specific func
From: Thor Thayer
The device private data structures should be converted from const
struct edac_device_prv_data to static const struct edac_device_prv_data.
Signed-off-by: Thor Thayer
---
v4 New patch added for conversion.
---
drivers/edac/altera_edac.c | 16
1 file changed
From: Thor Thayer
In preparation for additional memory module ECCs, the IRQ and
check_deps() functions are being made available to all the memory
buffers. Move them outside of the OCRAM only area.
Signed-off-by: Thor Thayer
---
v2 New patch. Move shared functions outside OCRAM only area.
v3 C
From: Thor Thayer
Add the device tree entries needed to support the Altera Ethernet
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No change
v3 Add interrupts for SBERR and DBERR.
v4 No change
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 16
1 fil
From: Thor Thayer
Separate the device match arrays for each platform to prevent
CycloneV matches when calling of_platform_populate() on the
Arria10 ECC manager node.
If the SDRAM is a child node of ECC manager, call probe function
via of_platform_populate().
Signed-off-by: Thor Thayer
---
driv
From: Thor Thayer
Designate the ECC Manager as an interrupt controller and add child
interrupts.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindi
From: Thor Thayer
Changes to support IRQ controller implementation including adding
new property irq-controller to eccmgr and adding IRQ property
to children.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10.dtsi |6 ++
1 file changed, 6 insertions(+)
diff --git a/arch
From: Thor Thayer
Changes to support ECC Manager as SDRAM IRQ parent by
1) updating IRQ property values to correct child IRQs
2) moving node under ECC Manager.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 13 +++--
1 file changed, 7 insertions(+), 6 deletio
From: Thor Thayer
To better support child devices, the ECC manager needs to be
implemented as an IRQ controller.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c | 162 +---
drivers/edac/altera_edac.h |5 +-
2 files changed, 125 insertions(
From: Thor Thayer
The Arria10 IRQs for each peripheral ECC block funnel into 2 IRQs
[1 for single bit errors (SBERR) and 1 for double bit errors (DBERR)]
which are better handled by the IRQ controller and IRQ domain
framework than the IRQ handler in the current implementation.
The IRQ numbers (h
From: Thor Thayer
In preparation for additional memory module ECCs, the
IRQ function will check a panic flag before doing a
kernel panic on double bit errors. ECCs on buffers
will not cause a kernel panic on DBERRs.
Signed-off-by: Thor Thayer
---
v2 New patch. Add panic flag to IRQ function.
-
From: Thor Thayer
This patch set adds the memory initialization functions for Altera's
Arria10 peripherals, the first of which is the Ethernet EDAC. The
ECC memory init functions are common to all the peripheral memory
buffers.
Thor Thayer (7):
EDAC, altera: Check parent status for Arria10 EDA
From: Thor Thayer
In preparation for the Arria10 ECC modules, check the status
of the parent in the device tree to ensure the block is enabled.
Skip if no parent phandle is set in the device tree.
Signed-off-by: Thor Thayer
---
v2 No change
---
drivers/edac/altera_edac.c |9 +
1 f
From: Thor Thayer
Add Altera Arria10 Ethernet FIFO memory EDAC support.
Signed-off-by: Thor Thayer
---
v2 Remove (void *) cast from altr_edac_device_of_match[]
Addition of panic flag to private data.
---
drivers/edac/Kconfig |7 ++
drivers/edac/altera_edac.c | 159 +
From: Thor Thayer
Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No Change
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 24
1 file changed, 24 insertions(+)
diff --git a
From: Thor Thayer
Add the device tree entries needed to support the Altera Ethernet
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2 No change
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 36
1 file changed, 36 insertions(+)
diff --gi
From: Thor Thayer
In preparation for additional memory module ECCs, the IRQ and
check_deps() functions are being made available to all the
memory buffers. Move it outside of the OCRAM only area.
Signed-off-by: Thor Thayer
---
v2 New patch. Move shared functions outside OCRAM only area.
---
dr
From: Thor Thayer
In preparation for additional memory module ECCs, add the
memory initialization functions.
Signed-off-by: Thor Thayer
---
v2: Specify INTMODE selection -> IRQ on each ECC error.
Insert functions above memory-specific functions so that function
declarations are not requ
From: Thor Thayer
Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.
Signed-off-by: Thor Thayer
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 24
1 file changed, 24 insertions(+)
diff --git a/Documentation/dev
From: Thor Thayer
In preparation for additional memory module ECCs, add the
memory initialization functions.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c | 152
drivers/edac/altera_edac.h |3 +
2 files changed, 155 insertions(+)
d
From: Thor Thayer
Add the device tree entries needed to support the Altera Ethernet
FIFO buffer EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
arch/arm/boot/dts/socfpga_arria10.dtsi | 36
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/
From: Thor Thayer
In preparation for the Arria10 ECC modules, check the status
of the parent in the device tree to ensure the block is enabled.
Skip if no parent phandle is set in the device tree.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c |9 +
1 file changed, 9 ins
From: Thor Thayer
Add Altera Arria10 Ethernet FIFO memory EDAC support.
Signed-off-by: Thor Thayer
---
drivers/edac/Kconfig |7 ++
drivers/edac/altera_edac.c | 153
drivers/edac/altera_edac.h | 14
3 files changed, 174 insertions(+
From: Thor Thayer
In preparation for additional memory module ECCs, the
IRQ declaration is being made available to everyone.
Move it outside of the OCRAM only area.
Signed-off-by: Thor Thayer
---
drivers/edac/altera_edac.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff -
This patch set adds the memory initialization functions for Altera's
Arria10 peripherals, the first of which is the Ethernet EDAC. The
first 3 patches add the memory initialization functionality. The
last 3 patches add Ethernet EDAC support.
[PATCH 1/6] EDAC, altera: Check parent status for Arria1
From: Thor Thayer
This series of patches adds the Arria10 OCRAM EDAC support
Thor Thayer (7):
EDAC, altera: New file operations for Arria10 ECC modules
EDAC, altera: Add register offset for ECC Enable
EDAC, altera: Make OCRAM ECC dependency check generic
Documentation: dt: socfpga: Add A
From: Thor Thayer
Add the device tree bindings needed to support the Altera On-Chip
RAM ECC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2: Align Required Properties descriptions
---
.../bindings/arm/altera/socfpga-eccmgr.txt | 10 ++
1 file changed, 10 insertions(+)
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, new file
operations are used because the Arria10 IRQ trigger mechanism
is different than Cyclone5/Arria5 and Arria10 L2 cache.
Add new pointer for file operations function to ecc data
structure and point to current file operations
From: Thor Thayer
In preparation for the Arria10 peripheral ECCs, a register
offset from the ECC base was added to the private data
structure to index to the ECC enable register.
Signed-off-by: Thor Thayer
---
v2: No change
---
drivers/edac/altera_edac.c |3 ++-
drivers/edac/altera_edac.h
From: Thor Thayer
Enable ECC for Arria10 On-Chip RAM on machine startup. The ECC has to
be enabled and memory initialized before data is stored in memory
otherwise the ECC will fail on reads.
Signed-off-by: Thor Thayer
---
v2: Add Arria10 ECC block initialization locally.
---
arch/arm/mach-soc
From: Thor Thayer
Add the device tree entries needed to support the Altera On-Chip
RAM EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer
---
v2: No change
---
arch/arm/boot/dts/socfpga_arria10.dtsi |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10
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