From: Suravee Suthikulpanit
Since PCIe is using SMMUv1 which only supports 15-bit stream ID,
only 7-bit PCI bus id is used to specify stream ID. Therefore,
we only limit the PCI bus range to 0x7f.
Signed-off-by: Suravee Suthikulpanit
---
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 2 +-
1 f
From: Suravee Suthikulpanit
AMD Seattle should support 40-bit DMA.
Signed-off-by: Suravee Suthikulpanit
---
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
b/arch/arm64/boo
From: Suravee Suthikulpanit
This patch set mainly fixes up the dma-ranges and pci bus range.
Please see each patch for more details.
Suravee Suthikulpanit (2):
arm64: amd-seattle: Fix dma-ranges property
arm64: amd-seattle: Fix PCI bus range due to SMMU limitation
arch/arm64/boot/dts/amd/a
From: Suravee Suthikulpanit
Initial revision of device tree for AMD Seattle Development platform.
Cc: Arnd Bergmann
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Thomas Lendacky
Signed-off-by: Joel Schopp
---
V5
From: Suravee Suthikulpanit
Initial revision of device tree for AMD Seattle platform.
Cc: Arnd Bergmann
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Thomas Lendacky
Signed-off-by: Joel Schopp
---
V4 Changes:
From: Suravee Suthikulpanit
This patch checks if the parent domain is NULL before recursively freeing
irqs in the parent domains.
In this case, GICv2m is freeing irqs in parent (GIC), which calls
irq_domain_free_irqs_top. This fixes the crash below:
Unble to handle kernel NULL pointer dereferen
From: Suravee Suthikulpanit
In the pci_scan_root_bus, pci_bus is created and passed down to:
pci_scan_child_bus
pci_scan_bridge
pci_add_new_bus
pci_alloc_child_bus
In pci_alloc_child_bus, the parent's msi_chip is propagated to child,
and the referenced by PCI devi
From: Suravee Suthikulpanit
This patch set introduces a new callback function to allow PCI host drivers
to specify MSI controller to be used for the child buses / devices.
This is reabased from:
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
pci/host-generic
Changes from V1:
From: Suravee Suthikulpanit
This patch introduces a new DT binding, msi-parent, which can
be used to specify MSI-parent phandle for a particular PCI
generic host controller.
Also, it implements and registers set_msi_parent callback.
Cc: Bjorn Helgass
Cc: Liviu Dudau
Cc: Will Deacon
Cc: Loren
From: Suravee Suthikulpanit
This patch implement set_msi_parent callback for PCI generic host controller.
Cc: Bjorn Helgass
Cc: Liviu Dudau
Cc: Lorenzo Pieralisi
Signed-off-by: Suravee Suthikulpanit
---
drivers/pci/host/pci-host-generic.c | 14 ++
1 file changed, 14 insertions(+
From: Suravee Suthikulpanit
In the pci_scan_root_bus, pci_bus is created and passed down to:
pci_scan_child_bus
pci_scan_bridge
pci_add_new_bus
pci_alloc_child_bus
In pci_alloc_child_bus, the parent's msi_chip is propagated to child,
and the referenced by PCI devi
From: Suravee Suthikulpanit
This patch set introduces a new callback function to allow PCI host drivers
to specify MSI controller to be used for the child buses / devices.
This is reabased from:
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
pci/host-generic
Suravee Suthikul
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in ARM
From: Suravee Suthikulpanit
Add a helper function to set irq type in parent irq domain.
Signed-off-by: Suravee Suthikulpanit
---
include/linux/irq.h | 1 +
kernel/irq/chip.c | 10 ++
2 files changed, 11 insertions(+)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 6159
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This patch adopt the new hierarchy irq domain, and is rebased from:
Git tree :
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platfo
From: Suravee Suthikulpanit
Add a helper function to set irq type in parent irq domain.
Signed-off-by: Suravee Suthikulpanit
---
include/linux/irq.h | 1 +
kernel/irq/chip.c | 10 ++
2 files changed, 11 insertions(+)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 6159
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This patch set is rebased from:
Git tree :
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
Git branch : domain_hier
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in ARM
From: Suravee Suthikulpanit
Initial revision of device tree for AMD Seattle platform
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Thomas Lendacky
Signed-off-by: Joel Schopp
---
Change in V3:
* Change sata compatible-id to
From: Suravee Suthikulpanit
Initial revision of device tree for AMD Seattle platform
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Cc: Rob Herring
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Thomas Lendacky
Signed-off-by: Joel Schopp
---
Change in V2:
* Re-order the
From: Suravee Suthikulpanit
Initial revision of device tree for AMD Seattle platform
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Cc: Rob Herring
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Thomas Lendacky
Signed-off-by: Joel Schopp
---
arch/arm64/Kconfig
From: Suravee Suthikulpanit
Initial revision of device tree for AMD Seattle platform
Cc: Rob Herring
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Thomas Lendacky
Signed-off-by: Joel Schopp
---
arch/arm64/boot/dts/Makefile
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in ARM
From: Suravee Suthikulpanit
When specify PCI_PROBE_ONLY, the resource parent does not get assigned.
Therefore, pci_enable_resources() return error saying that
"BAR x not claimed".
Note: This same logic is also used in the arch/arm/kernel/bios32.c
Cc: Liviu Dudau
Cc: Bjorn Helgaas
Cc: Will Dea
From: Suravee Suthikulpanit
This is an RFC to introduce support for AMD Seattle ARM64 platform.
It is also intended to provide support for validating Liviu's PCI patch series:
[PATCH v12 00/12] Support for creating generic PCI host bridges from DT
https://lkml.org/lkml/2014/9/23/852
It
From: Suravee Suthikulpanit
This patch adds ARM64 support to the generic PCI host driver.
For MSI support, it adds new device tree binding "msi-parent",
which should point to corresponded msi-controller.
Cc: Will Deacon
Cc: Liviu Dudau
Cc: Bjorn Helgaas
Cc: Mark Rutland
Cc: Catalin Marinas
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in ARM
From: Suravee Suthikulpanit
This patch implelments the ARM64 version of arch_setup_msi_irqs(),
which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1.
Signed-off-by: Suravee Suthikulpanit
Acked-by: Marc Zyngier
Cc: Mark Rutland
Cc: Jason Cooper
Cc: Catalin Marinas
Cc: Will Deacon
---
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports for ARM64:
[PATCH v11 00/10] Support for creati
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in ARM
From: Suravee Suthikulpanit
This patch implelments the ARM64 version of arch_setup_msi_irqs(),
which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1.
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Suravee Suthikulpanit
---
arch
From: Suravee Suthikulpanit
NOTE: Resend w/ proper subject for the 2/2 patch.
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports f
From: Suravee Suthikulpanit
This patch implelments the ARM64 version of arch_setup_msi_irqs(),
which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1.
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Suravee Suthikulpanit
---
arch
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in ARM
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports for ARM64:
[PATCH v10 00/10] Support for creati
From: Suravee Suthikulpanit
As a follow up of the email thread:
[PATCH v3 00/17] Introduce ACPI for ARM64 based on ACPI 5.1
https://lkml.org/lkml/2014/9/1/446
Besides Hanjun Guo's patches above, these are the additional patches required
to boot AMD Seattle platform with full ACPI suppor
From: Mark Salter
Commit 86c8b27a01cf:
"arm64: ignore DT memreserve entries when booting in UEFI mode
prevents early_init_fdt_scan_reserved_mem() from being called for
arm64 kernels booting via UEFI. This was done because the kernel
will use the UEFI memory map to determine reserved memory regi
From: Ard Biesheuvel
If we cannot relocate the kernel Image to its preferred offset of base of DRAM
plus TEXT_OFFSET, instead relocate it to the lowest available 2 MB boundary plus
TEXT_OFFSET. We may lose a bit of memory at the low end, but we can still
proceed normally otherwise.
Acked-by: Mar
From: Grame Gregory
This is a subset of pl011 UART which does not supprt DMA or baud rate
changing.
It is specified in the Server Base System Architecture document from
ARM.
Signed-off-by: Graeme Gregory
---
drivers/tty/Kconfig| 6 +
drivers/tty/Makefile | 1 +
drivers/tty/sbsauart.
From: Suravee Suthikulpanit
This patch adds ACPI match table in ahci_platform. The table includes
the acpi_device_id to match AMD Seattle SATA controller with following
asl structure in DSDT:
Device (SATA0)
{
Name(_HID, "AMDI0600")// Seattle AHSATA
Name (_CCA, 1)
From: Suravee Suthikulpanit
This patch extend GICv2m MSI to support multiple MSI in ARM64.
This requires the common arch_setup_msi_irqs() to be overwriten
with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and
nvec > 1.
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
Cc: Catali
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in ARM
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports for ARM64:
* https://lkml.org/lkml/2014/8/12/3
From: Suravee Suthikulpanit
This patch extend GICv2m MSI to support multiple MSI in ARM64.
This requires the common arch_setup_msi_irqs() to be overwriten
with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and
nvec > 1.
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
Cc: Catali
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in ARM
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports for ARM64:
* https://lkml.org/lkml/2014/8/12/3
From: Suravee Suthikulpanit
This patch adds ACPI support for non-PCI SATA contoller in ahci_platform driver.
It adds ACPI matching table in ahci_platform to support AMD Seattle SATA
controller
with following ASL structure in DSDT:
Device (SATA0)
{
Name(_HID, "AMDI0600")// Seat
From: Suravee Suthikulpanit
This patch extend GICv2m MSI to support multiple MSI in ARM64.
This requires the common arch_setup_msi_irqs() to be overwriten
with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and
nvec > 1.
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
Cc: Catali
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in ARM
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the V7 of"Add support for PCI in
AArch64"
(https://lkml.org/lkml/2014/3/14/320).
Changes in V4:
* Re
From: Suravee Suthikulpanit
This patch remove register index 4 in gic binding, and
introduce the "v2m" subnode. It also changes in the
gic_of_init function to probe for v2m subnode before calling
the gicv2m_of_init.
Besides, this patch also moves the "struct msi_chip" from
"struct gic_chip_data"
From: Suravee Suthikulpanit
This patch reverts the static declaration of various irq-gic
functions introduced in the fe7ac63fe5393b205b94247239f3d0686a65ee0a
Signed-off-by: Suravee Suthikulpanit
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
---
drivers/irqchip/irq-gic.c | 10 +-
From: Suravee Suthikulpanit
This patch remove the matching name gic-400-v2m.
It will use the "gic-400" instead
Signed-off-by: Suravee Suthikulpanit
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
---
drivers/irqchip/irq-gic-v2m.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/driv
From: Suravee Suthikulpanit
Remove irq-gic-v2m.h file which is no longer used
Signed-off-by: Suravee Suthikulpanit
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
---
drivers/irqchip/irq-gic-v2m.h | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v
From: Suravee Suthikulpanit
This patch set reworks the GICv2m initialization based on Marc Zyngier
review comments.
* Rebase to git://git.infradead.org/users/jcooper/linux.git irqchip/gic-v2m
Suravee Suthikulpanit (1):
irqchip/gic-v2m: Restructure the initalization code for v2m
Documentatio
From: Suravee Suthikulpanit
It's not quite clear that msi-controller is already checked
by of_msi_chip_add. So, this patch add a note to clarify.
Also, clean up redundant logic and unnecessary pr_info.
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
Cc: Catalin Marinas
Cc: Will Deacon
S
From: Suravee Suthikulpanit
This patch extend GICv2m MSI to support multiple MSI in ARM64.
This requires the common arch_setup_msi_irqs() to be overwriten
with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and
nvec > 1.
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
Cc: Catali
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frames. This patch introduces support for
the non-secure GICv2m register frame.
The driver currently matchs "arm,gic-400-plus" in device tree binding,
which implements GICv2m.
The "m
From: Suravee Suthikulpanit
This patch restructures the code to prepare for future MSI support.
It moves the declaration of structures and functions into the header file,
and omit the static prefix.
Since we are planing to have different irq_chip for GICv2m, the patch adds
irq_chip pointer in th
From: Suravee Suthikulpanit
Add new Irqchip declaration for GIC400. This was mentioned in
gic binding documentation, but there is not code to support it.
Signed-off-by: Suravee Suthikulpanit
---
drivers/irqchip/irq-gic.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the V7 of"Add support for PCI in
AArch64"
(https://lkml.org/lkml/2014/3/14/320).
Changes in V3:
* Re
From: Suravee Suthikulpanit
This patch restructures the code to prepare for future MSI support.
It moves the declaration of structures and functions into the header file,
and omit the static prefix.
Since we are planing to have different irq_chip for GIC, the patch adds
irq_chip pointer in the g
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frames. This patch introduces support for
the non-secure GICv2m register frame.
The driver currently matchs "arm,gic-400-plus" in device tree binding,
which implements GICv2m.
The "m
From: Suravee Suthikulpanit
Add new Irqchip declaration for GIC400. This was mentioned in
gic binding documentation, but there is not code to support it.
Signed-off-by: Suravee Suthikulpanit
---
drivers/irqchip/irq-gic.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400 (e.g. gic-400+).
This depends on and has been tested with the V7 of "Add support for PCI in
AArch64"
(https://lkml.org/lkml/2014/3/14/320).
Change
From: Suravee Suthikulpanit
Add new Irqchip declaration for GIC400. This was mentioned in
gic binding documentation, but there is not code to support it.
Signed-off-by: Suravee Suthikulpanit
---
drivers/irqchip/irq-gic.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the V7 of "Add support for PCI in
AArch64"
(https://lkml.org/lkml/2014/3/14/320).
Suravee Suthikulpanit
From: Suravee Suthikulpanit
GICv2m extends GICv2 to support MSI(-X) with a new set of register frames.
This patch introduces support for the non-secure GICv2m register frame.
This is optional. It uses the "msi-controller" keyword in ARM GIC
devicetree binding to indentify GIC driver that it shou
From: Suravee Suthikulpanit
Instead of doing the check here, this should be handled
in the common AHCI platform code.
Signed-off-by: Suravee Suthikulpanit
Suggested-by: Bartlomiej Zolnierkiewicz
Cc: Loc Ho
Cc: Tuan Phan
Cc: Suman Triphati
---
drivers/ata/ahci_xgene.c | 10 --
1 fil
From: Suravee Suthikulpanit
V2:
- Changes based on review comments from Hans and Bartlomiej.
- Remove the logic in ahci_xgene as suggested by Bartlomiej.
Suravee Suthikulpanit (2):
ata: Check and set 64-bit DMA mask for platform AHCI driver
ahci/xgene: Remove logic to set 64-
From: Suravee Suthikulpanit
The current platform AHCI driver does not set the dma_mask correctly
for 64-bit DMA capable AHCI controller. This patch checks the AHCI
capability bit and set the dma_mask and coherent_dma_mask accordingly.
Signed-off-by: Suravee Suthikulpanit
Reviewed-by: Bartlomiej
From: Suravee Suthikulpanit
Arm64 does not define dma_get_required_mask() function.
Therefore, it should not define the ARCH_HAS_DMA_GET_REQUIRED_MASK.
This causes build errors in some device drivers (e.g. mpt2sas)
Signed-off-by: Suravee Suthikulpanit
---
arch/arm64/include/asm/dma-mapping.h |
From: Suravee Suthikulpanit
The current platform AHCI drier does not set the dma_mask correctly
for 64-bit DMA capable AHCI controller. This patch checks the AHCI
capability bit and set the dma_mask and coherent_dma_mask accordingly.
Signed-off-by: Suravee Suthikulpanit
---
drivers/ata/libahc
From: Jay Cornwall
Do not disassociate the process page tables from a PASID during VM
invalidation. Invalidate the IOMMU TLB and IOTLBs before invalidation.
L2 translations may fail during VM range invalidation. The current
implementation associates an empty page table with a PASID within
the cr
From: Myron Stowe
The quirk is used for fixing up the numa_node information in sysfs for AMD
hostbridge
devices (i.e. PCI device 00:[18-1f].x). However, this is currently unused.
and is becoming maintenance burden. Therefore, it is removed.
Signed-off-by: Myron Stowe
Cc: Borislav Petkov
Cc:
From: Myron Stowe
The vast majority of platforms are not supplying ACPI _PXM (proximity)
information corresponding to host bridge (PNP0A03/PNP0A08) devices
resulting in sysfs "numa_node" values of -1 (NUMA_NO_NODE) [1]:
# for i in /sys/devices/pci\:00/*/numa_node; do cat $i; done | uniq
-
From: Suravee Suthikulpanit
This patch fixes the numa_node information in sysfs for PCI root
on AMD family15h platforms (currently showing -1) by adding
the hostbridge in the list of probed devices to be used for initializing
pci_root_info structue.
Signed-off-by: Suravee Suthikulpanit
Signed-o
From: Suravee Suthikulpanit
early_root_info_init is now deprecated in favor of info in ACPI.
Therefore, this patch adds note stating the deprecation.
Also, adding some clean up.
There is no functional change
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/pci/amd_bus.c | 69
From: Suravee Suthikulpanit
This in the V4 of the patch set which trys to fixed up numa_node for AMD
hostbridges.
This topic was discussed in the following threads:
V1: https://lkml.org/lkml/2014/3/5/898
V2: https://lkml.org/lkml/2014/4/18/623
V3: https://lkml.org/lkml/2014/5/7/588
Change from
From: Myron Stowe
The vast majority of platforms are not supplying ACPI _PXM (proximity)
information corresponding to host bridge (PNP0A03/PNP0A08) devices
resulting in sysfs "numa_node" values of -1 (NUMA_NO_NODE) [1]:
# for i in /sys/devices/pci\:00/*/numa_node; do cat $i; done | uniq
-
From: Myron Stowe
The quirk is used for fixing up the numa_node information in sysfs for AMD
hostbridge
devices (i.e. PCI device 00:[18-1f].x). However, this is currently unused.
and is becoming maintenance burden. Therefore, it is removed.
Signed-off-by: Myron Stowe
Cc: Borislav Petkov
Cc:
From: Suravee Suthikulpanit
This in the V3 of the patch set which trys to fixed up numa_node for AMD
hostbridges.
This topic was discussed in the following threads:
V1: https://lkml.org/lkml/2014/3/5/898
V2: https://lkml.org/lkml/2014/4/18/623
Change from V2:
As requested by Bjorn, the patch s
From: Suravee Suthikulpanit
This patch fixes the numa_node information in sysfs for PCI root
on AMD family15h platforms (currently showing -1) by adding
the hostbridge in the list of probed devices to be used for initializing
pci_root_info structue.
This mechanism is now deprecated in favor of i
From: Jay Cornwall
get_user_pages requires caller to hold a read lock on mmap_sem.
Signed-off-by: Jay Cornwall
Signed-off-by: Suravee Suthikulpanit
---
drivers/iommu/amd_iommu_v2.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/amd_iommu_v2.c b/drivers/iommu/amd_iommu_
From: Suravee Suthikulpanit
In reality, the spec can only support 16-bit PASID since
INVALIDATE_IOTLB_PAGES and COMPLETE_PPR_REQUEST commands only allow 16-bit
PASID. So, we updated the PASID_MASK accordingly and invoke BUG_ON
if the hardware is reporting PASmax more than 16-bit.
Besides, max PA
From: Suravee Suthikulpanit
This patch adds supports for additional MMIO ranges (16 ranges)
Also, each MMIO base/limit can now supports upto 48-bit MMIO address.
However, this requires initializing the ECS sooner since the new registers
are in the ECS ranges.
This applies for AMD family15h and l
From: Suravee Suthikulpanit
AMD hostbridges are gnenerally show up as PCI device 0:18.0.
This patch adds logic to automatically probe the device at
this location and check PCI device class code.
This patch should support AMD hostbridges from AMD platforms
(K8, family10h, 11h, 12h, 14h 15h and 1
From: Suravee Suthikulpanit
The current code only supports upto AMD hostbridge for family11h.
This causes PCI numa_node information to be reported incorrectly
for newer family with multi sockets.
This patch set introduces the logic to discover AMD hostbridges.
Note:
* Patch 1 and 2 are fun
From: Suravee Suthikulpanit
This patch doesn't have functional changes. List of changes including
* Refactoring the function early_fill_mp_bus_info into multiple helper
functions since it is getting long, and difficult to follow.
* Merge early_fill_mp_bus_info into amd_postcore_init since no
From: Suravee Suthikulpanit
According to IOMMUv2, max PASID is defined as ((2^(PASmax+1)) - 1)
using the value from MMIOx30[PASmax] register. The current does not
determine this correctly. Also the PASID_MASK should be determined by
max PASID instead of hardcoding value of 0xf.
Adding logic
From: Jay Cornwall
This patch corrects the PASID format in the INVALIDATE_IOTLB_PAGES
command, which was caused by incorrect information in
the AMD IOMMU Architectural Specification v2.01 document.
Incorrect format:
cmd->data[0][16:23] = PASID[7:0]
cmd->data[1][16:27] = PAS
From: Jacob Shin
Currently bp_len is given a default value of 4. Allow user to override it:
$ perf stat -e mem:0x1000/8
^
bp_len
If no value is given, it will default to 4 as it did before.
Signed-off-by: Jacob Shin
Signed-off-by: Sura
From: Jacob Shin
Clean up the logic for determining the breakpoint length
Signed-off-by: Jacob Shin
Signed-off-by: Suravee Suthikulpanit
---
arch/x86/kernel/hw_breakpoint.c | 25 +
1 file changed, 1 insertion(+), 24 deletions(-)
diff --git a/arch/x86/kernel/hw_breakpo
From: Jacob Shin
Signed-off-by: Jacob Shin
Signed-off-by: Suravee Suthikulpanit
---
tools/perf/tests/parse-events.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c
index 3cbd104..0c
From: Suravee Suthikulpanit
The following patchset enables hardware breakpoint bp_len greater than
HW_BREAKPOINT_LEN_8 on AMD Family 16h and later.
$ perf stat -e mem:0x1000/16:w a.out
^^
bp_len
This will count writes to [0x1000 ~ 0x1010
From: Jacob Shin
Implement hardware breakpoint address mask for AMD Family 16h and
above processors. CPUID feature bit indicates hardware support for
DRn_ADDR_MASK MSRs. These masks further qualify DRn/DR7 hardware
breakpoint addresses to allow matching of larger addresses ranges.
Valuable advic
From: Jacob Shin
Currently bp_len is given a default value of 4. Allow user to override it:
$ perf stat -e mem:0x1000/8
^
bp_len
If no value is given, it will default to 4 as it did before.
Signed-off-by: Jacob Shin
Signed-off-by: Sura
From: Jacob Shin
Implement hardware breakpoint address mask for AMD Family 16h and
above processors. CPUID feature bit indicates hardware support for
DRn_ADDR_MASK MSRs. These masks further qualify DRn/DR7 hardware
breakpoint addresses to allow matching of larger addresses ranges.
Valuable advic
From: Jacob Shin
Signed-off-by: Jacob Shin
Signed-off-by: Suravee Suthikulpanit
---
tools/perf/tests/parse-events.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c
index 48114d1..9b
From: Suravee Suthikulpanit
Frederic, this is the rebase of the V4 patch onto the linux-3.12.0-rc3
(linux.git),
and retest.
The following patchset enables hardware breakpoint bp_len greater than
HW_BREAKPOINT_LEN_8 on AMD Family 16h and later.
$ perf stat -e mem:0x1000/16:w a.out
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