[PATCH V5] perf/x86: Reset the dirty counter to prevent the leak for an RDPMC task

From: Kan Liang The counter value of a perf task may leak to another RDPMC task. For example, a perf stat task as below is running on CPU 0. perf stat -e 'branches,cycles' -- taskset -c 0 ./workload In the meantime, an RDPMC task, which is also running on CPU 0, may read the G

[tip: perf/core] perf/x86: Hybrid PMU support for counters

The following commit has been merged into the perf/core branch of tip: Commit-ID: d4b294bf84db7a84e295ddf19cb8e7f71b7bd045 Gitweb: https://git.kernel.org/tip/d4b294bf84db7a84e295ddf19cb8e7f71b7bd045 Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:46 -07:00 Committer

[tip: perf/core] perf/x86: Track pmu in per-CPU cpu_hw_events

The following commit has been merged into the perf/core branch of tip: Commit-ID: 61e76d53c39bb768ad264d379837cfc56b9e35b4 Gitweb: https://git.kernel.org/tip/61e76d53c39bb768ad264d379837cfc56b9e35b4 Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:43 -07:00 Committer

[tip: perf/core] perf/x86/intel: Hybrid PMU support for perf capabilities

The following commit has been merged into the perf/core branch of tip: Commit-ID: d0946a882e6220229a29f9031641e54379be5a1e Gitweb: https://git.kernel.org/tip/d0946a882e6220229a29f9031641e54379be5a1e Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:44 -07:00 Committer

[tip: perf/core] perf/x86: Hybrid PMU support for intel_ctrl

The following commit has been merged into the perf/core branch of tip: Commit-ID: fc4b8fca2d8fc8aecd58508e81d55afe4ed76344 Gitweb: https://git.kernel.org/tip/fc4b8fca2d8fc8aecd58508e81d55afe4ed76344 Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:45 -07:00 Committer

[tip: perf/core] perf/x86: Hybrid PMU support for hardware cache event

The following commit has been merged into the perf/core branch of tip: Commit-ID: 0d18f2dfead8dd63bf1186c9ef38528d6a615a55 Gitweb: https://git.kernel.org/tip/0d18f2dfead8dd63bf1186c9ef38528d6a615a55 Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:48 -07:00 Committer

[tip: perf/core] perf/x86: Hybrid PMU support for unconstrained

The following commit has been merged into the perf/core branch of tip: Commit-ID: eaacf07d1116f6bf3b93b265515fccf2301097f2 Gitweb: https://git.kernel.org/tip/eaacf07d1116f6bf3b93b265515fccf2301097f2 Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:47 -07:00 Committer

[tip: perf/core] perf/x86: Hybrid PMU support for event constraints

The following commit has been merged into the perf/core branch of tip: Commit-ID: 24ee38ffe61a68fc35065fcab1908883a34c866b Gitweb: https://git.kernel.org/tip/24ee38ffe61a68fc35065fcab1908883a34c866b Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:49 -07:00 Committer

[tip: perf/core] perf/x86: Hybrid PMU support for extra_regs

The following commit has been merged into the perf/core branch of tip: Commit-ID: 183af7366b4e813ee4e0b995ff731e3ac28251f0 Gitweb: https://git.kernel.org/tip/183af7366b4e813ee4e0b995ff731e3ac28251f0 Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:50 -07:00 Committer

[tip: perf/core] perf/x86/intel: Factor out intel_pmu_check_num_counters

The following commit has been merged into the perf/core branch of tip: Commit-ID: b8c4d1a87610ba20da1abddb7aacbde0b2817c1a Gitweb: https://git.kernel.org/tip/b8c4d1a87610ba20da1abddb7aacbde0b2817c1a Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:51 -07:00 Committer

[tip: perf/core] perf/x86/intel: Factor out intel_pmu_check_event_constraints

The following commit has been merged into the perf/core branch of tip: Commit-ID: bc14fe1beeec1d80ee39f03019c10e130c8d376b Gitweb: https://git.kernel.org/tip/bc14fe1beeec1d80ee39f03019c10e130c8d376b Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:52 -07:00 Committer

[tip: perf/core] perf/x86/intel: Factor out intel_pmu_check_extra_regs

The following commit has been merged into the perf/core branch of tip: Commit-ID: 34d5b61f29eea656be4283213273c33d5987e4d2 Gitweb: https://git.kernel.org/tip/34d5b61f29eea656be4283213273c33d5987e4d2 Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:53 -07:00 Committer

[tip: perf/core] perf/x86: Factor out x86_pmu_show_pmu_cap

The following commit has been merged into the perf/core branch of tip: Commit-ID: e11c1a7eb302ac8f6f47c18fa662546405a5fd83 Gitweb: https://git.kernel.org/tip/e11c1a7eb302ac8f6f47c18fa662546405a5fd83 Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:55 -07:00 Committer

[tip: perf/core] perf/x86: Remove temporary pmu assignment in event_init

The following commit has been merged into the perf/core branch of tip: Commit-ID: b98567298bad891774054113690b30bd90d5738d Gitweb: https://git.kernel.org/tip/b98567298bad891774054113690b30bd90d5738d Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:54 -07:00 Committer

[tip: perf/core] perf/x86: Register hybrid PMUs

The following commit has been merged into the perf/core branch of tip: Commit-ID: d9977c43bff895ed49a9d25e1f382b0a98bb271f Gitweb: https://git.kernel.org/tip/d9977c43bff895ed49a9d25e1f382b0a98bb271f Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:56 -07:00 Committer

[tip: perf/core] perf/x86: Add structures for the attributes of Hybrid PMUs

The following commit has been merged into the perf/core branch of tip: Commit-ID: a9c81ccdf52dd73a20178c40bca34cf52991fdea Gitweb: https://git.kernel.org/tip/a9c81ccdf52dd73a20178c40bca34cf52991fdea Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:57 -07:00 Committer

[tip: perf/core] perf/x86/intel: Add Alder Lake Hybrid support

The following commit has been merged into the perf/core branch of tip: Commit-ID: f83d2f91d2590318e083d05bd7b1beda2489050e Gitweb: https://git.kernel.org/tip/f83d2f91d2590318e083d05bd7b1beda2489050e Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:31:00 -07:00 Committer

[tip: perf/core] perf/x86/intel: Add attr_update for Hybrid PMUs

The following commit has been merged into the perf/core branch of tip: Commit-ID: 58ae30c29a370c09eb49e0007d881a9aed13c5a3 Gitweb: https://git.kernel.org/tip/58ae30c29a370c09eb49e0007d881a9aed13c5a3 Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:58 -07:00 Committer

[tip: perf/core] perf/x86: Support filter_match callback

The following commit has been merged into the perf/core branch of tip: Commit-ID: 3e9a8b219e4cc897dba20e19185d0471f129f6f3 Gitweb: https://git.kernel.org/tip/3e9a8b219e4cc897dba20e19185d0471f129f6f3 Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:30:59 -07:00 Committer

[tip: perf/core] perf: Extend PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE

The following commit has been merged into the perf/core branch of tip: Commit-ID: 55bcf6ef314ae8ba81bcd74aa760247b635ed47b Gitweb: https://git.kernel.org/tip/55bcf6ef314ae8ba81bcd74aa760247b635ed47b Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:31:01 -07:00 Committer

[tip: perf/core] perf/x86/intel/uncore: Add Alder Lake support

The following commit has been merged into the perf/core branch of tip: Commit-ID: 772ed05f3c5ce722b9de6c4c2dd87538a33fb8d3 Gitweb: https://git.kernel.org/tip/772ed05f3c5ce722b9de6c4c2dd87538a33fb8d3 Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:31:02 -07:00 Committer

[tip: perf/core] perf/x86/cstate: Add Alder Lake CPU support

The following commit has been merged into the perf/core branch of tip: Commit-ID: d0ca946bcf84e1f9847571923bb1e6bd1264f424 Gitweb: https://git.kernel.org/tip/d0ca946bcf84e1f9847571923bb1e6bd1264f424 Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:31:04 -07:00 Committer

[tip: perf/core] perf/x86/msr: Add Alder Lake CPU support

The following commit has been merged into the perf/core branch of tip: Commit-ID: 19d3a81fd92dc9b73950564955164ecfd0dfbea1 Gitweb: https://git.kernel.org/tip/19d3a81fd92dc9b73950564955164ecfd0dfbea1 Author:Kan Liang AuthorDate:Mon, 12 Apr 2021 07:31:03 -07:00 Committer

[tip: perf/core] perf/x86: Move cpuc->running into P4 specific code

The following commit has been merged into the perf/core branch of tip: Commit-ID: 46ade4740bbf9bf4e804ddb2c85845cccd219f3c Gitweb: https://git.kernel.org/tip/46ade4740bbf9bf4e804ddb2c85845cccd219f3c Author:Kan Liang AuthorDate:Wed, 14 Apr 2021 07:36:29 -07:00 Committer

[tip: perf/core] perf/x86: Reset the dirty counter to prevent the leak for an RDPMC task

The following commit has been merged into the perf/core branch of tip: Commit-ID: 01fd9661e168de7cfc4f947e7220fca0e6791999 Gitweb: https://git.kernel.org/tip/01fd9661e168de7cfc4f947e7220fca0e6791999 Author:Kan Liang AuthorDate:Wed, 14 Apr 2021 07:36:30 -07:00 Committer

[PATCH] perf/x86/intel/uncore: Remove uncore extra PCI dev HSWEP_PCI_PCU_3

From: Kan Liang There may be a kernel panic on the Haswell server and the Broadwell server, if the snbep_pci2phy_map_init() return error. The uncore_extra_pci_dev[HSWEP_PCI_PCU_3] is used in the cpu_init() to detect the existence of the SBOX, which is a MSR type of PMON unit. The

[PATCH V4 2/2] perf/x86: Reset the dirty counter to prevent the leak for an RDPMC task

From: Kan Liang The counter value of a perf task may leak to another RDPMC task. For example, a perf stat task as below is running on CPU 0. perf stat -e 'branches,cycles' -- taskset -c 0 ./workload In the meantime, an RDPMC task, which is also running on CPU 0, may read the G

[PATCH V4 1/2] perf/x86: Move cpuc->running into P4 specific code

From: Kan Liang The 'running' variable is only used in the P4 PMU. Current perf sets the variable in the critical function x86_pmu_start(), which wastes cycles for everybody not running on P4. Move cpuc->running into the P4 specific p4_pmu_enable_event(). Add a static per-CP

[PATCH V3 2/2] perf/x86: Reset the dirty counter to prevent the leak for an RDPMC task

From: Kan Liang The counter value of a perf task may leak to another RDPMC task. For example, a perf stat task as below is running on CPU 0. perf stat -e 'branches,cycles' -- taskset -c 0 ./workload In the meantime, an RDPMC task, which is also running on CPU 0, may read the G

[PATCH V3 1/2] perf/x86: Move cpuc->running into P4 specific code

From: Kan Liang The 'running' variable is only used in the P4 PMU. Current perf sets the variable in the critical function x86_pmu_start(), which wastes cycles for everybody not running on P4. Move cpuc->running into the P4 specific p4_pmu_enable_event(). Add a static per-CP

[PATCH V6 16/25] perf/x86: Register hybrid PMUs

From: Kan Liang Different hybrid PMUs have different PMU capabilities and events. Perf should registers a dedicated PMU for each of them. To check the X86 event, perf has to go through all possible hybrid pmus. All the hybrid PMUs are registered at boot time. Before the registration, add

[PATCH V6 17/25] perf/x86: Add structures for the attributes of Hybrid PMUs

From: Kan Liang Hybrid PMUs have different events and formats. In theory, Hybrid PMU specific attributes should be maintained in the dedicated struct x86_hybrid_pmu, but it wastes space because the events and formats are similar among Hybrid PMUs. To reduce duplication, all hybrid PMUs will

[PATCH V6 15/25] perf/x86: Factor out x86_pmu_show_pmu_cap

From: Kan Liang The PMU capabilities are different among hybrid PMUs. Perf should dump the PMU capabilities information for each hybrid PMU. Factor out x86_pmu_show_pmu_cap() which shows the PMU capabilities information. The function will be reused later when registering a dedicated hybrid PMU

[PATCH V6 14/25] perf/x86: Remove temporary pmu assignment in event_init

From: Kan Liang The temporary pmu assignment in event_init is unnecessary. The assignment was introduced by commit 8113070d6639 ("perf_events: Add fast-path to the rescheduling code"). At that time, event->pmu is not assigned yet when initializing an event. The assignment is requ

[PATCH V6 11/25] perf/x86/intel: Factor out intel_pmu_check_num_counters

From: Kan Liang Each Hybrid PMU has to check its own number of counters and mask fixed counters before registration. The intel_pmu_check_num_counters will be reused later to check the number of the counters for each hybrid PMU. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86

[PATCH V6 08/25] perf/x86: Hybrid PMU support for hardware cache event

From: Kan Liang The hardware cache events are different among hybrid PMUs. Each hybrid PMU should have its own hw cache event table. Suggested-by: Peter Zijlstra (Intel) Signed-off-by: Kan Liang --- arch/x86/events/core.c | 5 ++--- arch/x86/events/perf_event.h | 9 + 2 files

[PATCH V6 10/25] perf/x86: Hybrid PMU support for extra_regs

From: Kan Liang Different hybrid PMU may have different extra registers, e.g. Core PMU may have offcore registers, frontend register and ldlat register. Atom core may only have offcore registers and ldlat register. Each hybrid PMU should use its own extra_regs. An Intel Hybrid system should

[PATCH V6 06/25] perf/x86: Hybrid PMU support for counters

From: Kan Liang The number of GP and fixed counters are different among hybrid PMUs. Each hybrid PMU should use its own counter related information. When handling a certain hybrid PMU, apply the number of counters from the corresponding hybrid PMU. When reserving the counters in the

[PATCH V6 04/25] perf/x86/intel: Hybrid PMU support for perf capabilities

From: Kan Liang Some platforms, e.g. Alder Lake, have hybrid architecture. Although most PMU capabilities are the same, there are still some unique PMU capabilities for different hybrid PMUs. Perf should register a dedicated pmu for each hybrid PMU. Add a new struct x86_hybrid_pmu, which saves

[PATCH V6 03/25] perf/x86: Track pmu in per-CPU cpu_hw_events

From: Kan Liang Some platforms, e.g. Alder Lake, have hybrid architecture. In the same package, there may be more than one type of CPU. The PMU capabilities are different among different types of CPU. Perf will register a dedicated PMU for each type of CPU. Add a 'pmu' variable in

[PATCH V6 23/25] perf/x86/msr: Add Alder Lake CPU support

From: Kan Liang PPERF and SMI_COUNT MSRs are also supported on Alder Lake. The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source. The patch has been tested on real hardware. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86

[PATCH V6 02/25] x86/cpu: Add helper function to get the type of the current hybrid CPU

irski Cc: Dave Hansen Cc: Kan Liang Cc: "Peter Zijlstra (Intel)" Cc: "Rafael J. Wysocki" Cc: "Ravi V. Shankar" Cc: Srinivas Pandruvada Cc: linux-kernel@vger.kernel.org Reviewed-by: Len Brown Reviewed-by: Tony Luck Acked-by: Borislav Petkov Signed-off-by: Ric

[PATCH V6 18/25] perf/x86/intel: Add attr_update for Hybrid PMUs

From: Kan Liang The attribute_group for Hybrid PMUs should be different from the previous cpu PMU. For example, cpumask is required for a Hybrid PMU. The PMU type should be included in the event and format attribute. Add hybrid_attr_update for the Hybrid PMU. Check the PMU type in is_visible

[PATCH V6 20/25] perf/x86/intel: Add Alder Lake Hybrid support

From: Kan Liang Alder Lake Hybrid system has two different types of core, Golden Cove core and Gracemont core. The Golden Cove core is registered to "cpu_core" PMU. The Gracemont core is registered to "cpu_atom" PMU. The difference between the two PMUs include: - Number of G

[PATCH V6 24/25] perf/x86/cstate: Add Alder Lake CPU support

From: Kan Liang Compared with the Rocket Lake, the CORE C1 Residency Counter is added for Alder Lake, but the CORE C3 Residency Counter is removed. Other counters are the same. Create a new adl_cstates for Alder Lake. Update the comments accordingly. The External Design Specification (EDS) is

[PATCH V6 19/25] perf/x86: Support filter_match callback

From: Kan Liang Implement filter_match callback for X86, which check whether an event is schedulable on the current CPU. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/core.c | 10 ++ arch/x86/events/perf_event.h | 1 + 2 files changed, 11 insertions

[PATCH V6 25/25] perf/x86/rapl: Add support for Intel Alder Lake

From: Zhang Rui Alder Lake RAPL support is the same as previous Sky Lake. Add Alder Lake model for RAPL. Reviewed-by: Andi Kleen Signed-off-by: Zhang Rui --- arch/x86/events/rapl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index f42a

[PATCH V6 22/25] perf/x86/intel/uncore: Add Alder Lake support

From: Kan Liang The uncore subsystem for Alder Lake is similar to the previous Tiger Lake. The difference includes: - New MSR addresses for global control, fixed counters, CBOX and ARB. Add a new adl_uncore_msr_ops for uncore operations. - Add a new threshold field for CBOX. - New PCIIDs for

[PATCH V6 21/25] perf: Extend PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE

From: Kan Liang Current Hardware events and Hardware cache events have special perf types, PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE. The two types don't pass the PMU type in the user interface. For a hybrid system, the perf subsystem doesn't know which PMU the events belong to.

[PATCH V6 12/25] perf/x86/intel: Factor out intel_pmu_check_event_constraints

From: Kan Liang Each Hybrid PMU has to check and update its own event constraints before registration. The intel_pmu_check_event_constraints will be reused later to check the event constraints of each hybrid PMU. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/intel

[PATCH V6 13/25] perf/x86/intel: Factor out intel_pmu_check_extra_regs

From: Kan Liang Each Hybrid PMU has to check and update its own extra registers before registration. The intel_pmu_check_extra_regs will be reused later to check the extra registers of each hybrid PMU. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/intel/core.c | 35

[PATCH V6 09/25] perf/x86: Hybrid PMU support for event constraints

From: Kan Liang The events are different among hybrid PMUs. Each hybrid PMU should use its own event constraints. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/core.c | 3 ++- arch/x86/events/intel/core.c | 5 +++-- arch/x86/events/intel/ds.c | 5 +++-- arch

[PATCH V6 07/25] perf/x86: Hybrid PMU support for unconstrained

From: Kan Liang The unconstrained value depends on the number of GP and fixed counters. Each hybrid PMU should use its own unconstrained. Suggested-by: Peter Zijlstra (Intel) Signed-off-by: Kan Liang --- arch/x86/events/intel/core.c | 2 +- arch/x86/events/perf_event.h | 11 +++ 2

[PATCH V6 05/25] perf/x86: Hybrid PMU support for intel_ctrl

From: Kan Liang The intel_ctrl is the counter mask of a PMU. The PMU counter information may be different among hybrid PMUs, each hybrid PMU should use its own intel_ctrl to check and access the counters. When handling a certain hybrid PMU, apply the intel_ctrl from the corresponding hybrid PMU

[PATCH V6 01/25] x86/cpufeatures: Enumerate Intel Hybrid Technology feature bit

CPUID. Thus, software (user space and kernel) can run and migrate to any CPU in the system as well as utilize any of the enumerated features without any change or special provisions. The main difference among CPUs in a hybrid processor are power and performance properties. Cc: Andi Kleen Cc: Kan

[PATCH V6 00/25] Add Alder Lake support for perf (kernel)

From: Kan Liang Changes since V5: - Add a new static_key_false "perf_is_hybrid" to indicate a hybrid system. Update hybrid() so we can get a pointer for the hybrid variables (Peter) (Patch 4 & 20) - Use (not change) the x86_pmu.intel_cap.pebs_output_p

[PATCH V5 25/25] perf/x86/rapl: Add support for Intel Alder Lake

From: Zhang Rui Alder Lake RAPL support is the same as previous Sky Lake. Add Alder Lake model for RAPL. Reviewed-by: Andi Kleen Signed-off-by: Zhang Rui --- arch/x86/events/rapl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index f42a

[PATCH V5 24/25] perf/x86/cstate: Add Alder Lake CPU support

From: Kan Liang Compared with the Rocket Lake, the CORE C1 Residency Counter is added for Alder Lake, but the CORE C3 Residency Counter is removed. Other counters are the same. Create a new adl_cstates for Alder Lake. Update the comments accordingly. The External Design Specification (EDS) is

[PATCH V5 21/25] perf: Introduce PERF_TYPE_HARDWARE_PMU and PERF_TYPE_HW_CACHE_PMU

From: Kan Liang Current Hardware events and Hardware cache events have special perf types, PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE. The two types don't pass the PMU type in the user interface. For a hybrid system, the perf subsystem doesn't know which PMU the events belong to.

[PATCH V5 23/25] perf/x86/msr: Add Alder Lake CPU support

From: Kan Liang PPERF and SMI_COUNT MSRs are also supported on Alder Lake. The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source. The patch has been tested on real hardware. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86

[PATCH V5 22/25] perf/x86/intel/uncore: Add Alder Lake support

From: Kan Liang The uncore subsystem for Alder Lake is similar to the previous Tiger Lake. The difference includes: - New MSR addresses for global control, fixed counters, CBOX and ARB. Add a new adl_uncore_msr_ops for uncore operations. - Add a new threshold field for CBOX. - New PCIIDs for

[PATCH V5 20/25] perf/x86/intel: Add Alder Lake Hybrid support

From: Kan Liang Alder Lake Hybrid system has two different types of core, Golden Cove core and Gracemont core. The Golden Cove core is registered to "cpu_core" PMU. The Gracemont core is registered to "cpu_atom" PMU. The difference between the two PMUs include: - Number of G

[PATCH V5 17/25] perf/x86: Add structures for the attributes of Hybrid PMUs

From: Kan Liang Hybrid PMUs have different events and formats. In theory, Hybrid PMU specific attributes should be maintained in the dedicated struct x86_hybrid_pmu, but it wastes space because the events and formats are similar among Hybrid PMUs. To reduce duplication, all hybrid PMUs will

[PATCH V5 18/25] perf/x86/intel: Add attr_update for Hybrid PMUs

From: Kan Liang The attribute_group for Hybrid PMUs should be different from the previous cpu PMU. For example, cpumask is required for a Hybrid PMU. The PMU type should be included in the event and format attribute. Add hybrid_attr_update for the Hybrid PMU. Check the PMU type in is_visible

[PATCH V5 19/25] perf/x86: Support filter_match callback

From: Kan Liang Implement filter_match callback for X86, which check whether an event is schedulable on the current CPU. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/core.c | 10 ++ arch/x86/events/perf_event.h | 1 + 2 files changed, 11 insertions

[PATCH V5 15/25] perf/x86: Factor out x86_pmu_show_pmu_cap

From: Kan Liang The PMU capabilities are different among hybrid PMUs. Perf should dump the PMU capabilities information for each hybrid PMU. Factor out x86_pmu_show_pmu_cap() which shows the PMU capabilities information. The function will be reused later when registering a dedicated hybrid PMU

[PATCH V5 16/25] perf/x86: Register hybrid PMUs

From: Kan Liang Different hybrid PMUs have different PMU capabilities and events. Perf should registers a dedicated PMU for each of them. To check the X86 event, perf has to go through all possible hybrid pmus. All the hybrid PMUs are registered at boot time. Before the registration, add

[PATCH V5 12/25] perf/x86/intel: Factor out intel_pmu_check_event_constraints

From: Kan Liang Each Hybrid PMU has to check and update its own event constraints before registration. The intel_pmu_check_event_constraints will be reused later to check the event constraints of each hybrid PMU. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/intel

[PATCH V5 05/25] perf/x86: Hybrid PMU support for intel_ctrl

From: Kan Liang The intel_ctrl is the counter mask of a PMU. The PMU counter information may be different among hybrid PMUs, each hybrid PMU should use its own intel_ctrl to check and access the counters. When handling a certain hybrid PMU, apply the intel_ctrl from the corresponding hybrid PMU

[PATCH V5 13/25] perf/x86/intel: Factor out intel_pmu_check_extra_regs

From: Kan Liang Each Hybrid PMU has to check and update its own extra registers before registration. The intel_pmu_check_extra_regs will be reused later to check the extra registers of each hybrid PMU. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/intel/core.c | 35

[PATCH V5 06/25] perf/x86: Hybrid PMU support for counters

From: Kan Liang The number of GP and fixed counters are different among hybrid PMUs. Each hybrid PMU should use its own counter related information. When handling a certain hybrid PMU, apply the number of counters from the corresponding hybrid PMU. When reserving the counters in the

[PATCH V5 08/25] perf/x86: Hybrid PMU support for hardware cache event

From: Kan Liang The hardware cache events are different among hybrid PMUs. Each hybrid PMU should have its own hw cache event table. The hw_cache_extra_regs is not part of the struct x86_pmu, the hybrid() cannot be applied here. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86

[PATCH V5 11/25] perf/x86/intel: Factor out intel_pmu_check_num_counters

From: Kan Liang Each Hybrid PMU has to check its own number of counters and mask fixed counters before registration. The intel_pmu_check_num_counters will be reused later to check the number of the counters for each hybrid PMU. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86

[PATCH V5 07/25] perf/x86: Hybrid PMU support for unconstrained

From: Kan Liang The unconstrained value depends on the number of GP and fixed counters. Each hybrid PMU should use its own unconstrained. Suggested-by: Peter Zijlstra (Intel) Signed-off-by: Kan Liang --- arch/x86/events/intel/core.c | 5 - arch/x86/events/perf_event.h | 1 + 2 files

[PATCH V5 14/25] perf/x86: Remove temporary pmu assignment in event_init

From: Kan Liang The temporary pmu assignment in event_init is unnecessary. The assignment was introduced by commit 8113070d6639 ("perf_events: Add fast-path to the rescheduling code"). At that time, event->pmu is not assigned yet when initializing an event. The assignment is requ

[PATCH V5 09/25] perf/x86: Hybrid PMU support for event constraints

From: Kan Liang The events are different among hybrid PMUs. Each hybrid PMU should use its own event constraints. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/core.c | 3 ++- arch/x86/events/intel/core.c | 5 +++-- arch/x86/events/intel/ds.c | 5 +++-- arch

[PATCH V5 10/25] perf/x86: Hybrid PMU support for extra_regs

From: Kan Liang Different hybrid PMU may have different extra registers, e.g. Core PMU may have offcore registers, frontend register and ldlat register. Atom core may only have offcore registers and ldlat register. Each hybrid PMU should use its own extra_regs. An Intel Hybrid system should

[PATCH V5 02/25] x86/cpu: Add helper function to get the type of the current hybrid CPU

irski Cc: Dave Hansen Cc: Kan Liang Cc: "Peter Zijlstra (Intel)" Cc: "Rafael J. Wysocki" Cc: "Ravi V. Shankar" Cc: Srinivas Pandruvada Cc: linux-kernel@vger.kernel.org Reviewed-by: Len Brown Reviewed-by: Tony Luck Acked-by: Borislav Petkov Signed-off-by: Ric

[PATCH V5 04/25] perf/x86/intel: Hybrid PMU support for perf capabilities

From: Kan Liang Some platforms, e.g. Alder Lake, have hybrid architecture. Although most PMU capabilities are the same, there are still some unique PMU capabilities for different hybrid PMUs. Perf should register a dedicated pmu for each hybrid PMU. Add a new struct x86_hybrid_pmu, which saves

[PATCH V5 03/25] perf/x86: Track pmu in per-CPU cpu_hw_events

From: Kan Liang Some platforms, e.g. Alder Lake, have hybrid architecture. In the same package, there may be more than one type of CPU. The PMU capabilities are different among different types of CPU. Perf will register a dedicated PMU for each type of CPU. Add a 'pmu' variable in

[PATCH V5 01/25] x86/cpufeatures: Enumerate Intel Hybrid Technology feature bit

CPUID. Thus, software (user space and kernel) can run and migrate to any CPU in the system as well as utilize any of the enumerated features without any change or special provisions. The main difference among CPUs in a hybrid processor are power and performance properties. Cc: Andi Kleen Cc: Kan

[PATCH V5 00/25] Add Alder Lake support for perf (kernel)

From: Kan Liang Changes since V4: - Put the X86_HYBRID_CPU_TYPE_ID_SHIFT over the function where it is used (Boris) (Patch 2) - Add Acked-by from Boris for Patch 1 & 2 - Fix a smatch warning, "allocate_fake_cpuc() warn: possible memory leak of 'cpuc'" (0-DAY test) (

[tip: perf/core] perf/x86/intel/uncore: Generic support for the MSR type of uncore blocks

The following commit has been merged into the perf/core branch of tip: Commit-ID: d6c754130435ab786711bed75d04a2388a6b4da8 Gitweb: https://git.kernel.org/tip/d6c754130435ab786711bed75d04a2388a6b4da8 Author:Kan Liang AuthorDate:Wed, 17 Mar 2021 10:59:34 -07:00 Committer

[tip: perf/core] perf/x86/intel/uncore: Parse uncore discovery tables

The following commit has been merged into the perf/core branch of tip: Commit-ID: edae1f06c2cda41edffc93de6aedc8ba8dc883c3 Gitweb: https://git.kernel.org/tip/edae1f06c2cda41edffc93de6aedc8ba8dc883c3 Author:Kan Liang AuthorDate:Wed, 17 Mar 2021 10:59:33 -07:00 Committer

[tip: perf/core] perf/x86/intel/uncore: Generic support for the PCI type of uncore blocks

The following commit has been merged into the perf/core branch of tip: Commit-ID: 42839ef4a20a4bda415974ff0e7d85ff540fffa4 Gitweb: https://git.kernel.org/tip/42839ef4a20a4bda415974ff0e7d85ff540fffa4 Author:Kan Liang AuthorDate:Wed, 17 Mar 2021 10:59:36 -07:00 Committer

[tip: perf/core] perf/x86/intel/uncore: Rename uncore_notifier to uncore_pci_sub_notifier

The following commit has been merged into the perf/core branch of tip: Commit-ID: 6477dc3934775f82a571fac469fd8c348e611095 Gitweb: https://git.kernel.org/tip/6477dc3934775f82a571fac469fd8c348e611095 Author:Kan Liang AuthorDate:Wed, 17 Mar 2021 10:59:35 -07:00 Committer

[tip: perf/core] perf/x86/intel/uncore: Generic support for the MMIO type of uncore blocks

The following commit has been merged into the perf/core branch of tip: Commit-ID: c4c55e362a521d763356b9e02bc9a4348c71a471 Gitweb: https://git.kernel.org/tip/c4c55e362a521d763356b9e02bc9a4348c71a471 Author:Kan Liang AuthorDate:Wed, 17 Mar 2021 10:59:37 -07:00 Committer

[PATCH V4 25/25] perf/x86/rapl: Add support for Intel Alder Lake

From: Zhang Rui Alder Lake RAPL support is the same as previous Sky Lake. Add Alder Lake model for RAPL. Reviewed-by: Andi Kleen Signed-off-by: Zhang Rui --- arch/x86/events/rapl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index f42a

[PATCH V4 23/25] perf/x86/msr: Add Alder Lake CPU support

From: Kan Liang PPERF and SMI_COUNT MSRs are also supported on Alder Lake. The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source. The patch has been tested on real hardware. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86

[PATCH V4 24/25] perf/x86/cstate: Add Alder Lake CPU support

From: Kan Liang Compared with the Rocket Lake, the CORE C1 Residency Counter is added for Alder Lake, but the CORE C3 Residency Counter is removed. Other counters are the same. Create a new adl_cstates for Alder Lake. Update the comments accordingly. The External Design Specification (EDS) is

[PATCH V4 22/25] perf/x86/intel/uncore: Add Alder Lake support

From: Kan Liang The uncore subsystem for Alder Lake is similar to the previous Tiger Lake. The difference includes: - New MSR addresses for global control, fixed counters, CBOX and ARB. Add a new adl_uncore_msr_ops for uncore operations. - Add a new threshold field for CBOX. - New PCIIDs for

[PATCH V4 21/25] perf: Introduce PERF_TYPE_HARDWARE_PMU and PERF_TYPE_HW_CACHE_PMU

From: Kan Liang Current Hardware events and Hardware cache events have special perf types, PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE. The two types don't pass the PMU type in the user interface. For a hybrid system, the perf subsystem doesn't know which PMU the events belong to.

[PATCH V4 20/25] perf/x86/intel: Add Alder Lake Hybrid support

From: Kan Liang Alder Lake Hybrid system has two different types of core, Golden Cove core and Gracemont core. The Golden Cove core is registered to "cpu_core" PMU. The Gracemont core is registered to "cpu_atom" PMU. The difference between the two PMUs include: - Number of G

[PATCH V4 19/25] perf/x86: Support filter_match callback

From: Kan Liang Implement filter_match callback for X86, which check whether an event is schedulable on the current CPU. Reviewed-by: Andi Kleen Signed-off-by: Kan Liang --- arch/x86/events/core.c | 10 ++ arch/x86/events/perf_event.h | 1 + 2 files changed, 11 insertions

[PATCH V4 03/25] perf/x86: Track pmu in per-CPU cpu_hw_events

From: Kan Liang Some platforms, e.g. Alder Lake, have hybrid architecture. In the same package, there may be more than one type of CPU. The PMU capabilities are different among different types of CPU. Perf will register a dedicated PMU for each type of CPU. Add a 'pmu' variable in

[PATCH V4 18/25] perf/x86/intel: Add attr_update for Hybrid PMUs

From: Kan Liang The attribute_group for Hybrid PMUs should be different from the previous cpu PMU. For example, cpumask is required for a Hybrid PMU. The PMU type should be included in the event and format attribute. Add hybrid_attr_update for the Hybrid PMU. Check the PMU type in is_visible

[PATCH V4 05/25] perf/x86: Hybrid PMU support for intel_ctrl

From: Kan Liang The intel_ctrl is the counter mask of a PMU. The PMU counter information may be different among hybrid PMUs, each hybrid PMU should use its own intel_ctrl to check and access the counters. When handling a certain hybrid PMU, apply the intel_ctrl from the corresponding hybrid PMU

[PATCH V4 17/25] perf/x86: Add structures for the attributes of Hybrid PMUs

From: Kan Liang Hybrid PMUs have different events and formats. In theory, Hybrid PMU specific attributes should be maintained in the dedicated struct x86_hybrid_pmu, but it wastes space because the events and formats are similar among Hybrid PMUs. To reduce duplication, all hybrid PMUs will

[PATCH V4 16/25] perf/x86: Register hybrid PMUs

From: Kan Liang Different hybrid PMUs have different PMU capabilities and events. Perf should registers a dedicated PMU for each of them. To check the X86 event, perf has to go through all possible hybrid pmus. All the hybrid PMUs are registered at boot time. Before the registration, add

[PATCH V4 15/25] perf/x86: Factor out x86_pmu_show_pmu_cap

From: Kan Liang The PMU capabilities are different among hybrid PMUs. Perf should dump the PMU capabilities information for each hybrid PMU. Factor out x86_pmu_show_pmu_cap() which shows the PMU capabilities information. The function will be reused later when registering a dedicated hybrid PMU

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