From: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> Add feature enumeration to identify a processor with Intel Hybrid Technology: one in which CPUs of more than one type are the same package. On a hybrid processor, all CPUs support the same homogeneous (i.e., symmetric) instruction set. All CPUs enumerate the same features in CPUID. Thus, software (user space and kernel) can run and migrate to any CPU in the system as well as utilize any of the enumerated features without any change or special provisions. The main difference among CPUs in a hybrid processor are power and performance properties.
Cc: Andi Kleen <a...@linux.intel.com> Cc: Kan Liang <kan.li...@linux.intel.com> Cc: "Peter Zijlstra (Intel)" <pet...@infradead.org> Cc: "Rafael J. Wysocki" <rafael.j.wyso...@intel.com> Cc: "Ravi V. Shankar" <ravi.v.shan...@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruv...@linux.intel.com> Cc: linux-kernel@vger.kernel.org Reviewed-by: Len Brown <len.br...@intel.com> Reviewed-by: Tony Luck <tony.l...@intel.com> Acked-by: Borislav Petkov <b...@suse.de> Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com> --- Changes since v4 (as part of patchset for perf change for Alderlake) * Add Acked-by Changes since v3 (as part of patchset for perf change for Alderlake) * None Changes since V2 (as part of patchset for perf change for Alderlake) * Don't show "hybrid_cpu" in /proc/cpuinfo (Boris) Changes since v1 (as part of patchset for perf change for Alderlake) * None Changes since v1 (in a separate posting): * Reworded commit message to clearly state what is Intel Hybrid Technology. Stress that all CPUs can run the same instruction set and support the same features. --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index cc96e26..1ba4a6e 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -374,6 +374,7 @@ #define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */ #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */ #define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */ +#define X86_FEATURE_HYBRID_CPU (18*32+15) /* "" This part has CPUs of more than one type */ #define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */ #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ #define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */ -- 2.7.4
