On 2021/2/9 20:01, Greg KH wrote:
> On Tue, Feb 09, 2021 at 07:58:15PM +0800, Zhou Wang wrote:
>> On 2021/2/9 17:37, Greg KH wrote:
>>> On Tue, Feb 09, 2021 at 05:17:46PM +0800, Zhou Wang wrote:
>>>> On 2021/2/8 6:02, Andy Lutomirski wrote:
>>>>>
>&g
On 2021/2/9 17:37, Greg KH wrote:
> On Tue, Feb 09, 2021 at 05:17:46PM +0800, Zhou Wang wrote:
>> On 2021/2/8 6:02, Andy Lutomirski wrote:
>>>
>>>
>>>> On Feb 7, 2021, at 12:31 AM, Zhou Wang wrote:
>>>>
>>>> SVA(share virtual
On 2021/2/8 5:51, Arnd Bergmann wrote:
> On Sun, Feb 7, 2021 at 9:18 AM Zhou Wang wrote:
>
>> diff --git a/arch/arm64/include/asm/unistd32.h
>> b/arch/arm64/include/asm/unistd32.h
>> index cccfbbe..3f49529 100644
>> --- a/arch/arm64/include/asm/unistd32.h
&
On 2021/2/8 6:02, Andy Lutomirski wrote:
>
>
>> On Feb 7, 2021, at 12:31 AM, Zhou Wang wrote:
>>
>> SVA(share virtual address) offers a way for device to share process virtual
>> address space safely, which makes more convenient for user space device
>> dr
On 2021/2/8 5:34, Matthew Wilcox wrote:
> On Sun, Feb 07, 2021 at 04:18:03PM +0800, Zhou Wang wrote:
>> SVA(share virtual address) offers a way for device to share process virtual
>> address space safely, which makes more convenient for user space device
>> driver coding. Ho
This test gets a fd from new mempinfd syscall and creates multiple threads
to do pin/unpin memory.
Signed-off-by: Zhou Wang
Suggested-by: Barry Song
---
tools/testing/selftests/vm/Makefile | 1 +
tools/testing/selftests/vm/mempinfd.c | 131 ++
2 files
/msg3805205.html
Zhou Wang (2):
mempinfd: Add new syscall to provide memory pin
selftests/vm: add mempinfd test
arch/arm64/include/asm/unistd.h | 2 +-
arch/arm64/include/asm/unistd32.h | 2 +
fs/Makefile | 1 +
fs/mempinfd.c
pin page cases in
other places, can_do_mlock is used to check permission and input
parameters.
Signed-off-by: Zhou Wang
Signed-off-by: Sihang Chen
Suggested-by: Barry Song
---
arch/arm64/include/asm/unistd.h | 2 +-
arch/arm64/include/asm/unistd32.h | 2 +
fs/Makefile
On 2021/1/25 23:47, Jason Gunthorpe wrote:
> On Mon, Jan 25, 2021 at 04:34:56PM +0800, Zhou Wang wrote:
>
>> +static int uacce_pin_page(struct uacce_pin_container *priv,
>> + struct uacce_pin_address *addr)
>> +{
>> +unsigned int f
On 2021/1/25 17:28, Greg Kroah-Hartman wrote:
> On Mon, Jan 25, 2021 at 04:34:56PM +0800, Zhou Wang wrote:
>> +static int uacce_pin_page(struct uacce_pin_container *priv,
>> + struct uacce_pin_address *addr)
>> +{
>> +unsigned int flag
r one file
will be unpinned in file release process.
Signed-off-by: Zhou Wang
Signed-off-by: Sihang Chen
Suggested-by: Barry Song
---
Changes v1 -> v2:
- Some tiny fixes
- Follow Greg's suggestion to get mm-list and iommu-list involved.
v1: https://lwn.net/Articles/843432/
---
drivers/
On 2021/1/21 17:44, Greg Kroah-Hartman wrote:
> On Thu, Jan 21, 2021 at 05:09:14PM +0800, Zhou Wang wrote:
>> When IO page fault happens, DMA performance will be affected. Pin user page
>> can avoid IO page fault, this patch introduces a new char device named
>> /dev/uacce_ctr
under one file will be unpinned in file release process.
Signed-off-by: Zhou Wang
Signed-off-by: Sihang Chen
Suggested-by: Barry Song
---
drivers/misc/uacce/uacce.c | 172 +++-
include/uapi/misc/uacce/uacce.h | 16
2 files changed, 187 insertions
On 2020/6/23 23:04, Bjorn Helgaas wrote:
> On Fri, Jun 19, 2020 at 10:26:54AM +0800, Zhangfei Gao wrote:
>> Have studied _DSM method, two issues we met comparing using quirk.
>>
>> 1. Need change definition of either pci_host_bridge or pci_dev, like adding
>> member can_stall,
>> while pci system d
te a 'work_queue' and set as 'WQ_UNBOUND' to do the back half work
> on some different CPUS.
>
> Signed-off-by: Yang Shen
> Reviewed-by: Zaibo Xu
Reviewed-by: Zhou Wang
Thanks,
Zhou
> ---
> drivers/crypto/hisilicon/zip/zip_main.c | 26
On 2020/11/2 16:33, Greg Kroah-Hartman wrote:
> On Mon, Nov 02, 2020 at 03:38:49PM +0800, Zhou Wang wrote:
>> On 2020/11/2 15:09, Greg Kroah-Hartman wrote:
>>> On Mon, Nov 02, 2020 at 02:41:12PM +0800, Zhou Wang wrote:
>>>> On 2020/9/23 18:09, Kai Ye wrote:
>&
On 2020/11/2 15:09, Greg Kroah-Hartman wrote:
> On Mon, Nov 02, 2020 at 02:41:12PM +0800, Zhou Wang wrote:
>> On 2020/9/23 18:09, Kai Ye wrote:
>>> 1. delete some redundant code.
>>> 2. modify the module author information. "Hisilicon"
>>> spelling i
On 2020/9/23 18:09, Kai Ye wrote:
> The spelling of "Hisilicon" is modified.
>
> Signed-off-by: Kai Ye
> Reviewed-by: Zhou Wang
> Reviewed-by: Jonathan Cameron
> Acked-by: Zhangfei Gao
> ---
> drivers/misc/uacce/uacce.c | 2 +-
> 1 file changed, 1 insert
On 2020/9/23 18:09, Kai Ye wrote:
> Delete some redundant code.
>
> Signed-off-by: Kai Ye
> Reviewed-by: Zhou Wang
> Reviewed-by: Jonathan Cameron
> Acked-by: Zhangfei Gao
> ---
> drivers/misc/uacce/uacce.c | 11 ---
> 1 file changed, 11 deletions(-)
>
On 2020/9/23 18:09, Kai Ye wrote:
> 1. delete some redundant code.
> 2. modify the module author information. "Hisilicon"
> spelling is error.
>
> Changes v2 -> v3:
> Two things, splited to two patches.
> Changes v1 -> v2:
> deleted extra NULL pointer check in uacce_fops.
>
> Kai Ye (
On 2020/8/3 9:29, Jia-Ju Bai wrote:
>
>
> On 2020/8/3 9:12, Zhou Wang wrote:
>> On 2020/8/2 22:52, Jia-Ju Bai wrote:
>>> In qm_qp_ctx_cfg(), "sqc" and "aeqc" are mapped to streaming DMA:
>>>eqc_dma = dma_map_single(..., eqc, ...);
>
On 2020/8/2 22:52, Jia-Ju Bai wrote:
> In qm_qp_ctx_cfg(), "sqc" and "aeqc" are mapped to streaming DMA:
> eqc_dma = dma_map_single(..., eqc, ...);
> ..
> aeqc_dma = dma_map_single(..., aeqc, ...);
Only sqc, cqc will be configured in qm_qp_ctx_cfg.
>
> Then "sqc" and "aeqc" are accesse
On 2020/7/30 14:13, Kai Ye wrote:
> 1. delete some redundant code.
> 2. modify the module author information.
>
> Signed-off-by: Kai Ye
Fine to me.
Reviewed-by: Zhou Wang
Thanks,
Zhou
> ---
> Changes in V2:
> deleted extra NULL pointer check in uacce_fops.
>
: Gustavo A. R. Silva
Looks good to me, thanks!
Reviewed-by: Zhou Wang
> ---
> drivers/dma/hisi_dma.c | 5 +
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/dma/hisi_dma.c b/drivers/dma/hisi_dma.c
> index ed3619266a48..e1a958ae7925 100644
> --
On 2020/6/4 14:50, Herbert Xu wrote:
> On Thu, Jun 04, 2020 at 02:44:16PM +0800, Zhangfei Gao wrote:
>>
>> I think it is fine.
>> 1. Currently the name size is 64, bigger enough.
>> Simply grep in driver name, 64 should be enough.
>> We can make it larger when there is a request.
>> 2. it does not
tes which would
> have been copied if there were enough space and scnprintf() returns the
> number of bytes which were actually copied. It doesn't matter here
> because the strings are very short so they can't go over 256 bytes.
>
> Signed-off-by: Dan Carpenter
Looks go
480 218765574
> drivers/crypto/hisilicon/zip/zip_main.o
>
> After:
>textdata bss dec hex filename
> 156205776 480 218765574
> drivers/crypto/hisilicon/zip/zip_main.o
>
> Signed-off-by: Rikard Falkeborn
Reviewed-by: Zhou Wang
On 2019/8/12 19:15, Colin King wrote:
> From: Colin Ian King
>
> There is a spelling mistake in the hzip_dfx_regs array, fix this.
>
> Signed-off-by: Colin Ian King
> ---
> drivers/crypto/hisilicon/zip/zip_main.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers
On 2019/8/8 21:40, Jens Axboe wrote:
> On 7/28/19 6:44 PM, Zhou Wang wrote:
>> On 2019/7/24 11:54, Zhou Wang wrote:
>>> In function sg_split, the second sg_calculate_split will return -EINVAL
>>> when in_mapped_nents is 0.
>>>
>>> Indeed there i
On 2019/7/29 9:44, Zhou Wang wrote:
> On 2019/7/24 11:54, Zhou Wang wrote:
>> In function sg_split, the second sg_calculate_split will return -EINVAL
>> when in_mapped_nents is 0.
>>
>> Indeed there is no need to do second sg_calculate_split and sg_split_mapped
>&
The HiSilicon ZIP accelerator implements the zlib and gzip algorithm. It
uses Hisilicon QM as the interface to the CPU.
This patch provides PCIe driver to the accelerator and registers it to
crypto acomp interface. It also uses sgl as data input/output interface.
Signed-off-by: Zhou Wang
Signed
On 2019/7/24 11:54, Zhou Wang wrote:
> In function sg_split, the second sg_calculate_split will return -EINVAL
> when in_mapped_nents is 0.
>
> Indeed there is no need to do second sg_calculate_split and sg_split_mapped
> when in_mapped_nents is 0, as in_mapped_nents indicates no
In function sg_split, the second sg_calculate_split will return -EINVAL
when in_mapped_nents is 0.
Indeed there is no need to do second sg_calculate_split and sg_split_mapped
when in_mapped_nents is 0, as in_mapped_nents indicates no mapped entry in
original sgl.
Signed-off-by: Zhou Wang
Acked
On 2019/4/19 18:43, Robert Jarzmik wrote:
> Zhou Wang writes:
>
>> In function sg_split, the second sg_calculate_split will return -EINVAL
>> when in_mapped_nents is 0.
>>
>> Indeed there is no need to do second sg_calculate_split and sg_split_mapped
&g
In function sg_split, the second sg_calculate_split will return -EINVAL
when in_mapped_nents is 0.
Indeed there is no need to do second sg_calculate_split and sg_split_mapped
when in_mapped_nents is 0, as in_mapped_nents indicates no mapped entry in
original sgl.
Signed-off-by: Zhou Wang
-gnu-
> drivers/pci/controller/dwc/pcie-hisi.c:365:21: warning: symbol
> 'hisi_pcie_platform_ops' was not declared. Should it be static?
>
> Fixes: a2ec1996098("PCI: hisi: Add DT almost-ECAM support for Hip06/Hip07
> host controllers")
> Reported-by: Hulk Ro
On 2019/2/20 12:10, Herbert Xu wrote:
> On Sat, Feb 02, 2019 at 10:25:43AM +0800, Zhou Wang wrote:
>>
>> In fact, I planned to register to acomp later.
>>
>> It also makes sense to use scomp if hardware engine is faster than CPU.
>> So how about registering to sco
On 2019/2/1 23:39, Herbert Xu wrote:
> On Fri, Feb 01, 2019 at 03:15:54PM +0800, Zhou Wang wrote:
>>
>>> Polling in softirq context is unacceptable. Can't your hardware
>>> send interrupts to signal completion? What is the average speed
>>> of processing a
On 2019/2/1 13:22, Herbert Xu wrote:
> On Wed, Jan 23, 2019 at 09:08:51PM +0800, Zhou Wang wrote:
>>
>> +/**
>> + * hisi_qp_poll() - Poll current cqe to see if a task is finished.
>> + * @qp: The qp which will poll.
>> + *
>> + * This function polls curren
On 2019/1/23 21:08, Zhou Wang wrote:
> This series adds HiSilicon QM and ZIP controller driver in crypto subsystem.
>
> A simple QM/ZIP driver which helps to provide an example for a general
> accelerator framework is under review in community[1]. Based on this simple
> driver, t
mailboxes and doorbells. Specific task request are descripted by
specific description buffer, which will be controlled and pass to related
accelerator IP by QM.
This patch adds a QM driver used by the accelerator driver to access
the QM hardware.
Signed-off-by: Zhou Wang
Signed-off-by: Kenneth Lee
Add Zhou Wang as a maintainer for HiSilicon QM and ZIP controller driver.
Signed-off-by: Zhou Wang
Reviewed-by: John Garry
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 51029a4..6e6be9b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
The HiSilicon ZIP accelerator implements the zlib and gzip algorithm. It
uses Hisilicon QM as the interface to the CPU.
This patch provides PCIe driver to the accelerator and register it to
the crypto subsystem.
Signed-off-by: Zhou Wang
Signed-off-by: Shiju Jose
Signed-off-by: Kenneth Lee
Add debugfs descriptions for HiSilicon ZIP and QM driver.
Signed-off-by: Zhou Wang
Reviewed-by: Jonathan Cameron
---
Documentation/ABI/testing/debugfs-hisi-zip | 50 ++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/ABI/testing/debugfs-hisi-zip
hange to register zlib/gzip to scomp.
- Remove hisi_qm_mem_init/uninit, make QM interfaces compact.
- Some tiny fixes.
Links:
- v1 https://lwn.net/Articles/775484/
- rfc https://lkml.org/lkml/2018/12/13/290
Reference:
[1] https://lkml.org/lkml/2018/11/12/1951
Zhou Wang (4):
Documentation: Add debugfs
On 2019/1/18 12:55, Herbert Xu wrote:
> On Wed, Jan 16, 2019 at 10:12:47PM +0800, Zhou Wang wrote:
>>
>> A stupid question: how do we test scomp alg?
>>
>> It seems we can not use general comp API, e.g. crypto_alloc_comp
>> to do this.
>>
>> Coul
On 2019/1/11 14:34, Zhou Wang wrote:
> On 2019/1/11 14:08, Herbert Xu wrote:
>> On Sat, Dec 22, 2018 at 03:51:44PM +0800, Zhou Wang wrote:
>>>
>>> +static struct crypto_alg hisi_zip_zlib = {
>>> + .cra_name
On 2019/1/11 14:08, Herbert Xu wrote:
> On Sat, Dec 22, 2018 at 03:51:44PM +0800, Zhou Wang wrote:
>>
>> +static struct crypto_alg hisi_zip_zlib = {
>> +.cra_name = "zlib-deflate",
>> +.cra_flags = CRYPTO_AL
On 2018/12/22 15:51, Zhou Wang wrote:
> This series adds HiSilicon QM and ZIP controller driver in crypto subsystem.
>
> A simple QM/ZIP driver which helps to provide an example for a general
> accelerator framework is under review in community[1]. Based on this simple
> driver, t
Add Zhou Wang as a maintainer for HiSilicon QM and ZIP controller driver.
Signed-off-by: Zhou Wang
Reviewed-by: John Garry
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0767f1d..5be84e2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
Add debugfs descriptions for HiSilicon ZIP and QM driver.
Signed-off-by: Zhou Wang
Reviewed-by: Jonathan Cameron
---
Documentation/ABI/testing/debugfs-hisi-zip | 50 ++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/ABI/testing/debugfs-hisi-zip
mailboxes and doorbells. Specific task request are descripted by specific
description buffer, which will be controlled and pass to related accelerator
IP by QM.
This patch adds a QM driver used by the accelerator driver to access
the QM hardware.
Signed-off-by: Zhou Wang
Signed-off-by: Kenneth Lee
l.org/lkml/2018/11/12/1951
Zhou Wang (4):
Documentation: Add debugfs doc for hisi_zip
crypto: hisilicon: Add queue management driver for HiSilicon QM module
crypto: hisilicon: Add HiSilicon ZIP accelerator support
MAINTAINERS: add maintainer for HiSilicon QM and ZIP controller driver
Document
The HiSilicon ZIP accelerator implements the zlib and gzip algorithm. It
uses Hisilicon QM as the interface to the CPU.
This patch provides PCIe driver to the accelerator and register it to
the crypto subsystem.
Signed-off-by: Zhou Wang
Signed-off-by: Shiju Jose
Signed-off-by: Kenneth Lee
The HiSilicon ZIP accelerator implements the zlib and gzip algorithm. It
uses Hisilicon QM as the interface to the CPU.
This patch provides PCIe driver to the accelerator and register it to
the crypto subsystem.
Signed-off-by: Zhou Wang
Signed-off-by: Shiju Jose
Signed-off-by: Kenneth Lee
mailboxes and doorbells. Specific task request are descripted by specific
description buffer, which will be controlled and pass to related accelerator
IP by QM.
This patch adds a QM driver used by the accelerator driver to access
the QM hardware.
Signed-off-by: Zhou Wang
Signed-off-by: Kenneth Lee
Add Zhou Wang as a maintainer for HiSilicon QM and ZIP controller driver.
Signed-off-by: Zhou Wang
reviewed-by: John Garry
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0767f1d..5be84e2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
l.org/lkml/2018/11/12/1951
Zhou Wang (4):
Documentation: Add debugfs doc for hisi_zip
crypto: hisilicon: Add queue management driver for HiSilicon QM module
crypto: hisilicon: Add HiSilicon ZIP accelerator support
MAINTAINERS: add maintainer for HiSilicon QM and ZIP controller driver
Document
Add debugfs descriptions for HiSilicon ZIP and QM driver.
Signed-off-by: Zhou Wang
reviewed-by: Jonathan Cameron
---
Documentation/ABI/testing/debugfs-hisi-zip | 50 ++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/ABI/testing/debugfs-hisi-zip
On 2017/5/15 17:17, Lorenzo Pieralisi wrote:
> On Mon, May 15, 2017 at 02:13:47PM +0800, Zhou Wang wrote:
>> On 2017/4/26 18:06, Lorenzo Pieralisi wrote:
>>> The introduction of pci_bus_find_numa_node(pci_bus) allows at PCI
>>> host bridge registration to detec
On 2017/4/26 18:06, Lorenzo Pieralisi wrote:
> The introduction of pci_bus_find_numa_node(pci_bus) allows at PCI
> host bridge registration to detect the NUMA node for a given
> struct pci_bus.dev. Implement an ACPI method that, through
> the struct pci_bus.bridge ACPI companion, retrieve and retur
On 2017/3/22 16:00, Arnd Bergmann wrote:
> On Mar 22, 2017 04:27, "Zhou Wang" <mailto:wangzh...@hisilicon.com>> wrote:
>
> On 2017/3/21 23:48, Jingoo Han wrote:
> > (+cc: Joao Pinto, Zhou Wang, Gabriele Paoloni)
> >
> > On Tuesday
On 2017/3/21 23:48, Jingoo Han wrote:
> (+cc: Joao Pinto, Zhou Wang, Gabriele Paoloni)
>
> On Tuesday, March 21, 2017 10:32 AM, Arnd Bergmann wrote:
>>
>> Without PCI_HOST_COMMON support enabled, we get a link error:
>>
>> drivers/pci/dwc/built-in.o: In func
On 2017/1/12 5:37, Bjorn Helgaas wrote:
> On Wed, Jan 04, 2017 at 03:00:06PM +0800, Zhou Wang wrote:
>> The configuration data provided by an MCFG region (ie PCI segment and
>> bus range) may span multiple host bridges.
>>
>> Current code in pci_mcfg_lookup() carries
On 2017/1/10 5:45, Rafael J. Wysocki wrote:
> On Mon, Jan 9, 2017 at 4:39 AM, Zhou Wang wrote:
>> On 2017/1/4 15:00, Zhou Wang wrote:
>>> The configuration data provided by an MCFG region (ie PCI segment and
>>> bus range) may span multiple host bridges.
>>>
On 2017/1/4 15:00, Zhou Wang wrote:
> The configuration data provided by an MCFG region (ie PCI segment and
> bus range) may span multiple host bridges.
>
> Current code in pci_mcfg_lookup() carries out an exact match of host
> bridge bus range start value against the MCFG regi
.
Signed-off-by: Zhou Wang
Reviewed-by: Tomasz Nowicki
Acked-by: Lorenzo Pieralisi
---
drivers/acpi/pci_mcfg.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index a6a4cea..2944353 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b
On 2017/1/3 20:00, Lorenzo Pieralisi wrote:
> On Thu, Dec 22, 2016 at 05:07:43PM +0800, Zhou Wang wrote:
>> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for
>> each
>> host bridge should be in the coverage of bus range of related PCIe segment.
On 2017/1/3 14:39, Tomasz Nowicki wrote:
> On 22.12.2016 10:07, Zhou Wang wrote:
>> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for
>> each
>> host bridge should be in the coverage of bus range of related PCIe segment.
>>
>> Thi
On 2016/12/22 17:07, Zhou Wang wrote:
> Multiple PCIe host bridges may exists in one PCIe segment. So bus range for
> each
> host bridge should be in the coverage of bus range of related PCIe segment.
>
> This patch will support this kind of scenario:
>
> MCFG:
>
:
bus range: 0x00~0x1f.
segment: 0.
host bridge 2:
bus range: 0x20~0x4f.
segment: 0.
Signed-off-by: Zhou Wang
---
drivers/acpi/pci_mcfg.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/acpi/pci_mcfg.c
> Signed-off-by: Arnd Bergmann
>
Hi Arnd,
Many thanks, it looks good to me. so
Acked-by: Zhou Wang
Regards,
Zhou
> diff --git a/drivers/pci/host/pcie-hisi.c b/drivers/pci/host/pcie-hisi.c
> index 35457ecd8e70..163671a4f798 100644
> --- a/drivers/pci/host/pcie-hisi.c
> +++ b/
.html
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Signed-off-by: Arnd Bergmann
Tested-by: James Morse
Tested-by: Gabriel Fernandez
Tested-by: Minghuan Lian
Acked-by: Pratyush Anand
---
drivers/pci/host/pci-dra7xx.c | 8
drivers/pci/host/pc
nware: Remove *_mod_base".
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Signed-off-by: Arnd Bergmann
Tested-by: James Morse
Tested-by: Gabriel Fernandez
Tested-by: Minghuan Lian
Acked-by: Pratyush Anand
---
drivers/pci/host/pcie-designwa
This patch adds PCIe host support for HiSilicon SoC Hip05, related DT binding
document and maintainer update.
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Signed-off-by: liudongdong
Acked-by: Rob Herring
---
.../bindings/arm/hisilicon/hisilicon.txt | 17
This patch uses the new of_pci_get_host_bridge_resources
API in place of the PCI OF DT parser
For reference see previous suggestions from Gabriele[1]
[1] http://www.spinics.net/lists/linux-pci/msg42194.html
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Tested-by: James Morse
/lists/linux-pci/msg42539.html
Link of v2:
- http://www.spinics.net/lists/linux-pci/msg41844.html
Link of RFC v1:
- http://www.spinics.net/lists/linux-pci/msg41305.html
Link of RFC:
- http://www.spinics.net/lists/linux-pci/msg40434.html
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/
s only
applicable to DRA7xx.
This patch moves the calculation of the bus addresses to the DRA7xx
driver and is needed to allow the rework of designware to use
the new DT parsing API.
Signed-off-by: Gabriele Paoloni
Signed-off-by: Zhou Wang
Acked-by: Pratyush Anand
---
drivers/pci/host/pc
hods), but the pci_sys_data->align_resource pointer was
used only by Marvell (see mvebu_pcie_enable()), so this would only be a
problem if we had a system with a combination of Marvell and other host
bridges
[bhelgaas: changelog]
Signed-off-by: Gabriele Paoloni
Signed-off-by: Zhou Wang
Si
On 2015/10/28 6:32, Bjorn Helgaas wrote:
> Hi Zhou,
>
> On Mon, Oct 26, 2015 at 07:35:42PM +0800, Zhou Wang wrote:
>> This patchset adds PCIe host support for HiSilicon SoC Hip05. The PCIe hosts
>> use PCIe IP core from Synopsys, So this driver is based on designware PCIe
&
On 2015/10/28 3:19, Rob Herring wrote:
> On Mon, Oct 26, 2015 at 6:35 AM, Zhou Wang wrote:
>> This patch adds related DTS binding document for HiSilicon PCIe host driver.
>>
>> Signed-off-by: Zhou Wang
>
> Acked-by: Rob Herring
>
Thanks for your review.
Zho
This patch reverts commit f4c55c5a3f7f ("PCI: designware: Program ATU with
untranslated address") based on 1/8 in this series. we delete *_mod_base in
pcie-designware. This was discussed in [1]
[1] http://www.spinics.net/lists/arm-kernel/msg436779.html
Signed-off-by: Zhou Wang
Sig
ch solves the issue by removing "align_resource" from "pci_sys_data"
struct and defining a static global function pointer in "bios32.c"
Signed-off-by: Gabriele Paoloni
Signed-off-by: Zhou Wang
Acked-by: Pratyush Anand
---
arch/arm/include/asm/mach/pci.h | 6 --
arch
This patch uses the new of_pci_get_host_bridge_resources
API in place of the PCI OF DT parser
For reference see previous suggestions from Gabriele[1]
[1] http://www.spinics.net/lists/linux-pci/msg42194.html
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Tested-by: James Morse
This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw_pci,
move related operations to dw_pcie_host_init.
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Signed-off-by: Arnd Bergmann
Tested-by
This patch adds PCIe host support for HiSilicon SoC Hip05.
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Signed-off-by: liudongdong
---
drivers/pci/host/Kconfig | 8 ++
drivers/pci/host/Makefile| 1 +
drivers/pci/host/pcie-hisi.c | 198
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/359741.html
Zhou Wang (6):
PCI: designware: Replace DT PCI ranges parse with
of_pci_get_host_bridge_resources
PCI: designware: Add ARM64 support
PCI: designware: Remove *_mod_base
PCI: hisi: Add PCIe host support for HiSilicon
s only
applicable to DRA7xx.
This patch moves the calculation of the bus addresses to the DRA7xx
driver and is needed to allow the rework of designware to use
the new DT parsing API.
Signed-off-by: Gabriele Paoloni
Signed-off-by: Zhou Wang
Acked-by: Pratyush Anand
---
drivers/pci/host/pc
Signed-off-by: Zhou Wang
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7ba7ab7..944a229 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8047,6 +8047,13 @@ S: Maintained
F: Documentation/devicetree/bindings/pci/xgene-pci
This patch adds related DTS binding document for HiSilicon PCIe host driver.
Signed-off-by: Zhou Wang
---
.../bindings/arm/hisilicon/hisilicon.txt | 17 +
.../devicetree/bindings/pci/hisilicon-pcie.txt | 44 ++
2 files changed, 61 insertions(+)
create
On 2015/10/23 2:46, Bjorn Helgaas wrote:
> Hi Zhou,
>
> This looks pretty good to me; just a mask question and add a printk.
>
> On Fri, Oct 16, 2015 at 06:23:39PM +0800, Zhou Wang wrote:
>> This patch adds PCIe host support for HiSilicon SoC Hip05.
On 2015/10/23 2:28, Bjorn Helgaas wrote:
> Hi Zhou,
>
> On Fri, Oct 16, 2015 at 06:23:38PM +0800, Zhou Wang wrote:
>> This patch tries to unify ARM32 and ARM64 PCIe in designware driver. Delete
>> function dw_pcie_setup, dw_pcie_scan_bus, dw_pcie_map_irq and struct hw
On 2015/10/23 0:35, Bjorn Helgaas wrote:
> Hi Gabriele,
>
> On Thu, Oct 22, 2015 at 07:21:41AM +, Gabriele Paoloni wrote:
>>> -Original Message-
>>> From: Bjorn Helgaas [mailto:helg...@kernel.org]
>
#define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
#define
Signed-off-by: Zhou Wang
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7ba7ab7..944a229 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8047,6 +8047,13 @@ S: Maintained
F: Documentation/devicetree/bindings/pci/xgene-pci
This patch adds PCIe host support for HiSilicon SoC Hip05.
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Signed-off-by: liudongdong
---
drivers/pci/host/Kconfig | 8 ++
drivers/pci/host/Makefile| 1 +
drivers/pci/host/pcie-hisi.c | 196
s only
applicable to DRA7xx.
This patch moves the calculation of the bus addresses to the DRA7xx
driver and is needed to allow the rework of designware to use
the new DT parsing API.
Signed-off-by: Gabriele Paoloni
Signed-off-by: Zhou Wang
Acked-by: Pratyush Anand
---
drivers/pci/host/pc
don't have
ARM32 PCIe related board to do test. It will be appreciated if someone could
help to test it.
Signed-off-by: Zhou Wang
Signed-off-by: Gabriele Paoloni
Signed-off-by: Arnd Bergmann
Tested-by: James Morse
Tested-by: Gabriel Fernandez
Tested-by: Minghuan Lian
Acked-by: Pratyush A
This patch adds related DTS binding document for HiSilicon PCIe host driver.
Signed-off-by: Zhou Wang
---
.../bindings/arm/hisilicon/hisilicon.txt | 17 +
.../devicetree/bindings/pci/hisilicon-pcie.txt | 44 ++
2 files changed, 61 insertions(+)
create
ch solves the issue by removing "align_resource" from "pci_sys_data"
struct and defining a static global function pointer in "bios32.c"
Signed-off-by: Gabriele Paoloni
Signed-off-by: Zhou Wang
Acked-by: Pratyush Anand
---
arch/arm/include/asm/mach/pci.h | 6 --
arch
41305.html
Link of RFC:
- http://www.spinics.net/lists/linux-pci/msg40434.html
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-July/359741.html
Zhou Wang (4):
PCI: designware: Add ARM64 support
PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05
Documentation: DT: Add HiSilicon P
1 - 100 of 149 matches
Mail list logo
