On Tue, Mar 2, 2021 at 12:39 PM Zhi Li wrote:
>
> On Tue, Mar 2, 2021 at 10:25 AM Adrian Hunter wrote:
> >
> > On 2/03/21 5:12 pm, Zhi Li wrote:
> > >
> > >
> > > On Tue, Mar 2, 2021 at 1:03 AM Adrian Hunter > > <mailto:adrian.hun...@intel.
On Tue, Mar 2, 2021 at 10:25 AM Adrian Hunter wrote:
>
> On 2/03/21 5:12 pm, Zhi Li wrote:
> >
> >
> > On Tue, Mar 2, 2021 at 1:03 AM Adrian Hunter > <mailto:adrian.hun...@intel.com>> wrote:
> >
> > On 1/03/21 7:21 pm, Frank Li wrote:
> &g
E_DATA(LOONGSON, GMAC, &loongson_pci_info) },
+{}
+};
+MODULE_DEVICE_TABLE(pci, loongson_gmac_table);
+
+struct pci_driver loongson_gmac_driver = {
+.name = "loongson gmac",
+.id_table = loongson_gmac_table,
+.probe = loongson_gmac_probe,
+.remove = loongson_gmac_remove,
+.driver = {
+.pm = &loongson_eth_pm_ops,
+},
+};
+
+module_pci_driver(loongson_gmac_driver);
+
+MODULE_DESCRIPTION("Loongson DWMAC PCI driver");
+MODULE_AUTHOR("Zhi Li ");
+MODULE_LICENSE("GPL v2");
Thanks
- Jiaxun
Add gmac platform data to support LS7A bridge chip.
Co-developed-by: Hongbin Li
Signed-off-by: Hongbin Li
Signed-off-by: Zhi Li
---
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac
lank line after declarations
+ int value = loongson3_cpu_temp(id);
+ return sprintf(buf, "%d\n", value);
ERROR: spaces required around that '=' (ctx:VxV)
+ for (i=0; i
Signed-off-by: Zhi Li
---
drivers/platform/mips/cpu_hwmon.c | 33 ++
From: Tiezhu Yang
Once the temperature of any CPUs is too high, it can power off immediately,
no need to check the rest of CPUs, and it is better to print a log before
power off, this is useful when analysis the abnormal issues.
Signed-off-by: Tiezhu Yang
Signed-off-by: Zhi Li
---
drivers
-by: Zhi Li
---
drivers/platform/mips/cpu_hwmon.c | 22 ++
1 file changed, 2 insertions(+), 20 deletions(-)
diff --git a/drivers/platform/mips/cpu_hwmon.c
b/drivers/platform/mips/cpu_hwmon.c
index c9f35e5..386389f 100644
--- a/drivers/platform/mips/cpu_hwmon.c
+++ b/drivers
nd add log in
do_thermal_timer()
Zhi Li (1):
MIPS: Loongson: Fix boot warning about hwmon_device_register()
drivers/platform/mips/cpu_hwmon.c | 66 +++
1 file changed, 25 insertions(+), 41 deletions(-)
--
2.1.0
The parameter "cmdline_p" is useless in bootcmdline_init()，remove it.
Signed-off-by: Zhi Li
---
v2:
- Remove "the" before "bootcmdline_init()" in the patch subject.
arch/mips/kernel/setup.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --gi
The parameter "cmdline_p" is useless in bootcmdline_init(), remove it.
Signed-off-by: Zhi Li
---
arch/mips/kernel/setup.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 8db533c..7b537fa 100644
--- a
On Fri, Feb 24, 2017 at 9:47 AM, Zhi Li wrote:
> On Wed, Feb 15, 2017 at 8:28 AM, Zhi Li wrote:
>> On Wed, Feb 15, 2017 at 6:00 AM, wrote:
>>> From: Tiberiu Breana
>>>
>>> Fixed an error in the "write-accesses" event definition.
>>>
>
On Wed, Feb 15, 2017 at 8:28 AM, Zhi Li wrote:
> On Wed, Feb 15, 2017 at 6:00 AM, wrote:
>> From: Tiberiu Breana
>>
>> Fixed an error in the "write-accesses" event definition.
>>
>> Signed-off-by: Tiberiu Breana
>
> Acked-by: Frank Li
Shawn
On Wed, Feb 15, 2017 at 6:00 AM, wrote:
> From: Tiberiu Breana
>
> Fixed an error in the "write-accesses" event definition.
>
> Signed-off-by: Tiberiu Breana
Acked-by: Frank Li
> ---
> arch/arm/mach-imx/mmdc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm
On Wed, Feb 15, 2017 at 6:00 AM, wrote:
> From: Tiberiu Breana
>
> Add support for an extra config parameter for perf commands:
> axi_id, which will be written in the MMDC's MADPCR1 register,
> to filter memory usage profiling (see i.MX6 reference manual,
> chapter 44.7 MMDC Profiling for AXI id
Subject should add prefix like:
ARM: imx: fix
best regards
Frank Li
On Tue, Feb 14, 2017 at 3:01 AM, Tiberiu Breana
wrote:
> Fixed an error in the "write-accesses" event definition.
>
> Signed-off-by: Tiberiu Breana
> ---
> arch/arm/mach-imx/mmdc.c | 2 +-
> 1 file changed, 1 insertion(+
On Tue, Nov 8, 2016 at 2:11 PM, Peter Zijlstra wrote:
> On Tue, Nov 08, 2016 at 01:21:47PM -0600, Zhi Li wrote:
>> On Tue, Nov 8, 2016 at 1:00 PM, Paul Gortmaker
>> > I just noticed this commit now that linux-next is back after the week off.
>> >
>> > Th
On Tue, Nov 8, 2016 at 1:00 PM, Paul Gortmaker
wrote:
> On Mon, Sep 19, 2016 at 1:47 PM, Frank Li wrote:
>> From: Zhengyu Shen
>>
>> MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64
>> and LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high
>> performance,
On Wed, Nov 2, 2016 at 9:40 AM, Shawn Guo wrote:
> On Tue, Oct 25, 2016 at 04:26:56PM -0500, Frank Li wrote:
>> i.MX6QP added new reigster bit PROFILE_SEL in MADPCR0.
>> need set it at perf start.
>>
>> Signed-off-by: Frank Li
>> ---
>> arch/arm/mach-imx/mmdc.c | 45 +
On Wed, Nov 2, 2016 at 9:42 AM, Shawn Guo wrote:
> On Tue, Oct 25, 2016 at 04:26:57PM -0500, Frank Li wrote:
>> mmdc of i.MX6QP are little difference with i.MX6Q.
>> added new compatible stream fsl,imx6qp-mmdc
>>
>> Signed-off-by: Frank Li
>> ---
>> arch/arm/boot/dts/imx6qp.dtsi | 7 +++
>>
On Mon, Sep 26, 2016 at 11:40 AM, Zhi Li wrote:
> On Mon, Sep 19, 2016 at 12:57 PM, Frank Li wrote:
>> From: Zhengyu Shen
>>
>> MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64
>> and LPDDR2 two channel x16/x32 memory types. MMDC is configurabl
On Mon, Sep 19, 2016 at 12:57 PM, Frank Li wrote:
> From: Zhengyu Shen
>
> MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64
> and LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high
> performance, and optimized. MMDC is present on i.MX6 Quad and i.MX6
> Qua
On Wed, Aug 17, 2016 at 2:42 PM, Zhengyu Shen wrote:
> MMDC is a multi-mode DDR controller that supports DDR3/DDR3L x16/x32/x64
> and LPDDR2 two channel x16/x32 memory types. MMDC is configurable, high
> performance, and optimized. MMDC is present on i.MX6 Quad and i.MX6
> QuadPlus devices, but th
On Fri, Aug 5, 2016 at 9:35 AM, Zhengyu Shen wrote:
> $ perf stat -e
> mmdc/busy-cycles/,mmdc/read-accesses/,mmdc/read-bytes/,mmdc/total-cycles/,mmdc/write-accesses/,mmdc/write-bytes/
> dd if=/dev/zero of=/dev/null bs=1M count=5000
> Performance counter stats for 'dd if=/dev/zero of=/dev/null bs
On Fri, Sep 18, 2015 at 8:12 PM, Shawn Guo wrote:
> On Fri, Sep 18, 2015 at 02:38:39PM +, Shenwei Wang wrote:
>>
>>
>> > -Original Message-
>> > From: Shawn Guo [mailto:shawn...@kernel.org]
>> > Sent: 2015年9月18日 9:15
>> > To: Wang Shenwei-B38339
>> > Cc: ja...@lakedaemon.net; Huang Yon
On Tue, Jul 28, 2015 at 9:30 AM, Shawn Guo wrote:
> On Tue, Jul 28, 2015 at 02:16:20PM +, Shenwei Wang wrote:
>> > The files are named with "-imx7". It's a clear sign that the build of the
>> > files
>> > should be controlled by something like related to "imx7".
>> > Ideally, it should be CO
On Mon, Jun 1, 2015 at 10:12 AM, Stefan Agner wrote:
> In some SoC's using the IMX pin controller, the IP looses its state
> when entering lowest power modes. Enhance the driver with suspend/
> resume functions restoring the pin states.
> ---
> Hi all,
>
> Currently I'm working on implementing sus
On Wed, Jan 28, 2015 at 10:40 AM, Stefan Wahren wrote:
> The clk init for the i.MX28 in the kernel tries to the set
> IO0FRAC and IO1FRAC at once. So this patch fix this problem.
Okay, I am fine. I suggest add comment about only change one FRAC once.
--
To unsubscribe from this list: send the li
On Wed, Jan 28, 2015 at 9:52 AM, Stefan Wahren wrote:
> Hi,
>
> Am 28.01.2015 um 04:36 schrieb Zhi Li:
>> On Tue, Jan 27, 2015 at 7:51 PM, Mike Turquette
>> wrote:
>>> Quoting Marek Vasut (2015-01-21 15:39:01)
>>>> On Wednesday, January 21, 2015 at 05
On Tue, Jan 27, 2015 at 7:51 PM, Mike Turquette wrote:
> Quoting Marek Vasut (2015-01-21 15:39:01)
>> On Wednesday, January 21, 2015 at 05:16:03 PM, Zhi Li wrote:
>> > On Sun, Dec 28, 2014 at 4:26 AM, Stefan Wahren
>> > wrote:
>> > > According to
On Sun, Dec 28, 2014 at 4:26 AM, Stefan Wahren wrote:
> According to i.MX23 and i.MX28 reference manual the fractional
> clock control registers must be addressed by byte instructions.
>
I don't think mx23 and mx28 have such limitation. I will double check
with IC team about this.
RTL is generate
On Thu, Aug 21, 2014 at 4:21 AM, Zhu Yanjun wrote:
> From Reference Manual, freescale IMX6 is little endian mode. Therefore
> the first structure field is length, the second is status.
>
> CC: David Miller
> CC: Frank Li
> Signed-off-by: Zhu Yanjun
> ---
> drivers/net/ethernet/freescale/fec.h
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