On 4/13/2021 9:19 AM, Viresh Kumar wrote:
On 12-04-21, 15:01, Taniya Das wrote:
Technically the HW we are trying to program here differs in terms of
clocking, the LUT definitions and many more. It will definitely make
debugging much more troublesome if we try to accommodate multiple versions
Hi Bjorn,
On 1/21/2021 12:35 AM, Bjorn Andersson wrote:
On Wed 20 Jan 12:25 CST 2021, Taniya Das wrote:
The CPUFREQ-HW driver is intended to be used only for CPUFREQ HW designs
where the firmware programs the look up tables.
It's obvious that this is the intended target for the cu
Add support for the video, gpu, display, lpass clock controller
device nodes for SC7280 SoC.
Signed-off-by: Taniya Das
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 58
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch
Add device node for cpufreq HW and clock controllers of GPU, DISP, VIDEO, LPASS.
The clock controller nodes are dependent on the following
VIDEO/DISP/GPU: https://lkml.org/lkml/2021/3/16/1624
LPASS: https://lkml.org/lkml/2021/4/9/812
Taniya Das (2):
arm64: dts: qcom: sc7280: Add cpufreq hw
Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+
cores on SC7280 SoCs.
Signed-off-by: Taniya Das
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280
Add support for the lpass clock controller found on SC7280 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 8 ++
drivers/clk/qcom/Makefile | 1
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic
properties that are needed in a device tree. Add the LPASS clock IDs for
LPASS PIL client to request for the clocks.
Signed-off-by: Taniya Das
---
.../bindings/clock/qcom,sc7280-lpasscc.yaml| 69
Thanks Stephen for the review.
On 3/23/2021 12:59 PM, Stephen Boyd wrote:
Quoting Taniya Das (2021-03-19 00:47:34)
Update the RCGs to use shared ops to park the RCGs at XO.
s/Update/fix/?
Can you also elaborate more on why we need to park the RCGs here for all
these different clks? Is the
.
Thus park the RCGs at XO during clock disable and update the rcg_ops to
use the shared_ops.
Fixes: 15d09e830bbc ("clk: qcom: camcc: Add camera clock controller driver for
SC7180")
Signed-off-by: Taniya Das
---
drivers/clk/qcom/camcc-sc7180.c | 50 ---
Hello Stephen,
Thanks for your review.
On 3/14/2021 4:29 AM, Stephen Boyd wrote:
Quoting Taniya Das (2021-03-11 04:51:32)
The root clock generators with MND divider has the capability to support
change in duty-cycle by updating the 'D'. Add the clock ops which would
check all th
Update the RCGs to use shared ops to park the RCGs at XO.
Fixes: 15d09e830bbc ("clk: qcom: camcc: Add camera clock controller driver for
SC7180")
Signed-off-by: Taniya Das
---
drivers/clk/qcom/camcc-sc7180.c | 50 -
1 file changed, 25 inserti
Add support for the graphics clock controller found on SC7280
based devices. This would allow graphics drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig| 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gpucc-sc7280.c | 491
Add support for the video clock controller found on SC7280
based devices. This would allow video drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/videocc-sc7280.c | 372
Add device tree bindings for video clock subsystem clock
controller for Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,videocc.yaml| 4 +++-
include/dt-bindings/clock/qcom,videocc-sc7280.h| 27 ++
2
Add support for the display clock controller found on SC7280
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/dispcc-sc7280.c
Add device tree bindings for display clock controller subsystem for
Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das
---
.../bindings/clock/qcom,sc7280-dispcc.yaml | 94 ++
include/dt-bindings/clock/qcom,dispcc-sc7280.h | 55 +
2
Add device tree bindings for graphics clock subsystem clock
controller for Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gpucc.yaml | 4 ++-
include/dt-bindings/clock/qcom,gpucc-sc7280.h | 35 ++
2
Add support for display, video & graphics clock controllers on SC7280
along with the bindings for each of the clock controllers.
Taniya Das (6):
dt-bindings: clock: Add SC7280 DISPCC clock binding
clk: qcom: Add display clock controller driver for SC7280
dt-bindings: clock: Add SC7280 G
The root clock generators with MND divider has the capability to support
change in duty-cycle by updating the 'D'. Add the clock ops which would
check all the boundary conditions and enable setting the desired duty-cycle
as per the consumer.
Signed-off-by: Taniya Das
---
drivers/cl
The root clock generators with MND divider has the capability to support
change in duty-cycle by updating the 'D'. Add the clock ops which would
check all the boundary conditions and enable setting the desired duty-cycle
as per the consumer.
Signed-off-by: Taniya Das
---
drivers/cl
The bi_tcxo clock source for SC7280 requires a div 4 to derive 19.2MHz
from the xo_board. Thus update the same.
Fixes: fff2b9a65162 ("clk: qcom: rpmh: Add support for RPMH clocks on SC7280")
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rpmh.c | 7 +--
1 file changed, 5
Hello Stephen,
Thanks for the review.
On 2/23/2021 1:13 PM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2021-02-11 23:28:43)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 7848e88..10851e7 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/
Reviewed-by: Taniya Das
On 2/24/2021 11:20 PM, Douglas Anderson wrote:
While picking commit a8cd989e1a57 ("mmc: sdhci-msm: Warn about
overclocking SD/MMC") back to my tree I was surprised that it was
reporting warnings. I thought I fixed those! Looking closer at the
fix, I see that
Add support for the global clock controller found on SC7280
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc
Add device tree bindings for global clock subsystem clock
controller for Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc-sc7280.yaml | 92 +
include/dt-bindings/clock/qcom,gcc-sc7280.h| 226 +++
QSPI/WPSS/MSS/LPASS/PCIE clocks.
* Update the floor rcg ops for SDCC/QSPI clock.
* Add comment for cpuss critical clocks.
[v1]
* Documentation binding for GCC clock for SC7280.
* GCC clock driver for SC7280.
Taniya Das (2):
dt-bindings: clock: Add SC7280 GCC clock binding
clk: qcom: Add Gl
Thanks Stephen for your review comments.
On 1/13/2021 1:34 AM, Stephen Boyd wrote:
+
+static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
+ .cmd_rcgr = 0x7500c,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = gcc_parent_map_8,
+ .freq_tbl = ftbl_gcc_sdcc1_apps_cl
Thanks Stephen for your review comments.
On 1/13/2021 1:36 AM, Stephen Boyd wrote:
+ clock-names:
+items:
+ - const: bi_tcxo
+ - const: bi_tcxo_ao
+ - const: sleep_clk
+ - const: pcie_0_pipe_clk
+ - const: pcie_1_pipe_clk
+ - const: usb3_phy_wrapper_gcc_usb30_
Thanks Rob for your review comments.
diff --git a/include/dt-bindings/clock/qcom,gcc-sc7280.h
b/include/dt-bindings/clock/qcom,gcc-sc7280.h
new file mode 100644
index 000..3295bd4
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sc7280.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier:
Add support for RPMH clocks on SC7280 SoCs.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-rpmh.c | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 6a2a13c..c180959 100644
--- a
Add the bindings for sc7280 and support the rpmh clock which
are required to be supported on SC7280.
Taniya Das (2):
dt-bindings: clock: Add RPMHCC bindings for SC7280
clk: qcom: rpmh: Add support for RPMH clocks on SC7280
.../devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
drivers
Add bindings and update documentation for clock rpmh driver on SC7280.
Signed-off-by: Taniya Das
---
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
b/Documentation/devicetree
Hi Bjorn,
On 1/21/2021 4:10 AM, Bjorn Andersson wrote:
On Wed 20 Jan 01:47 CST 2021, Taniya Das wrote:
There are intermittent GDSC power-up failures observed for titan top
gdsc, which requires the XO clock. Thus mark all the MM XO clocks always
enabled from probe.
But if this is the reason
The CPUFREQ-HW driver is intended to be used only for CPUFREQ HW designs
where the firmware programs the look up tables.
Suggestion is to separate out the driver where the programming is
managed by high level OS.
On 1/19/2021 11:15 PM, AngeloGioacchino Del Regno wrote:
On new SoCs (SDM845 on
There are intermittent GDSC power-up failures observed for titan top
gdsc, which requires the XO clock. Thus mark all the MM XO clocks always
enabled from probe.
Fixes: 8d4025943e13 ("clk: qcom: camcc-sc7180: Use runtime PM ops instead of
clk ones")
Signed-off-by: Taniya Das
---
d
clk ones")
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sc7180.c | 21 +++--
1 file changed, 3 insertions(+), 18 deletions(-)
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index d82d725..b05901b 100644
--- a/drivers/clk/qcom/gcc-sc7180.c
+++
Add driver support for Global Clock controller for SC7280 and also update
device tree bindings for the various clocks supported in the clock controller.
Taniya Das (2):
dt-bindings: clock: Add SC7280 GCC clock binding
clk: qcom: Add Global Clock controller (GCC) driver for SC7280
Add support for the global clock controller found on SC7280
based devices. This should allow most non-multimedia device
drivers to probe and control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/gcc
Add device tree bindings for global clock subsystem clock
controller for Qualcomm Technology Inc's SC7280 SoCs.
Signed-off-by: Taniya Das
---
.../devicetree/bindings/clock/qcom,gcc-sc7280.yaml | 85
include/dt-bindings/clock/qcom,gcc-sc7280.h| 215 +++
On 12/11/2020 12:40 PM, Stephen Boyd wrote:
Quoting Vinod Koul (2020-12-10 21:43:49)
On 10-12-20, 12:43, Stephen Boyd wrote:
+static struct clk_branch gcc_camera_ahb_clk = {
+ .halt_reg = 0x26004,
+ .halt_check = BRANCH_HALT_DELAY,
+ .hwcg_reg = 0x26004,
+ .hwcg_bit =
Hi Vinod,
On 12/4/2020 10:05 AM, Vinod Koul wrote:
Hi Bjorn,
On 03-12-20, 18:06, Bjorn Andersson wrote:
On Thu 03 Dec 01:02 CST 2020, Vinod Koul wrote:
diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
[..]
+static int gcc_sm8350_probe(struct platform_device *pdev)
The LPASSCC driver's suspend/resume is invoked multiple number of times
and thus allow the device to autosuspend for 500ms.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/lpasscorecc-sc7180.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/clk
Add the camera clock controller node supported on SC7180.
Signed-off-by: Taniya Das
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index f5ef2cb..e795dba
Reviewed-by: Taniya Das
On 10/20/2020 4:19 AM, Douglas Anderson wrote:
Let's convert the lpass clock control driver to use devm. This is a
few more lines of code, but it will be useful in a later patch which
disentangles the two devices handled by this driver.
Signed-off-by: Douglas And
Reviewed-by: Taniya Das
On 10/20/2020 4:19 AM, Douglas Anderson wrote:
The sc7180 lpass clock driver manages two different devices. These
two devices were tangled together, using one probe and a lookup to
figure out the real probe. I think it's cleaner to really separate
the probe for
Reviewed-by: Taniya Das
On 10/17/2020 7:31 AM, Stephen Boyd wrote:
If the GDSC is enabled out of boot but doesn't have the retain ff bit
set we will get confusing results where the registers that are powered
by the GDSC lose their contents on the first power off of the GDSC but
thereafter
The Camera Subsystem clock provider have a bunch of generic properties
that are needed in a device tree. Add a YAML schemas for those.
Add clock ids for camera clocks which are required to bring the camera
subsystem out of reset.
Signed-off-by: Taniya Das
---
.../bindings/clock/qcom,sc7180
Add programming sequence support for managing the Agera PLLs.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-alpha-pll.c | 62
drivers/clk/qcom/clk-alpha-pll.h | 4 +++
2 files changed, 66 insertions(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c
Add support for the camera clock controller found on SC7180 based devices.
This would allow camera drivers to probe and control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig|9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/camcc-sc7180.c | 1736
ous clocks supported in the
clock controller.
Taniya Das (4):
clk: qcom: clk-alpha-pll: Add support for helper functions
clk: qcom: clk-alpha-pll: Add support for controlling Agera PLLs
dt-bindings: clock: Add YAML schemas for the QCOM Camera clock
bindings.
clk: qcom: camcc: Add ca
Introduce clk_alpha_pll_write_config and alpha_pll_check_rate_margin
helper functions to be across PLL configure functions and PLL set rate
functions.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-alpha-pll.c | 155 +--
1 file changed, 66 insertions
Thanks for your review Stephen.
On 10/14/2020 7:29 AM, Stephen Boyd wrote:
Quoting Taniya Das (2020-10-13 10:11:50)
diff --git a/drivers/clk/qcom/camcc-sc7180.c b/drivers/clk/qcom/camcc-sc7180.c
new file mode 100644
index 000..e954d21
--- /dev/null
+++ b/drivers/clk/qcom/camcc-sc7180.c
Thanks for your review Stephen.
On 10/14/2020 7:39 AM, Stephen Boyd wrote:
Quoting Taniya Das (2020-10-13 10:11:49)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml
b/Documentation/devicetree/bindings/clock/qcom,sc7180-camcc.yaml
new file mode 100644
index 000
Thanks Stephen for the review comments.
On 10/14/2020 7:37 AM, Stephen Boyd wrote:
Quoting Taniya Das (2020-10-13 10:11:48)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 26139ef..17e1fc0 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk
Thanks Doug for the patch.
On 10/14/2020 9:28 PM, Douglas Anderson wrote:
From: Taniya Das
In the case where the PLL configuration is lost, then the pm runtime
resume will reconfigure before usage.
Fixes: edab812d802d ("clk: qcom: lpass: Add support for LPASS clock controller for
S
In the case where the PLL configuration is lost, then the pm runtime
resume will reconfigure before usage.
Fixes: edab812d802d ("clk: qcom: lpass: Add support for LPASS clock controller
for SC7180")
Signed-off-by: Taniya Das
---
drivers/clk/qcom/lpasscorecc-sc7
In the case where the LPASSCC PLL loses the PLL configuration it would fail
to lock. Thus allow reconfigure the PLL from pm_resume.
Taniya Das (1):
clk: qcom: lpasscc: Re-configure the PLL in case lost
drivers/clk/qcom/lpasscorecc-sc7180.c | 22 ++
1 file changed, 22
Add support for the camera clock controller found on SC7180 based devices.
This would allow camera drivers to probe and control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig|9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/camcc-sc7180.c | 1737
Add programming sequence support for managing the Agera PLLs.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-alpha-pll.c | 80
drivers/clk/qcom/clk-alpha-pll.h | 4 ++
2 files changed, 84 insertions(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c
The Camera Subsystem clock provider have a bunch of generic properties
that are needed in a device tree. Add a YAML schemas for those.
Add clock ids for camera clocks which are required to bring the camera
subsystem out of reset.
Signed-off-by: Taniya Das
---
.../bindings/clock/qcom,sc7180
in the
clock controller.
Taniya Das (3):
clk: qcom: clk-alpha-pll: Add support for controlling Agera PLLs
dt-bindings: clock: Add YAML schemas for the QCOM Camera clock
bindings.
clk: qcom: camcc: Add camera clock controller driver for SC7180
.../bindings/clock/qcom,sc7180
Thanks for the review Stephen.
On 9/15/2020 5:43 AM, Stephen Boyd wrote:
Quoting Taniya Das (2020-09-08 10:07:26)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 26139ef..fb27fcf 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk
[v1]
* Add support for Agera PLL which is used in the camera clock controller.
* Add driver support for camera clock controller for SC7180 and also
update device tree bindings for the various clocks supported in the
clock controller.
Taniya Das (3):
clk: qcom: clk-alpha-pll: Add
Add support for the camera clock controller found on SC7180 based devices.
This would allow camera drivers to probe and control their clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig|9 +
drivers/clk/qcom/Makefile |1 +
drivers/clk/qcom/camcc-sc7180.c | 1737
The Camera Subsystem clock provider have a bunch of generic properties
that are needed in a device tree. Add a YAML schemas for those.
Add clock ids for Camera clocks which are required to bring the camera
subsystem out of reset.
Signed-off-by: Taniya Das
---
.../bindings/clock/qcom,sc7180
Add programming sequence support for managing the Agera PLLs.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/clk-alpha-pll.c | 82
drivers/clk/qcom/clk-alpha-pll.h | 4 ++
2 files changed, 86 insertions(+)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c
Hi Stephen,
On 8/6/2020 1:54 AM, Stephen Boyd wrote:
Quoting Taniya Das (2020-07-24 09:07:58)
+
+static struct clk_rcg2 core_clk_src = {
+ .cmd_rcgr = 0x1d000,
+ .mnd_width = 8,
+ .hid_width = 5,
+ .parent_map = lpass_core_cc_parent_map_2,
+ .clkr.hw.init
Update the clock controller nodes for Low power audio subsystem
functionality.
Signed-off-by: Taniya Das
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom
[v2]
- Update the node in sorted order.
- Depends on the patch
https://lore.kernel.org/r/20200731133006.1.Iee81b115f5be50d6d69500fe1bda11bba6e16143@changeid
[v1]
- Clock controller LPASS device Node.
Taniya Das (1):
arm64: dts: qcom: sc7180: Add LPASS clock controller nodes
arch/arm64
The Low Power Audio subsystem clocks are required for Audio client
to be able to request for the clocks and power domains.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/lpasscorecc-sc7180.c | 477
Add the GCC lpass clock which is required to access the LPASS core
clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sc7180.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index ca4383e..8d3b161 100644
.
[v2]
* Update retention macro name.
* Update the register description in the documentation.
[v1]
* Add support for Retention of GDSCR.
* Add YAML schema for LPASS clocks and clock IDs for LPASS.
* Add clock driver for LPASS core clocks and GCC LPASS clock.
Taniya Das (4):
clk: qcom: gdsc: Add
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic
properties that are needed in a device tree. Also add clock ids for GCC
LPASS and LPASS Core clock IDs for LPASS client to request for the clocks.
Signed-off-by: Taniya Das
---
.../bindings/clock/qcom,sc7180
Add support for the RETAIN_FF_ENABLE feature which enables the
usage of retention registers. These registers maintain their
state after disabling and re-enabling a GDSC.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gdsc.c | 12
drivers/clk/qcom/gdsc.h | 1 +
2 files changed, 13
Hi Stephen,
Thanks for the review.
On 7/21/2020 1:18 PM, Stephen Boyd wrote:
Quoting Taniya Das (2020-07-14 23:36:50)
diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c
b/drivers/clk/qcom/lpasscorecc-sc7180.c
+static struct clk_alpha_pll lpass_lpaaudio_dig_pll = {
+ .offset = 0x1000
Hi Stephen,
Thanks for the review.
On 7/21/2020 1:21 PM, Stephen Boyd wrote:
+...
diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h
b/include/dt-bindings/clock/qcom,gcc-sc7180.h
index 992b67b..bdf43adc 100644
--- a/include/dt-bindings/clock/qcom,gcc-sc7180.h
+++ b/include/dt-bindings/c
Update the clock controller nodes for Low power audio subsystem
functionality.
Signed-off-by: Taniya Das
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180
The display gpll0 branch clock needs to be always left enabled, thus
move the clock ops to _aon branch ops.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sc7180.c | 2 +-
drivers/clk/qcom/gcc-sdm845.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom
The Low Power Audio subsystem clocks are required for Audio client
to be able to request for the clocks and power domains.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/lpasscorecc-sc7180.c | 478
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic
properties that are needed in a device tree. Also add clock ids for GCC
LPASS and LPASS Core clock IDs for LPASS client to request for the clocks.
Signed-off-by: Taniya Das
---
.../bindings/clock/qcom,sc7180
Add the GCC lpass clock which is required to access the LPASS core
clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sc7180.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index ca4383e..8d3b161 100644
]
* Add support for Retention of GDSCR.
* Add YAML schema for LPASS clocks and clock IDs for LPASS.
* Add clock driver for LPASS core clocks and GCC LPASS clock.
Taniya Das (4):
clk: qcom: gdsc: Add support to enable retention of GSDCR
dt-bindings: clock: Add YAML schemas for LPASS clocks on
Hi Rob,
Thanks for the review.
On 6/18/2020 3:59 AM, Rob Herring wrote:
On Wed, Jun 10, 2020 at 10:48:05PM +0530, Taniya Das wrote:
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic
properties that are needed in a device tree. Also add clock ids for GCC
LPASS and
Add support for the RETAIN_FF_ENABLE feature which enables the
usage of retention registers. These registers maintain their
state after disabling and re-enabling a GDSC.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gdsc.c | 12
drivers/clk/qcom/gdsc.h | 1 +
2 files changed, 13
for LPASS clocks and clock IDs for LPASS.
* Add clock driver for LPASS core clocks and GCC LPASS clock.
Taniya Das (4):
clk: qcom: gdsc: Add support to enable retention of GSDCR
dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
clk: qcom: gcc: Add support for GCC LPASS clock for
Add support for the RETAIN_FF_ENABLE feature which enables the
usage of retention registers. These registers maintain their
state after disabling and re-enabling a GDSC.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gdsc.c | 12
drivers/clk/qcom/gdsc.h | 1 +
2 files changed, 13
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic
properties that are needed in a device tree. Also add clock ids for GCC
LPASS and LPASS Core clock IDs for LPASS client to request for the clocks.
Signed-off-by: Taniya Das
---
.../bindings/clock/qcom,sc7180
The Low Power Audio subsystem clocks are required for Audio client
to be able to request for the clocks and power domains.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/lpasscorecc-sc7180.c | 478
Add the GCC lpass clock which is required to access the LPASS core
clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sc7180.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index ca4383e..8d3b161 100644
Thanks for your review.
On 5/27/2020 8:40 AM, Stephen Boyd wrote:
Quoting Taniya Das (2020-05-17 02:22:24)
diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c
b/drivers/clk/qcom/lpasscorecc-sc7180.c
new file mode 100644
index 000..86e3599
--- /dev/null
+++ b/drivers/clk/qcom/lpasscorecc
Thanks for your review.
On 5/29/2020 1:55 AM, Rob Herring wrote:
On Sun, May 17, 2020 at 02:52:22PM +0530, Taniya Das wrote:
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic
properties that are needed in a device tree. Also add clock ids for GCC
LPASS and LPASS Core
Thanks for the review.
On 5/27/2020 8:41 AM, Stephen Boyd wrote:
+ clocks:
+items:
+ - description: gcc_lpass_sway clock from GCC
+
+ clock-names:
+items:
+ - const: gcc_lpass_sway
As said on patch #4, maybe "iface" instead?
Will take care in the next patch.
+
+ powe
There is a requirement to support 51.2MHz from GPLL6 for qup clocks,
thus update the frequency table and parent data/map to use the GPLL6
source PLL.
Fixes: 17269568f7267 ("clk: qcom: Add Global Clock controller (GCC) driver for
SC7180")
Signed-off-by: Taniya Das
---
drivers/cl
The gcc_sec_ctrl_clk_src clock is required to be controlled by the
secure controller driver.
Signed-off-by: Taniya Das
---
include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/qcom,gcc-sc7180.h
b/include/dt-bindings/clock
The secure controller driver requires to request for various frequencies
on the source clock, thus add support for the same.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sc7180.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sc7180.c b
[v2]
* Update to use ARRAY_SIZE instead of hard-coded values for num_parents.
Also add the fixes tag.
[v1]
* Add a new frequency of 51.2MHz for QUP clock.
* Add support for gcc_sec_ctrl_clk_src RCG for client to be able to request
various frequencies.
Taniya Das (3):
clk: qcom
Hello Stephen,
Thanks for your review.
On 3/16/2020 11:19 PM, Stephen Boyd wrote:
Quoting Taniya Das (2020-03-16 03:54:42)
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index ad75847..3302f19 100644
--- a/drivers/clk/qcom/gcc-sc7180.c
+++ b/drivers/clk/qcom/gcc
Hello Stephen,
Thanks for your review.
On 3/16/2020 11:19 PM, Stephen Boyd wrote:
Quoting Taniya Das (2020-03-16 03:54:40)
There is a requirement to support 51.2MHz from GPLL6 for qup clocks,
thus update the frequency table and parent data/map to use the GPLL6
source PLL.
Signed-off-by
Add support for the RETAIN_FF_ENABLE feature which enables the
usage of retention registers. These registers maintain their
state after disabling and re-enabling a GDSC.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gdsc.c | 12
drivers/clk/qcom/gdsc.h | 1 +
2 files changed, 13
Add the GCC lpass clock which is required to access the LPASS core
clocks.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/gcc-sc7180.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index 6a51b5b..d970647 100644
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