On 4/25/2025 5:42 PM, Luca Weiss wrote:
> Compared to the msm-4.19 driver the mainline GDSC driver always sets the
> bits for en_rest, en_few & clk_dis, and if those values are not set
> per-GDSC in the respective driver then the default value from the GDSC
> driver is used. The downstream driver only conditionally sets
> clk_dis_wait_val if qcom,clk-dis-wait-val is given in devicetree.
>
> Correct this situation by explicitly setting those values. For all GDSCs
> the reset value of those bits are used.
>
> Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for
> SM6350")
> Signed-off-by: Luca Weiss <luca.we...@fairphone.com>
> ---
> drivers/clk/qcom/dispcc-sm6350.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/clk/qcom/dispcc-sm6350.c
> b/drivers/clk/qcom/dispcc-sm6350.c
> index
> e703ecf00e440473156f707498f23cde53fb7e22..b0bd163a449ccd2b27751e32eb17a982facf07d8
> 100644
> --- a/drivers/clk/qcom/dispcc-sm6350.c
> +++ b/drivers/clk/qcom/dispcc-sm6350.c
> @@ -681,6 +681,9 @@ static struct clk_branch disp_cc_xo_clk = {
>
> static struct gdsc mdss_gdsc = {
> .gdscr = 0x1004,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0xf,
> .pd = {
> .name = "mdss_gdsc",
> },
>
Reviewed-by: Taniya Das <quic_t...@quicinc.com>
