Document the binding for enabling mtk svs on MediaTek SoC.
Signed-off-by: Roger Lu
Reviewed-by: Rob Herring
---
.../bindings/soc/mediatek/mtk-svs.yaml| 84 +++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mtk
The Smart Voltage Scaling(SVS) engine is a piece of hardware
which calculates suitable SVS bank voltages to OPP voltage table.
Then, DVFS driver could apply those SVS bank voltages to PMIC/Buck
when receiving OPP_EVENT_ADJUST_VOLTAGE.
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/Kconfig
The purpose of SVS is to help find the suitable voltages
for DVFS. Therefore, if SVS bank voltages are concerned
to be wrong, we can adjust SVS bank voltages by this patch.
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/mtk-svs.c | 328 +
1 file changed, 328
add compitable/reg/irq/clock/efuse setting in svs node
Signed-off-by: Roger Lu
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/mtk-svs.c | 477 -
1 file changed, 471 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c
index 39f29d9e4fc7..e179ad7c2b35 100644
--- a/drivers/soc/mediatek
add compitable/reg/irq/clock/efuse/reset setting in svs node
Signed-off-by: Roger Lu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
://patchwork.kernel.org/project/linux-mediatek/patch/20200817030324.5690-5-crystal@mediatek.com/
changes since v14:
- fix coverities
- call regulator_set_mode() after regulator_enable()
- save SVS registers into svsb->reg_data[SVSB_PHASE_ERROR] when
svs_error_isr_handler() happens
Roger Lu
Signed-off-by: Roger Lu
Reviewed-by: Rob Herring
---
.../devicetree/bindings/soc/mediatek/mtk-svs.yaml | 8
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
I ran some tests on a 4 intel socket box with files in tmpfs (gold
6152 I think) and with the files interleaved 4way (I think) got the
same speeds you got on your intels (roughly) with defaults.
I also tested on my 6 core/4500u ryzen and got almost the same
speed(slightly slower) as on your large
85: warning: Function parameter or member
> 'dev' not described in 'blkfront_resume'
> drivers/block/xen-blkfront.c:2085: warning: expecting prototype for or a
> backend(). Prototype was for blkfront_resume() instead
> drivers/block/xen-blkfront.c:2444: warning: wrong ker
On Fri, Apr 2, 2021 at 4:13 AM Paul Menzel wrote:
>
> Dear Linux folks,
>
>
> > Are these values a good benchmark for comparing processors?
>
> After two years, yes they are. I created 16 10 GB files in `/dev/shm`,
> set them up as loop devices, and created a RAID6. For resync speed it
> makes di
list to features')
Suggested-by: Andy Shevchenko
Signed-off-by: Roger Pau Monné
---
Changes since v2:
- Return ENODEV.
- Adjust code comment.
Changes since v1:
- New in this version.
---
Cc: Mika Westerberg
Cc: Andy Shevchenko
Cc: Linus Walleij
Cc: linux-g...@vger.kernel.org
---
drive
On Wed, Mar 24, 2021 at 06:57:12PM +0200, Andy Shevchenko wrote:
> On Wed, Mar 24, 2021 at 04:13:59PM +0100, Roger Pau Monné wrote:
> > On Wed, Mar 24, 2021 at 04:22:44PM +0200, Andy Shevchenko wrote:
> > > On Wed, Mar 24, 2021 at 02:55:15PM +0100, Roger Pau Monné wrote:
>
On Wed, Mar 24, 2021 at 07:01:18PM +0200, Andy Shevchenko wrote:
> On Wed, Mar 24, 2021 at 04:43:11PM +0100, Roger Pau Monne wrote:
>
> Thanks for a fix! My comments below.
>
> > Use the value read from the REVID register in order to check for the
> > presence of the de
The purpose of SVS is to help find the suitable voltages
for DVFS. Therefore, if SVS bank voltages are concerned
to be wrong, we can adjust SVS bank voltages by this patch.
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/mtk-svs.c | 328 +
1 file changed, 328
Document the binding for enabling mtk svs on MediaTek SoC.
Signed-off-by: Roger Lu
---
.../bindings/soc/mediatek/mtk-svs.yaml| 84 +++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
diff --git a
The Smart Voltage Scaling(SVS) engine is a piece of hardware
which calculates suitable SVS bank voltages to OPP voltage table.
Then, DVFS driver could apply those SVS bank voltages to PMIC/Buck
when receiving OPP_EVENT_ADJUST_VOLTAGE.
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/Kconfig
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/mtk-svs.c | 477 -
1 file changed, 471 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c
index e36b3abfee03..3e152a86d280 100644
--- a/drivers/soc/mediatek
add compitable/reg/irq/clock/efuse setting in svs node
Signed-off-by: Roger Lu
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index
Signed-off-by: Roger Lu
---
.../devicetree/bindings/soc/mediatek/mtk-svs.yaml | 8
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
index a855ced410f8
add compitable/reg/irq/clock/efuse/reset setting in svs node
Signed-off-by: Roger Lu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
bank fills FREQPCT74 / FREQPCT30 with 0 and SVS
controller won't run normally. Therefore, we initialize SVS HIGH bank's
FREQPCT30 with svsb->freqs_pct[0] to avoid this issue.
- Change SVS GPU opp count back from 14 to 16 because GPU DVFS has a better
solution
Roger Lu (7):
[v14,1/7]
en.
Fixes: 91d898e51e60 ('pinctrl: intel: Convert capability list to features')
Signed-off-by: Roger Pau Monné
---
Changes since v1:
- Adjust commit message.
---
Cc: Mika Westerberg
Cc: Andy Shevchenko
Cc: Linus Walleij
Cc: linux-g...@vger.kernel.org
---
drivers/pinctrl/intel/pinctrl-intel.c |
hence contains the
pinctrl devices, but the MMIO region(s) containing the device
registers might not be mapped in the guest physical memory map if such
region(s) are not exposed on a PCI device BAR or marked as reserved in
the host memory map.
Suggested-by: Andy Shevchenko
Signed-off-by: Roger Pau
Hello,
The following series adds some consistency checks to the values returned
by some of the MMIO registers of the Intel pinctrl device.
That done to avoid a crash when running as a PVH dom0. See patch #1 for
more details.
Thanks, Roger.
Roger Pau Monne (2):
intel/pinctrl: check REVID
On Wed, Mar 24, 2021 at 04:22:44PM +0200, Andy Shevchenko wrote:
> On Wed, Mar 24, 2021 at 02:55:15PM +0100, Roger Pau Monné wrote:
> > On Wed, Mar 24, 2021 at 02:58:07PM +0200, Andy Shevchenko wrote:
> > > On Wed, Mar 24, 2021 at 01:31:18PM +0100, Roger Pau Monne wrote:
> &
On Wed, Mar 24, 2021 at 02:58:07PM +0200, Andy Shevchenko wrote:
> On Wed, Mar 24, 2021 at 01:31:18PM +0100, Roger Pau Monne wrote:
> > When parsing the capability list make sure the offset is between the
> > MMIO region mapped in 'regs', or else the kernel hits a page f
nel if the MMIO region is not properly reported.
Fixes: 91d898e51e60 ('pinctrl: intel: Convert capability list to features')
Signed-off-by: Roger Pau Monné
---
Cc: Mika Westerberg
Cc: Andy Shevchenko
Cc: Linus Walleij
Cc: linux-g...@vger.kernel.org
---
Resend because I've missed
o the size limitation of the p2m.
Rename the option to XEN_MEMORY_HOTPLUG_LIMIT since it's no longer
tied to ballooning.
Fixes: 9e2369c06c8a18 ("xen: add helpers to allocate unpopulated memory")
Signed-off-by: Roger Pau Monné
---
Cc: Boris Ostrovsky
Cc: Juergen Gross
Cc: Stefano Stabel
hould already trigger a properly sized p2m on Xen PV.
Note that XEN_UNPOPULATED_ALLOC depends on ZONE_DEVICE which pulls in
MEMORY_HOTPLUG.
Leave the check added to __set_phys_to_machine and the adjusted
comment about EXTRA_MEM_RATIO.
Signed-off-by: Roger Pau Monné
---
Cc: Boris Ostrovsky
Cc: Ju
when XEN_BALLOON_MEMORY_HOTPLUG is disabled
with XEN_UNPOPULATED_ALLOC.
Thanks, Roger.
Roger Pau Monne (2):
xen/x86: make XEN_BALLOON_MEMORY_HOTPLUG_LIMIT depend on
MEMORY_HOTPLUG
Revert "xen: fix p2m size in dom0 for disabled memory hotplug case"
arch/x86/include/asm/xen/page.h | 12 ---
nel if the MMIO region is not properly reported.
Fixes: 91d898e51e60 ('pinctrl: intel: Convert capability list to features')
Signed-off-by: Roger Pau Monné
---
drivers/pinctrl/intel/pinctrl-intel.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/driv
The purpose of SVS is to help find the suitable voltages
for DVFS. Therefore, if SVS bank voltages are concerned
to be wrong, we can adjust SVS bank voltages by this patch.
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/mtk-svs.c | 328 +
1 file changed, 328
Document the binding for enabling mtk svs on MediaTek SoC.
Signed-off-by: Roger Lu
---
.../bindings/soc/mediatek/mtk-svs.yaml| 81 +++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
diff --git a
Signed-off-by: Roger Lu
---
.../devicetree/bindings/soc/mediatek/mtk-svs.yaml | 8
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
index 0d8d12f927de
add compitable/reg/irq/clock/efuse setting in svs node
Signed-off-by: Roger Lu
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index
The Smart Voltage Scaling(SVS) engine is a piece of hardware
which calculates suitable SVS bank voltages to OPP voltage table.
Then, DVFS driver could apply those SVS bank voltages to PMIC/Buck
when receiving OPP_EVENT_ADJUST_VOLTAGE.
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/Kconfig
add compitable/reg/irq/clock/efuse/reset setting in svs node
Signed-off-by: Roger Lu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/mtk-svs.c | 476 -
1 file changed, 470 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c
index e36b3abfee03..54e7f908b76e 100644
--- a/drivers/soc/mediatek
8192_banks
- Assign svsp->bank_num by ARRAY_SIZE(svs_mt81xx_banks)
- Replace `,` with `;` in svs_get_svs_mt8192_platform_data()
Roger Lu (7):
[v13,1/7]: dt-bindings: soc: mediatek: add mtk svs dt-bindings
[v13,2/7]: arm64: dts: mt8183: add svs device information
[v13,3/7]: soc: mediatek: S
hould already trigger a properly sized p2m on Xen PV.
Leave the check added to __set_phys_to_machine.
Signed-off-by: Roger Pau Monné
---
Cc: Boris Ostrovsky
Cc: Juergen Gross
Cc: Stefano Stabellini
Cc: Jan Beulich
Cc: xen-de...@lists.xenproject.org
---
arch/x86/include/asm/xen/page.h
o the size limitation of the p2m.
Rename the option to XEN_MEMORY_HOTPLUG_LIMIT since it's no longer
tied to ballooning.
Fixes: 9e2369c06c8a18 ("xen: add helpers to allocate unpopulated memory")
Signed-off-by: Roger Pau Monné
---
Cc: Boris Ostrovsky
Cc: Juergen Gross
Cc: Stefano Stabel
when XEN_BALLOON_MEMORY_HOTPLUG is disabled
with XEN_UNPOPULATED_ALLOC.
Thanks, Roger.
Roger Pau Monne (2):
xen/x86: make XEN_BALLOON_MEMORY_HOTPLUG_LIMIT depend on
MEMORY_HOTPLUG
Revert "xen: fix p2m size in dom0 for disabled memory hotplug case"
arch/x86/include/asm/xen/page.h | 12 ---
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/mtk-svs.c | 477 -
1 file changed, 471 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c
index 5c315467747d..17e61acce868 100644
--- a/drivers/soc/mediatek
The Smart Voltage Scaling(SVS) engine is a piece of hardware
which calculates suitable SVS bank voltages to OPP voltage table.
Then, DVFS driver could apply those SVS bank voltages to PMIC/Buck
when receiving OPP_EVENT_ADJUST_VOLTAGE.
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/Kconfig
Signed-off-by: Roger Lu
---
.../devicetree/bindings/soc/mediatek/mtk-svs.yaml | 8
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
index 0d8d12f927de
add compitable/reg/irq/clock/efuse/reset setting in svs node
Signed-off-by: Roger Lu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
://patchwork.kernel.org/project/linux-mediatek/patch/20200817030324.5690-5-crystal@mediatek.com/
changes since v11:
- update mtk svs dt-bindings only.
Roger Lu (7):
[v12,1/7]: dt-bindings: soc: mediatek: add mtk svs dt-bindings
[v12,2/7]: arm64: dts: mt8183: add svs device information
add compitable/reg/irq/clock/efuse setting in svs node
Signed-off-by: Roger Lu
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index
Document the binding for enabling mtk svs on MediaTek SoC.
Signed-off-by: Roger Lu
---
.../bindings/soc/mediatek/mtk-svs.yaml| 81 +++
1 file changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
diff --git a
The purpose of SVS is to help find the suitable voltages
for DVFS. Therefore, if SVS bank voltages are concerned
to be wrong, we can adjust SVS bank voltages by this patch.
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/mtk-svs.c | 325 +
1 file changed, 325
://patchwork.kernel.org/project/linux-mediatek/patch/20200817030324.5690-5-crystal@mediatek.com/
changes since v11:
- update mtk svs dt-bindings only.
Roger Lu (7):
[v12,1/7]: dt-bindings: soc: mediatek: add mtk svs dt-bindings
[v12,2/7]: arm64: dts: mt8183: add svs device information
[v12,3
Liu
> Reviewed-by: Paul Durrant
> ---
> drivers/block/xen-blkback/xenbus.c | 2 +-
Reviewed-by: Roger Pau Monné
Thanks, Roger.
d by one that does not
> because, instead of reading 'ring-ref', xen-blkback will read the stale
> 'ring-ref0' left around by the previous frontend will try to map the wrong
> grant reference.
>
> This patch restores the original behaviour.
>
> Fixes: 4a8
On Wed, Jan 20, 2021 at 03:37:57PM +0100, Jan Beulich wrote:
> On 20.01.2021 15:35, Roger Pau Monné wrote:
> > On Wed, Jan 20, 2021 at 03:23:30PM +0100, Arthur Borsboom wrote:
> >> Hi Roger,
> >>
> >> I have set up a test environment based on Linux 5.11.0-rc4
On Wed, Jan 20, 2021 at 03:23:30PM +0100, Arthur Borsboom wrote:
> Hi Roger,
>
> I have set up a test environment based on Linux 5.11.0-rc4.
> The patch did not apply clean, so I copied/pasted the patch manually.
>
> Without the patch the call trace (as reported) is visible in
Forgot to Cc stable for the Fixes tag. Doing it now.
On Tue, Jan 19, 2021 at 11:57:27AM +0100, Roger Pau Monne wrote:
> This is inline with the specification described in blkif.h:
>
> * discard-granularity: should be set to the physical block size if
>node is not present.
: ed30bf317c5ce ('xen-blkfront: Handle discard requests.')
Reported-by: Arthur Borsboom
Signed-off-by: Roger Pau Monné
---
Cc: Boris Ostrovsky
Cc: Juergen Gross
Cc: Stefano Stabellini
Cc: Konrad Rzeszutek Wilk
Cc: "Roger Pau Monné"
Cc: Jens Axboe
Cc: xen-de...@lists.xenproj
On Tue, Jan 19, 2021 at 11:11:26AM +0100, Jürgen Groß wrote:
> On 19.01.21 11:06, Roger Pau Monné wrote:
> > On Tue, Jan 19, 2021 at 08:43:01AM +0100, Jürgen Groß wrote:
> > > On 18.01.21 16:15, Roger Pau Monne wrote:
> > > > Don't require the discard-align
On Tue, Jan 19, 2021 at 08:43:01AM +0100, Jürgen Groß wrote:
> On 18.01.21 16:15, Roger Pau Monne wrote:
> > Don't require the discard-alignment xenstore node to be present in
> > order to correctly setup the feature. This can happen with versions of
> > QEMU t
logic to not enable the discard feature if discard-granularity is not
present.
Reported-by: Arthur Borsboom
Signed-off-by: Roger Pau Monné
---
Cc: Boris Ostrovsky
Cc: Juergen Gross
Cc: Stefano Stabellini
Cc: Konrad Rzeszutek Wilk
Cc: "Roger Pau Monné"
Cc: Jens Ax
implementation, and causes issues
when mapping resources that don't have fixed or known sizes.
Signed-off-by: Roger Pau Monné
Cc: sta...@vger.kernel.org # >= 4.18
---
NB: fetching the size of a resource shouldn't trigger an hypercall
preemption, and hence I've dropped the p
On Tue, Jan 12, 2021 at 06:57:30AM +0100, Jürgen Groß wrote:
> On 11.01.21 16:29, Roger Pau Monne wrote:
> > Allow issuing an IOCTL_PRIVCMD_MMAP_RESOURCE ioctl with num = 0 and
> > addr = 0 in order to fetch the size of a specific resource.
> >
> > Add a shortcut to th
7;xen/privcmd: add IOCTL_PRIVCMD_MMAP_RESOURCE')
Signed-off-by: Roger Pau Monné
---
NB: fetching the size of a resource shouldn't trigger an hypercall
preemption, and hence I've dropped the preempt indications.
---
Cc: Boris Ostrovsky
Cc: Juergen Gross
Cc: Stefano Stabellini
Cc: Paul
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/mtk-svs.c | 477 -
1 file changed, 471 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c
index 5c315467747d..17e61acce868 100644
--- a/drivers/soc/mediatek
The purpose of SVS is to help find the suitable voltages
for DVFS. Therefore, if SVS bank voltages are concerned
to be wrong, we can adjust SVS bank voltages by this patch.
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/mtk-svs.c | 325 +
1 file changed, 325
The Smart Voltage Scaling(SVS) engine is a piece of hardware
which calculates suitable SVS bank voltages to OPP voltage table.
Then, DVFS driver could apply those SVS bank voltages to PMIC/Buck
when receiving OPP_EVENT_ADJUST_VOLTAGE.
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/Kconfig
Document the binding for enabling mtk svs on MediaTek SoC.
Signed-off-by: Roger Lu
---
.../bindings/soc/mediatek/mtk-svs.yaml| 80 +++
1 file changed, 80 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
diff --git a
add compitable/reg/irq/clock/efuse setting in svs node
Signed-off-by: Roger Lu
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index
add compitable/reg/irq/clock/efuse/reset setting in svs node
Signed-off-by: Roger Lu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
Signed-off-by: Roger Lu
---
.../devicetree/bindings/soc/mediatek/mtk-svs.yaml| 9 +
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
index bb8c345a0c0a
- Check "supplier links.status DL_DEV_DRIVER_BOUND" to make
sure supplier is ready after doing device_link_add()
Roger Lu (7):
[v11,1/7]: dt-bindings: soc: mediatek: add mtk svs dt-bindings
[v11,2/7]: arm64: dts: mt8183: add svs device information
[v11,3/7]: soc: mediatek: SVS: int
Hi Nicolas,
[snip]
> >
> > > +
> > > + /* Svs efuse parsing */
> > > + ft_pgm = (svsp->efuse[0] >> 4) & GENMASK(3, 0);
> > > +
> > > + for (idx = 0; idx < svsp->bank_num; idx++) {
> > > + svsb = &svsp->banks[idx];
> > > +
> > > + if (ft_pgm <= 1)
> >
Hi Nicolas,
On Mon, 2021-01-04 at 17:27 +0800, Nicolas Boichat wrote:
> On Mon, Jan 4, 2021 at 4:51 PM Roger Lu wrote:
> >
> >
> > Hi Nicolas,
> >
> > Thanks for all the advices.
> >
> > On Thu, 2020-12-31 at 10:10 +0800, Nicolas Boichat wrote:
&
Hi Nicolas,
Thanks for all the advices.
On Thu, 2020-12-31 at 10:10 +0800, Nicolas Boichat wrote:
> On Sun, Dec 27, 2020 at 6:55 PM Roger Lu wrote:
> >
> > The Smart Voltage Scaling(SVS) engine is a piece of hardware
> > which calculats suitable SVS bank voltages
cuting.
If switching to WARN_ON is indeed fine it needs to be explained in the
commit message that returning to the caller(s) with
HYPERVISOR_grant_table_op having returned an error code is fine, and
that it's not going to create other issues, like memory corruption or
leaks.
Thanks, Roger.
Document the binding for enabling mtk svs on MediaTek SoC.
Signed-off-by: Roger Lu
---
.../bindings/soc/mediatek/mtk-svs.yaml| 75 +++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
diff --git a
The Smart Voltage Scaling(SVS) engine is a piece of hardware
which calculats suitable SVS bank voltages to OPP voltage table.
Then, DVFS driver could apply those SVS bank voltages to PMIC/Buck
when receiving OPP_EVENT_ADJUST_VOLTAGE.
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/Kconfig
Signed-off-by: Roger Lu
---
.../bindings/soc/mediatek/mtk-svs.yaml| 26 +++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
b/Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml
index 9c7da0acd82f
The purpose of SVS is to help find the suitable voltages
for DVFS. Therefore, if SVS bank voltages are concerned
to be wrong, we can adjust SVS bank voltages by this patch.
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/mtk-svs.c | 324 +
1 file changed, 324
Signed-off-by: Roger Lu
---
drivers/soc/mediatek/mtk-svs.c | 494 -
1 file changed, 488 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c
index ef3aeb4b7dbd..9201e5480c6c 100644
--- a/drivers/soc/mediatek
add compitable/reg/irq/clock/efuse setting in svs node
Signed-off-by: Roger Lu
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index
y SVS header file.
- Add mt8192 SVS driver.
- Change linux license to GPL-2.0-only.
- Squash "struct mtk_svs" members into "struct svs_platform"
and remove "struct mtk_svs".
Roger Lu (7):
[v10,1/7]: dt-bindings: soc: mediatek: add mtk svs dt-bindings
[v10,2/7]:
add compitable/reg/irq/clock/efuse/reset setting in svs node
Signed-off-by: Roger Lu
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>
> No, I don't think so. At least in the CONFIG_ZONE_DEVICE case the
> initial list in a PV dom0 is populated from extra memory (basically
> the same, but not marked as zone device memory explicitly).
I assume it's fine for us to then use page->zone_device_data even if
the page is not explicitly marked as ZONE_DEVICE memory?
If that's fine, add my:
Acked-by: Roger Pau Monné
To both patches, and thank you very much for fixing this!
Roger.
ry strange to put a pfn with a
> > struct page into a VMA and then deliberately not take the refcount for
> > the duration of that pfn being in the VMA?
> >
> > What prevents memunmap_pages() from progressing while VMAs still point
> > at the memory?
>
> Agreed. A
Hi Peter,
On 25/11/2020 14:49, Roger Quadros wrote:
Hardware based role switch is broken as the driver always skips it.
Fix this by registering for SW role switch only if 'usb-role-switch'
property is present in the device tree.
Fixes: 50642709f659 ("usb: cdns3: core: quit
Hardware based role switch is broken as the driver always skips it.
Fix this by registering for SW role switch only if 'usb-role-switch'
property is present in the device tree.
Fixes: 50642709f659 ("usb: cdns3: core: quit if it uses role switch class")
Signed-off-by: Roger Q
On 25/11/2020 02:36, Peter Chen wrote:
On 20-11-24 14:22:25, Roger Quadros wrote:
Peter,
On 24/11/2020 13:47, Peter Chen wrote:
On 20-11-24 12:33:34, Roger Quadros wrote:
I am sorry about that. Do you use role switch /sys entry, if you have
used, I prefer using "usb-role-switch"
Peter,
On 24/11/2020 13:47, Peter Chen wrote:
On 20-11-24 12:33:34, Roger Quadros wrote:
I am sorry about that. Do you use role switch /sys entry, if you have
used, I prefer using "usb-role-switch" property at dts to judge if SoC
OTG signals or external signals for role switch. I
+Heikki
Peter,
On 24/11/2020 11:57, Peter Chen wrote:
Best regards,
Peter Chen
-Original Message-
From: Roger Quadros
Sent: 2020年11月24日 17:39
To: Peter Chen
Cc: paw...@cadence.com; gre...@linuxfoundation.org; ba...@kernel.org;
linux-...@vger.kernel.org; linux-kernel
Peter,
On 24/11/2020 08:43, Peter Chen wrote:
On 20-11-23 13:50:51, Roger Quadros wrote:
This reverts commit 50642709f6590fe40afa6d22c32f23f5b842aed5.
This commit breaks hardware based role switching on TI platforms.
cdns->role_sw is always going to be non-zero as it is a pointer
to
is not required by the platform.
Signed-off-by: Roger Quadros
---
drivers/usb/cdns3/core.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c
index a0f73d4711ae..4c1445cf2ad0 100644
--- a/drivers/usb/cdns3/core.c
+++ b/drivers/usb/cdns3/cor
Some platforms (e.g. TI) will not have any platform data which will
lead to NULL pointer dereference if we don't check for NULL pdata.
Fixes: a284b7fd1b8f ("usb: cdns3: add quirk for enable runtime pm by default")
Reported-by: Nishanth Menon
Signed-off-by: Roger Quadros
---
dr
d a fallthrough like it's done below in
XenbusStateClosed.
Also, FWIW, I think clang's fallthrough warnings are a bit too verbose.
Falling through to a break like the case here shouldn't cause a
warning IMO, falling through to anything != break should indeed cause
those warnings to appear.
Thanks, Roger.
On 12/11/2020 03:49, Nishanth Menon wrote:
The default state of a device tree node is "okay". There is no specific
use of explicitly adding status = "okay" in the board dts.
Fixes: 7e7e7dd51d06 ("arm64: dts: ti: k3-am654-base-board: enable USB1")
Signed-off-by: Nis
> "Support for running in Xen PVH mode"?
>
> Yeah, just dropping "guest" would be fine with me. No idea how
> to reflect that PVH Dom0 isn't supported, yet.
The fact that it isn't supported by Xen shouldn't be reflected on the
Linux configuration, as it's independent. Ie: you could run this Linux
kernel on a future version of Xen where PVH dom0 is supported.
There's already a warning printed by Xen when booting PVH dom0 about
not being a supported mode.
Thanks, Roger.
On Thu, Oct 15, 2020 at 04:37:52PM +0200, Jürgen Groß wrote:
> On 15.10.20 16:24, Roger Pau Monne wrote:
> > Assume that reads and writes to the variable will be atomic. The worse
> > that could happen is that one of the purges removes a partially
> > written percentage of
Assume that reads and writes to the variable will be atomic. The worse
that could happen is that one of the purges removes a partially
written percentage of grants, but the cache itself will recover.
Signed-off-by: Roger Pau Monné
---
Cc: Konrad Rzeszutek Wilk
Cc: Jens Axboe
Cc: Boris
Assume that reads and writes to the variable will be atomic. The worse
that could happen is that one of the LRU intervals is not calculated
properly if a partially written value is read, but that would only be
a transient issue.
Signed-off-by: Roger Pau Monné
---
Cc: Konrad Rzeszutek Wilk
Cc
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