Fenghua/Andre,
On 5/10/19 2:29 PM, Yu, Fenghua wrote:
> [CAUTION: External Email]
>
>> On Friday, May 10, 2019 10:40 AM
>> Andre Przywara [mailto:andre.przyw...@arm.com] wrote:
>> To: Yu, Fenghua
>> Cc: Thomas Gleixner ; Ingo Molnar
>> ; Borislav Petkov ; H Peter Anvin
>> ; Luck, Tony ; Chatre,
> ; Ravi V Shankar ;
> Xiaochen Shen ; Arshiya Hayatkhan Pathan
> ; Sai Praneeth Prakhya
> ; Moger, Babu
> Cc: linux-kernel
> Subject: Re: [PATCH v7 00/13] selftests/resctrl: Add resctrl selftest
>
> On Sat, Feb 09, 2019 at 06:50:29PM -0800, Fenghua Yu wrote:
> > With m
kar ;
> Xiaochen Shen ; Arshiya Hayatkhan Pathan
> ; Sai Praneeth Prakhya
> ; Moger, Babu
> Cc: linux-kernel ; Fenghua Yu
>
> Subject: [PATCH v7 00/13] selftests/resctrl: Add resctrl selftest
>
> With more and more resctrl features are being added by Intel, AMD
> and ARM,
From: Fenghua Yu
resctrl tests will be implemented. README is added for the tool first.
Signed-off-by: Fenghua Yu
Signed-off-by: Babu Moger
---
tools/testing/selftests/resctrl/README | 53 ++
1 file changed, 53 insertions(+)
create mode 100644 tools/testing/se
From: Fenghua Yu
The resctrl selftest will be maintained by RDT maintainers.
Signed-off-by: Fenghua Yu
Signed-off-by: Babu Moger
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 32d7..16359bc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@
From: Arshiya Hayatkhan Pathan
Cache Allocation Technology (CAT) selftest allocates a portion of
last level cache and starts a benchmark to read each cache
line in this portion of cache. Measure the cache misses in perf and
the misses should be equal to the number of cache lines in this
portion o
From: Sai Praneeth Prakhya
Built-in benchmark fill_buf generates stressful memory bandwidth
and cache traffic.
Later it will be used as a default benchmark by various resctrl tests
such as MBA (Memory Bandwidth Allocation) and MBM (Memory Bandwidth
Monitoring) tests.
Signed-off-by: Sai Praneeth
AMD uses the cache l3 boundary for schemata masks. Update it accordigly.
Signed-off-by: Babu Moger
---
tools/testing/selftests/resctrl/resctrlfs.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tools/testing/selftests/resctrl/resctrlfs.c
b/tools/testing/selftests/r
For now, disable MBA and MBM tests for AMD. Deciding test pass/fail
is not clear right now. We can enable when we have some clarity.
Signed-off-by: Babu Moger
---
tools/testing/selftests/resctrl/cat_test.c | 2 +-
tools/testing/selftests/resctrl/resctrl_tests.c | 4 ++--
2 files changed, 3
From: Arshiya Hayatkhan Pathan
MBM (Memory Bandwidth Monitoring) test is the first implemented selftest.
It starts a stressful memory bandwidth benchmark and assigns the
bandwidth pid in a resctrl monitoring group. Read and compare perf IMC
counter and MBM total bytes for the benchmark. The numbe
From: Arshiya Hayatkhan Pathan
MBA (Memory Bandwidth Allocation) test starts a stressful memory
bandwidth benchmark and allocates memory bandwidth from 100% down
to 10% for the benchmark process. For each allocation, compare
perf IMC counter and mbm total bytes from resctrl. The difference
betwee
From: Sai Praneeth Prakhya
The callback starts a child process and puts the child pid in created
resctrl group with specified memory bandwidth in schemata. The child
starts running benchmark.
Signed-off-by: Sai Praneeth Prakhya
Signed-off-by: Arshiya Hayatkhan Pathan
Signed-off-by: Fenghua Yu
RESCTRL feature is supported both on Intel and AMD now. Some features
are implemented differently. Add vendor detection mechanism. Use the vendor
check where there are differences.
Signed-off-by: Babu Moger
---
tools/testing/selftests/resctrl/resctrl.h | 13 +
tools/testing/selftests/r
With more and more resctrl features are being added by Intel, AMD
and ARM, a test tool is becoming more and more useful to validate
that both hardware and software functionalities work as expected.
We introduce resctrl selftest to cover resctrl features on both
X86 and ARM architectures. It first
From: Arshiya Hayatkhan Pathan
Cache QoS Monitoring (CQM) selftest starts stressful cache benchmark
with specified size of memory to access the cache. Last Level cache
occupancy reported by CQM should be close to the size of the memory.
Signed-off-by: Arshiya Hayatkhan Pathan
Signed-off-by: Sai
From: Sai Praneeth Prakhya
The basic resctrl file system operations and data are added for future
usage by resctrl selftest tool.
Signed-off-by: Sai Praneeth Prakhya
Signed-off-by: Arshiya Hayatkhan Pathan
Signed-off-by: Fenghua Yu
Signed-off-by: Babu Moger
---
tools/testing/selftests/resct
From: Sai Praneeth Prakhya
Total memory bandwidth can be monitored from perf IMC counter and from
resctrl file system. Later the two will be compared to verify the total
memory bandwidth read from resctrl is correct.
Signed-off-by: Sai Praneeth Prakhya
Signed-off-by: Arshiya Hayatkhan Pathan
S
On 1/16/19 1:13 PM, Fenghua Yu wrote:
> On Wed, Jan 16, 2019 at 03:54:07PM +0000, Moger, Babu wrote:
>> Hi Fenghua/Sai/Arshiya,
>> We were thinking of updating these selftests to work on both Intel and
>> AMD. What do you guys think?
>>
>> If that is ok, I can
Hi Fenghua/Sai/Arshiya,
We were thinking of updating these selftests to work on both Intel and
AMD. What do you guys think?
If that is ok, I can update these patches and resubmit. If you have
already updated, please post the latest series. I will use the latest
version. Please let me know.
Thank
Hi Fenghua/Sai/Arshiya,
Few comments on this patch below. Sorry for the late comment.
On 12/21/18 6:20 PM, Fenghua Yu wrote:
> From: Arshiya Hayatkhan Pathan
>
> Cache Allocation Technology (CAT) selftest allocates a portion of
> last level cache and starts a benchmark to read each cache
> line
Looks good to me. Sanity tested the patch.
> -Original Message-
> From: Borislav Petkov
> Sent: Tuesday, January 8, 2019 11:14 AM
> To: Ingo Molnar
> Cc: Linus Torvalds ; x86-ml
> ; lkml ; James Morse
> ; Moger, Babu ;
> Fenghua Yu ; Reinette Chatre
> ; Tony L
Hi Fenghua,
> -Original Message-
> From: Fenghua Yu
> Sent: Friday, December 21, 2018 6:21 PM
> To: Thomas Gleixner ; Ingo Molnar
> ; H Peter Anvin ; Tony Luck
> ; Peter Zijlstra ; Reinette
> Chatre ; Moger, Babu
> ; James Morse ;
> Xiaochen Shen ; Ravi V Shank
Fenghua, Sai,
Couple of problems with these patches(see below). Please check again.
> -Original Message-
> From: Fenghua Yu
> Sent: Friday, December 21, 2018 6:21 PM
> To: Thomas Gleixner ; Ingo Molnar
> ; H Peter Anvin ; Tony Luck
> ; Peter Zijlstra ; Reinette
>
Hi Jan,
> -Original Message-
> From: Jan Engelhardt
> Sent: Sunday, December 23, 2018 12:27 PM
> To: Moger, Babu
> Cc: t...@linutronix.de; mi...@redhat.com; b...@alien8.de; cor...@lwn.net;
> fenghua...@intel.com; reinette.cha...@intel.com; pet...@in
The static checker(smatch) reports the following error after the
commit a36c5ff560fb ("x86/resctrl: Bring cbm_validate() into the
resource structure").
arch/x86/kernel/cpu/resctrl//ctrlmondata.c:227 parse_cbm()
error: uninitialized symbol 'cbm_val'.
arch/x86/kernel/cpu/resctrl//ctrlmondata.c:236 p
Boris,
> -Original Message-
> From: Borislav Petkov
> Sent: Wednesday, November 28, 2018 2:30 PM
> To: Moger, Babu
> Cc: t...@linutronix.de; mi...@redhat.com; h...@zytor.com;
> x...@kernel.org; fenghua...@intel.com; reinette.cha...@intel.com;
> dan.carpen...@ora
Fix the following compiler warning caused by recent change.
arch/x86/kernel/cpu/resctrl/ctrlmondata.c:227 parse_cbm()
error: uninitialized symbol 'cbm_val'
Fixes: a36c5ff560fb ("x86/resctrl: Bring cbm_validate() into the resource
structure")
Reported-by: Dan Carpenter
Signed-off-by: Babu Moger
Fix the compiler warning caused by a recent change.
Fixes: a36c5ff560fb ("x86/resctrl: Bring cbm_validate() into the resource
structure")
Reported-by: Dan Carpenter
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
d
My bad.. Sorry about this. I think this should also go to
sta...@vger.kernel.org
> -Original Message-
> From: Luiz Capitulino
> Sent: Friday, November 23, 2018 12:27 PM
> To: Liran Alon
> Cc: Paolo Bonzini ; Moger, Babu
> ; k...@vger.kernel.org; linux-
> ker...@vger
On 10/31/18 4:02 PM, Fenghua Yu wrote:
> From: Sai Praneeth Prakhya
>
> Total memory bandwidth can be monitored from perf IMC counter and from
> resctrl file system. Later the two will be compared to verify the total
> memory bandwidth read from resctrl is correct.
>
> Signed-off-by: Sai Prane
On 10/31/18 4:02 PM, Fenghua Yu wrote:
> From: Sai Praneeth Prakhya
>
> The callback starts a child process and puts the child pid in created
> resctrl group with specified memory bandwidth in schemata. The child
> starts running benchmark.
>
> Signed-off-by: Sai Praneeth Prakhya
> Signed-off
Boris,
On 11/12/18 11:56 AM, Borislav Petkov wrote:
> On Fri, Nov 09, 2018 at 08:52:27PM +0000, Moger, Babu wrote:
>> As AMD is starting to support RDT(or QOS) features, rename
>> the RDT functions and definitions to more generic names.
>>
>> Replace intel_rdt
Initialize the resource functions that are different between the
vendors. Some features are initialized differently between the vendors.
Add _intel suffix to Intel specific functions.
For example, MBA feature varies significantly between Intel and AMD.
Separate the initialization of these resource
Idea is to bring all the functions that are different between the
vendors into resource structure and initialize them dynamically.
Add _intel suffix to Intel specific functions.
Following function is implemented separately for each vendors.
cbm_validate : Cache bitmask validate function. AMD allo
Update the MAINTAINERS to reflect the changed file(and documentation)
names in arch/x86/kernel/cpu. The file names have changed from
intel_rdt* to resctrl*.
Signed-off-by: Babu Moger
---
MAINTAINERS | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINE
Enables QOS feature on AMD.
Following QoS sub-features are supported in AMD if the underlying
hardware supports it.
- L3 Cache allocation enforcement
- L3 Cache occupancy monitoring
- L3 Code-Data Prioritization support
- Memory Bandwidth Enforcement(Allocation)
The specification for this feat
Jon,
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Jon Masters
> Sent: Friday, November 2, 2018 1:43 AM
> To: Moger, Babu ; t...@linutronix.de;
> mi...@redhat.com; h...@zytor.com; reinette.cha...@intel.com;
>
Fenghua,
> -Original Message-
> From: Fenghua Yu
> Sent: Tuesday, October 30, 2018 1:36 PM
> To: Moger, Babu ; Fenghua Yu
>
> Cc: Thomas Gleixner ; Ingo Molnar
> ; H Peter Anvin ; Tony Luck
> ; Peter Zijlstra ; Reinette
> Chatre ; James Morse
> ; Ravi V Sh
Hi Fenghua,
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Fenghua Yu
> Sent: Thursday, October 25, 2018 6:07 PM
> To: Thomas Gleixner ; Ingo Molnar
> ; H Peter Anvin ; Tony Luck
> ; Peter Zijlstra ; Reinette
&
Fenghua/Sai,
> -Original Message-
> From: Fenghua Yu
> Sent: Thursday, October 25, 2018 6:07 PM
> To: Thomas Gleixner ; Ingo Molnar
> ; H Peter Anvin ; Tony Luck
> ; Peter Zijlstra ; Reinette
> Chatre ; Moger, Babu
> ; James Morse ; Ravi V
> Shankar ; Sai P
Hi Fenghua/Sai,
> -Original Message-
> From: Fenghua Yu
> Sent: Thursday, October 25, 2018 6:07 PM
> To: Thomas Gleixner ; Ingo Molnar
> ; H Peter Anvin ; Tony Luck
> ; Peter Zijlstra ; Reinette
> Chatre ; Moger, Babu
> ; James Morse ; Ravi V
> Shankar ; Sai P
Fenghua, Sai
> -Original Message-
> From: Fenghua Yu
> Sent: Thursday, October 25, 2018 6:07 PM
> To: Thomas Gleixner ; Ingo Molnar
> ; H Peter Anvin ; Tony Luck
> ; Peter Zijlstra ; Reinette
> Chatre ; Moger, Babu
> ; James Morse ; Ravi V
> Shankar ; Sai P
Hi Fenghua, Sai,
> -Original Message-
> From: Fenghua Yu
> Sent: Thursday, October 25, 2018 6:07 PM
> To: Thomas Gleixner ; Ingo Molnar
> ; H Peter Anvin ; Tony Luck
> ; Peter Zijlstra ; Reinette
> Chatre ; Moger, Babu
> ; James Morse ; Ravi V
> Shankar ; Sai P
On 10/17/2018 12:28 PM, Prakhya, Sai Praneeth wrote:
>>> No, the selftest in this patch set will not replace intel-cmt-cat or
>>> vice versa.
>>>
>>> The selftest in this patch set has a different purpose from intel-cmt-cat:
>>> the selftest is a test tool which validates resctrl functionalities
On 10/17/2018 01:03 PM, Moger, Babu wrote:
> Hi Fenghua,
> My few comments.
>
> On 10/17/2018 09:40 AM, Moger, Babu wrote:
>>
>>
>> On 10/16/2018 03:32 PM, Fenghua Yu wrote:
>>>> From: Moger, Babu [mailto:babu.mo...@amd.com]
>>>> On 10/1
Hi Fenghua,
My few comments.
On 10/17/2018 09:40 AM, Moger, Babu wrote:
>
>
> On 10/16/2018 03:32 PM, Fenghua Yu wrote:
>>> From: Moger, Babu [mailto:babu.mo...@amd.com]
>>> On 10/16/2018 11:56 AM, Fenghua Yu wrote:
>>>> With more and more resctrl fea
Hi Fenghua,
On 10/16/2018 06:45 PM, Fenghua Yu wrote:
> On Mon, Oct 15, 2018 at 08:55:49PM +0000, Moger, Babu wrote:
>> update_mba_bw : Feedback loop bandwidth update functionality is not
>> needed for AMD.
>
> Will you implement update_mba_bw() for AMD in
On 10/16/2018 06:48 PM, Fenghua Yu wrote:
> On Mon, Oct 15, 2018 at 08:55:54PM +0000, Moger, Babu wrote:
>> From: Sherry Hurwitz
>>
>> The feature bit X86_FEATURE_MBA is detected via CPUID leaf 0x8008
>> EBX Bit 06. This bit indicates the support of AMD's MB
On 10/16/2018 03:32 PM, Fenghua Yu wrote:
>> From: Moger, Babu [mailto:babu.mo...@amd.com]
>> On 10/16/2018 11:56 AM, Fenghua Yu wrote:
>>> With more and more resctrl features are being added by Intel, AMD and
>>> ARM, a test tool is becoming more and more use
Hi Fenghua,
On 10/16/2018 11:56 AM, Fenghua Yu wrote:
> With more and more resctrl features are being added by Intel, AMD
> and ARM, a test tool is becoming more and more useful to validate
> that both hardware and software functionalities work as expected.
I like the initiative here. It is alwa
This series adds support for AMD64 architectural extensions for Platform
Quality of Service. These extensions are intended to provide for the
monitoring of the usage of certain system resources by one or more
processors and for the separate allocation and enforcement of limits on
the use of certain
Enables QOS feature on AMD.
Following QoS sub-features are supported in AMD if the underlying
hardware supports it.
- L3 Cache allocation enforcement
- L3 Cache occupancy monitoring
- L3 Code-Data Prioritization support
- Memory Bandwidth Enforcement(Allocation)
The specification for this feat
Update the MAINTAINERS to reflect the changed file(and documentation)
names in arch/x86/kernel/cpu. The file names have changed from
intel_rdt* to resctrl*.
Signed-off-by: Babu Moger
---
MAINTAINERS | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINE
Separate the call sequence for rdt_quirks and MBA feature.
This is in preparation to handle vendor differences in these
call sequences.
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/resctrl.c | 29 +++--
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/a
From: Sherry Hurwitz
The feature bit X86_FEATURE_MBA is detected via CPUID leaf 0x8008
EBX Bit 06. This bit indicates the support of AMD's MBA feature.
This feature is supported by both Intel and AMD. But they are detected
different CPUID leaves.
Signed-off-by: Sherry Hurwitz
Signed-off-by
Initialize the resource functions that are different between the
vendors. Some features are initialized differently between the vendors.
Add _intel suffix to Intel specific functions.
For example, MBA feature varies significantly between Intel and AMD.
Separate the initialization of these resource
Introduces the new config parameter AMD_QOS. This parameter will be
used to enable cache and memory bandwidth allocation and monitoring
features on AMD processors. This will enable common config parameter
RESCTRL if selected.
Signed-off-by: Babu Moger
---
arch/x86/Kconfig | 17 -
Bring all the macros to resctrl.h and rename for consistency.
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/resctrl.c | 3 ---
arch/x86/kernel/cpu/resctrl.h | 5 +
arch/x86/kernel/cpu/resctrl_monitor.c | 7 ++-
3 files changed, 7 insertions(+), 8 deletions(-)
diff --
Rename intel_rdt_ui.txt to generic resctrl_ui.txt and update the
documentation for AMD.
Signed-off-by: Babu Moger
---
Documentation/x86/{intel_rdt_ui.txt => resctrl_ui.txt} | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
rename Documentation/x86/{intel_rdt_ui.txt => resctrl_ui.tx
Use newly added config parameter RESCTRL to compile sources.
This is common parameter across both Intel and AMD.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/resctrl_sched.h | 4 ++--
arch/x86/kernel/cpu/Makefile | 4 ++--
include/linux/sched.h| 2 +-
3 files change
Bring all resource functions that are different between the vendors
into resource structure and initialize them dynamically.
Add _intel suffix to Intel specific functions.
Implement these functions separately for each vendors.
update_mba_bw : Feedback loop bandwidth update functionality is not
New generation of AMD processors start supporting RDT(or QOS) features.
With more than one vendors supporting these features, it seems more
appropriate to rename these files.
Changed intel_rdt to resctrl where applicable.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/{intel_rdt_sched.h =>
As AMD is starting to support RDT(or QOS) features, rename
the RDT functions and definitions to more generic names.
Replace intel_rdt to resctrl where applicable.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/resctrl_sched.h | 24
arch/x86/kernel/cpu/resctrl.c
Introduces a new config parameter RESCTRL.
This will be used as a common config parameter for both Intel and AMD.
Each vendor will have their own config parameter to enable RDT feature.
One for Intel(INTEL_RDT) and one for AMD(AMD_QOS). It can be enabled or
disabled separately. The new parameter R
On 10/12/2018 02:40 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 10/11/2018 1:33 PM, Moger, Babu wrote:
>> @@ -883,20 +883,20 @@ static int __init intel_rdt_late_init(void)
>> rdt_online = state;
>>
>> for_each_alloc_capable_rdt_resource(r)
>
Hi Reinette,
On 10/12/2018 02:07 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 10/11/2018 1:33 PM, Moger, Babu wrote:
>> New generation of AMD processors start supporting RDT(or QOS) features.
>> With more than one vendors supporting these features, it seems more
>>
On 10/12/2018 09:43 AM, Borislav Petkov wrote:
> On Fri, Oct 12, 2018 at 02:40:50PM +0000, Moger, Babu wrote:
>> That is correct. CPU_SUP_AMD implicitly means x86.
>> To be more specific, I will change it to
>> "depends on X86_64 && CPU_SUP_AMD" as this fe
Boris,
On 10/11/2018 05:02 PM, Borislav Petkov wrote:
> On Thu, Oct 11, 2018 at 08:33:35PM +0000, Moger, Babu wrote:
>> Introduces the new config parameter AMD_QOS. This parameter will be
>> used to enable cache and memory bandwidth allocation and monitoring
>> features on
Introduces the new config parameter AMD_QOS. This parameter will be
used to enable cache and memory bandwidth allocation and monitoring
features on AMD processors. This will enable common config parameter
RESCTRL if selected.
Signed-off-by: Babu Moger
---
arch/x86/Kconfig | 17 -
Bring all resource functions that are different between the vendors
into resource structure and initialize them dynamically.
Add _intel suffix to Intel specific functions.
Implement these functions separately for each vendors.
update_mba_bw : Feedback loop bandwidth update functionality is not
Initialize the resource functions that are different between the
vendors. Some features are initialized differently between the vendors.
Add _intel suffix to Intel specific functions.
For example, MBA feature varies significantly between Intel and AMD.
Separate the initialization of these resource
From: Sherry Hurwitz
The feature bit X86_FEATURE_MBA is detected via CPUID leaf 0x8008
EBX Bit 06. This bit indicates the support of AMD's MBA feature.
This feature is supported by both Intel and AMD. But they are detected
different CPUID leaves.
Signed-off-by: Sherry Hurwitz
Signed-off-by
Enables QOS feature on AMD.
Following QoS sub-features are supported in AMD if the underlying
hardware supports it.
- L3 Cache allocation enforcement
- L3 Cache occupancy monitoring
- L3 Code-Data Prioritization support
- Memory Bandwidth Enforcement(Allocation)
The specification for this feat
Use newly added config parameter RESCTRL to compile sources.
This is common parameter across both Intel and AMD.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/resctrl_sched.h | 4 ++--
arch/x86/kernel/cpu/Makefile | 4 ++--
include/linux/sched.h| 2 +-
3 files change
Bring all the macros to resctrl.h and rename for consistency.
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/resctrl.c | 3 ---
arch/x86/kernel/cpu/resctrl.h | 5 +
arch/x86/kernel/cpu/resctrl_monitor.c | 7 ++-
3 files changed, 7 insertions(+), 8 deletions(-)
diff --
Introduces a new config parameter RESCTRL.
This will be used as a common config parameter for both Intel and AMD.
Each vendor will have their own config parameter to enable RDT feature.
One for Intel(INTEL_RDT) and one for AMD(AMD_QOS). It can be enabled or
disabled separately. The new parameter R
As AMD is starting to support RDT(or QOS) features, rename
the RDT functions and definitions to more generic names.
Replace intel_rdt to resctrl where applicable.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/resctrl_sched.h | 24
arch/x86/kernel/cpu/resctrl.c
This series adds support for AMD64 architectural extensions for Platform
Quality of Service. These extensions are intended to provide for the
monitoring of the usage of certain system resources by one or more
processors and for the separate allocation and enforcement of limits on
the use of certain
New generation of AMD processors start supporting RDT(or QOS) features.
With more than one vendors supporting these features, it seems more
appropriate to rename these files.
Changed intel_rdt to resctrl where applicable.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/{intel_rdt_sched.h =>
Separate the call sequence for rdt_quirks and MBA feature.
This is in preparation to handle vendor differences in these
call sequences.
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/resctrl.c | 29 +++--
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/a
On 10/10/2018 12:53 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 10/10/2018 7:11 AM, Moger, Babu wrote:
>> On 10/09/2018 05:01 PM, Reinette Chatre wrote:
>>> On 10/9/2018 2:17 PM, Moger, Babu wrote:
>>>> On 10/09/2018 11:39 AM, Reinette Chatre wrote:
>
Thomas,
On 10/10/2018 09:16 AM, Thomas Gleixner wrote:
> Babu,
>
> On Wed, 10 Oct 2018, Moger, Babu wrote:
>> On 10/09/2018 05:01 PM, Reinette Chatre wrote:
>>> As far as all the code you touch is concerned it may be easier and cause
>>> less confusion for now
Hi Reinette,
On 10/09/2018 05:01 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 10/9/2018 2:17 PM, Moger, Babu wrote:
>> On 10/09/2018 11:39 AM, Reinette Chatre wrote:
>>> Hi Babu,
>>>
>>> On 10/5/2018 1:55 PM, Moger, Babu wrote:
>>>> New
Hi Reinette,
On 10/09/2018 11:39 AM, Reinette Chatre wrote:
> Hi Babu,
>
> On 10/5/2018 1:55 PM, Moger, Babu wrote:
>> New generation of AMD processors start support RDT(or QOS) features.
>> With more than one vendors supporting these features, it seems more
>> approp
On 10/09/2018 12:18 PM, Reinette Chatre wrote:
> Hi Babu,
>
> On 10/5/2018 1:55 PM, Moger, Babu wrote:
>> diff --git a/arch/x86/kernel/cpu/rdt_ctrlmondata.c
>> b/arch/x86/kernel/cpu/rdt_ctrlmondata.c
>> index 812cc5c5e39e..ee3e8389d8d2 100644
>> --- a/arch
> -Original Message-
> From: Borislav Petkov
> Sent: Friday, October 5, 2018 4:31 PM
> To: Moger, Babu
> Cc: t...@linutronix.de; mi...@redhat.com; h...@zytor.com;
> reinette.cha...@intel.com; fenghua...@intel.com; james.mo...@arm.com;
> vikas.shiva...@li
Hi Fenghua,
> -Original Message-
> From: Fenghua Yu
> Sent: Friday, October 5, 2018 6:39 PM
> To: Moger, Babu
> Cc: t...@linutronix.de; mi...@redhat.com; h...@zytor.com;
> reinette.cha...@intel.com; fenghua...@intel.com; james.mo...@arm.com;
> vikas.shiva...@li
As AMD is starting to support RDT(or QOS) features, rename
the RDT functions and definitions to more generic names.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/rdt_sched.h | 22 +++---
arch/x86/kernel/cpu/rdt.c | 24
arch/x86/kernel/cpu/
Separate the call sequence for rdt_quirks and MBA feature.
This is in preparation to handle vendor differences in these
call sequences.
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/rdt.c | 29 +++--
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/arch/
Bring all resource functions that are different between the vendors
into resource structure and initialize them dynamically.
Add _intel suffix to Intel specific functions.
Implement these functions separately for each vendors.
update_mba_bw : Feedback loop bandwidth update functionality is not
Introduces the new config parameter AMD_QOS. This parameter will be
used to enable cache and memory bandwidth allocation and monitoring
features on AMD processors. This will enable common config parameter
PLATFORM_QOS if selected.
Signed-off-by: Babu Moger
---
arch/x86/Kconfig | 17 +
Use newly added config parameter PLATFORM_QOS to compile sources.
This is common parameter across both Intel and AMD.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/rdt_sched.h | 4 ++--
arch/x86/kernel/cpu/Makefile | 4 ++--
include/linux/sched.h| 2 +-
3 files changed, 5 in
Introduces a new config parameter PLATFORM_QOS.
This will be used as a common config parameter for both Intel and AMD.
Each vendor will have their own config parameter to enable RDT feature.
One for Intel(INTEL_RDT) and one for AMD(AMD_QOS). It can be enabled or
disabled separately. The new parame
Initialize the resource functions that are different between the
vendors. Some features are initialized differently between the vendors.
Add _intel suffix to Intel specific functions.
For example, MBA feature varies significantly between Intel and AMD.
Separate the initialization of these resource
New generation of AMD processors start support RDT(or QOS) features.
With more than one vendors supporting these features, it seems more
appropriate to rename these files.
Signed-off-by: Babu Moger
---
arch/x86/include/asm/{intel_rdt_sched.h => rdt_sched.h} | 0
arch/x86/kernel/cpu/Makefile
From: Sherry Hurwitz
The feature bit X86_FEATURE_MBA is detected via CPUID leaf 0x8008
EBX Bit 06. This bit indicates the support of AMD's MBA feature.
This feature is supported by both Intel and AMD. But they are detected
different CPUID leaves.
Signed-off-by: Babu Moger
Signed-off-by: Sh
Enables QOS feature on AMD.
Following QoS sub-features are supported in AMD if the underlying
hardware supports it.
- L3 Cache allocation enforcement
- L3 Cache occupancy monitoring
- L3 Code-Data Prioritization support
- Memory Bandwidth Enforcement(Allocation)
There are differences in the wa
This series adds support for AMD64 architectural extensions for Platform
Quality of Service. These extensions are intended to provide for the
monitoring of the usage of certain system resources by one or more
processors and for the separate allocation and enforcement of limits on
the use of certain
Bring all the macros to rdt.h and rename for consistency.
Signed-off-by: Babu Moger
---
arch/x86/kernel/cpu/rdt.c | 3 ---
arch/x86/kernel/cpu/rdt.h | 5 +
arch/x86/kernel/cpu/rdt_monitor.c | 7 ++-
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/arch/x86/k
Hi James,
On 10/05/2018 11:20 AM, James Morse wrote:
> Hi Babu,
>
> On 24/09/18 20:19, Moger, Babu wrote:
>> Enables QOS feature on AMD.
>> Following QoS sub-features are supported in AMD if the underlying
>> hardware supports it.
>> - L3 Cache allocation enf
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