Thanks Martin.
On 2/5/2019 3:37 AM, Martin K. Petersen wrote:
> Joao,
>
>> Currently I am managing the Synopsys drivers & tools team (full-time) and
>> so I am passing the DWC UFS driver maintenance to Pedro Sousa.
> Applied to 5.1/scsi-queue, thanks.
>
Hello Bart,
First of all thanks for the feedback.
On 1/30/2019 5:54 PM, Bart Van Assche wrote:
> On Wed, 2019-01-30 at 18:48 +0100, Joao Pinto wrote:
>> Currently I am managing the Synopsys drivers & tools team (full-time) and
>> so I am passing the DWC UFS driver mainten
Currently I am managing the Synopsys drivers & tools team (full-time) and
so I am passing the DWC UFS driver maintenance to Pedro Sousa.
Signed-off-by: Joao Pinto
Cc: Pedro Sousa
Cc: Marc Gonzalez
Cc: Alex Lemberg
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Currently I am managing the Synopsys drivers & tools team (full-time) and so I
am passing the pcie-designware maintenance to Gustavo.
Signed-off-by: Joao Pinto
CC: Gustavo Pimentel
CC: Jingoo Han
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINE
--
> drivers/pci/endpoint/functions/pci-epf-test.c | 7 +
> include/linux/pci-epc.h| 8 ++
> 7 files changed, 206 insertions(+), 27 deletions(-)
>
Thanks for this patch-set.
Reviewed-by: Joao Pinto
ly, convert the
> existing function to a managed version.
>
> CC: Jingoo Han
> CC: Joao Pinto
> CC: Lorenzo Pieralisi
> Signed-off-by: Jan Kiszka
> ---
> drivers/pci/dwc/pcie-designware-host.c | 2 +-
> drivers/pci/host/pci-aardvark.c| 2 +-
> drivers/pci/
ns/pci-epf-test.c
> +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
> @@ -435,6 +435,13 @@ static int pci_epf_test_bind(struct pci_epf *epf)
> if (WARN_ON_ONCE(!epc))
> return -EINVAL;
>
> + if (epc->features & EPC_FEATURE_NO_LINKUP_NOTIFIER)
> + epf_test->linkup_notifier = false;
> + else
> + epf_test->linkup_notifier = true;
> +
> + epf_test->test_reg_bar = EPC_FEATURE_GET_BAR(epc->features);
> +
> ret = pci_epc_write_header(epc, epf->func_no, header);
> if (ret) {
> dev_err(dev, "configuration header write failed\n");
> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> index af657ca..243eaa5 100644
> --- a/include/linux/pci-epc.h
> +++ b/include/linux/pci-epc.h
> @@ -90,8 +90,16 @@ struct pci_epc {
> struct config_group *group;
> /* spinlock to protect against concurrent access of EP controller */
> spinlock_t lock;
> + unsigned intfeatures;
> };
>
> +#define EPC_FEATURE_NO_LINKUP_NOTIFIER BIT(0)
> +#define EPC_FEATURE_BAR_MASK (BIT(1) | BIT(2) | BIT(3))
> +#define EPC_FEATURE_SET_BAR(features, bar) \
> + (features |= (EPC_FEATURE_BAR_MASK & (bar << 1)))
> +#define EPC_FEATURE_GET_BAR(features)\
> + ((features & EPC_FEATURE_BAR_MASK) >> 1)
> +
> #define to_pci_epc(device) container_of((device), struct pci_epc, dev)
>
> #define pci_epc_create(dev, ops)\
>
Acked-by: Joao Pinto
ze = resource_size(pp->cfg) / 2;
> - pp->cfg1_size = resource_size(pp->cfg) / 2;
> + pp->cfg0_size = resource_size(pp->cfg) >> 1;
> + pp->cfg1_size = resource_size(pp->cfg) >> 1;
> pp->cfg0_base = pp->cfg->start;
> pp->cfg1_base = pp->cfg->start + pp->cfg0_size;
> break;
>
Thanks Gustavo!
Acked-by: Joao Pinto
s not being enabled\n");
> + dev_err(pci->dev, "Inbound iATU is not being enabled\n");
>
> return -EBUSY;
> }
> @@ -284,7 +284,7 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int
> index, int bar,
>
> usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> }
> - dev_err(pci->dev, "inbound iATU is not being enabled\n");
> + dev_err(pci->dev, "Inbound iATU is not being enabled\n");
>
> return -EBUSY;
> }
> @@ -313,16 +313,16 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci)
> {
> int retries;
>
> - /* check if the link is up or not */
> + /* Check if the link is up or not */
> for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
> if (dw_pcie_link_up(pci)) {
> - dev_info(pci->dev, "link up\n");
> + dev_info(pci->dev, "Link up\n");
> return 0;
> }
> usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
> }
>
> - dev_err(pci->dev, "phy link never came up\n");
> + dev_err(pci->dev, "Phy link never came up\n");
>
> return -ETIMEDOUT;
> }
> @@ -351,7 +351,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
> if (ret)
> lanes = 0;
>
> - /* set the number of lanes */
> + /* Set the number of lanes */
> val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
> val &= ~PORT_LINK_MODE_MASK;
> switch (lanes) {
> @@ -373,7 +373,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
> }
> dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val);
>
> - /* set link width speed control register */
> + /* Set link width speed control register */
> val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
> switch (lanes) {
>
Acked-by: Joao Pinto
init,
> + .set_num_vectors = dw_plat_set_num_vectors,
> };
>
> static int dw_plat_pcie_establish_link(struct dw_pcie *pci)
>
Yes, in our reference plat driver we should target all the available IRQs.
Thanks!
Acked-by: Joao Pinto
Hi Gustavo,
Às 3:34 PM de 4/17/2018, Gustavo Pimentel escreveu:
> The PCIe controller dual mode is capable of operating in host mode as well
> as endpoint mode by configuration, therefore this patch aims to add
> endpoint mode support to the designware driver.
>
> Signed-off-by: Gustavo Pimentel
ddress_lo = lower_32_bits(msi_target);
> + msg.address_hi = upper_32_bits(msi_target);
>
> if (pp->ops->get_msi_data)
> msg.data = pp->ops->get_msi_data(pp, pos);
>
Thanks for the patch.
Gustavo' patch-set targeting the update of the Interrupt API for
pcie-designware* already does this modification, so I would suggest that we wait
for Gustavo' patch to be stable and get the same modification.
Best regards,
Joao Pinto
Hi Niklas,
Às 11:22 PM de 12/20/2017, Niklas Cassel escreveu:
> On Wed, Dec 20, 2017 at 07:47:41PM +0000, Joao Pinto wrote:
>>
>> Hello to all,
>>
>> Às 5:34 PM de 12/20/2017, Lorenzo Pieralisi escreveu:
>>> On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas Cass
Hello to all,
Às 5:34 PM de 12/20/2017, Lorenzo Pieralisi escreveu:
> On Wed, Dec 20, 2017 at 12:29:21AM +0100, Niklas Cassel wrote:
>> This is a series that adds:
>> - PCI endpoint mode support in the ARTPEC-6 driver.
>> - ARTPEC-7 SoC support in the ARTPEC-6 driver (the SoCs are very similar).
eset_bar(struct dw_pcie *pci, enum pci_barno bar);
> #else
> static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
> @@ -353,6 +356,12 @@ static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
> {
> }
>
> +static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep,
> +u8 interrupt_num)
> +{
> + return 0;
> +}
> +
> static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno
> bar)
> {
> }
>
Acked-by: Joao Pinto
@ struct dw_pcie_ep {
> unsigned long ob_window_map;
> u32 num_ib_windows;
> u32 num_ob_windows;
> + void __iomem*msi_mem;
> + phys_addr_t msi_mem_phys;
> };
>
> struct dw_pcie_ops {
>
Acked-by: Joao Pinto
val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
> val &= ~MSI_CAP_MMC_MASK;
> val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
> + dw_pcie_dbi_ro_wr_en(pci);
> dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
> + dw_pcie_dbi_ro_wr_dis(pci);
>
> return 0;
> }
>
Acked-by: Joao Pinto
IFT)
> #define MSI_CAP_MME_SHIFT 4
> #define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
> #define MSI_MESSAGE_ADDR_L32 0x54
>
Acked-by: Joao Pinto
+#include
> #include
> #include
> #include
> @@ -168,7 +169,7 @@ struct pcie_port {
> const struct dw_pcie_host_ops *ops;
> int msi_irq;
> struct irq_domain *irq_domain;
> - unsigned long msi_data;
> + dma_addr_t msi_data;
> DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
> };
>
>
Makes total sense! Thanks.
Acked-by: Joao Pinto
Hi Niklas,
Às 1:59 PM de 12/13/2017, Niklas Cassel escreveu:
> On Thu, Nov 30, 2017 at 03:28:43PM +, Lorenzo Pieralisi wrote:
>> Jingoo, Joao,
>>
>> I am expecting your testing on the series and ACKs on the dwc related
>> patches please, according to v4 review - I will mark them as needs
>> r
Hi Niklas,
Às 10:56 PM de 12/7/2017, Niklas Cassel escreveu:
> There is nothing that says that number of TX queues == number of RX
> queues. E.g. the ARTPEC-6 SoC has 2 TX queues and 1 RX queue.
>
Yes you are totally right. Our Hardware was configured with 4RX queues and 4TX
queues and that lea
Hello to all,
Às 12:56 AM de 11/8/2017, Bjorn Helgaas escreveu:
> On Fri, Nov 03, 2017 at 02:47:05PM +0100, Niklas Cassel wrote:
>> Use the DMA-API to get the MSI address. This address will be written to
>> our PCI config space and to the register which determines which AXI
>> address the DWC IP w
_MSI_INTR0_STATUS + i * 12,
> 4, 1 << pos);
> - generic_handle_irq(irq);
> pos++;
> }
> }
>
It makes sense.
Acked-By: Joao Pinto
Hello Greg and Prabu,
Às 10:31 AM de 7/18/2017, Greg Kroah-Hartman (gre...@linuxfoundation.org)
escreveu:
> On Tue, Jul 18, 2017 at 09:15:58AM +, Prabu Thangamuthu wrote:
>> As per internal decision, Joao Pinto will be maintainer for DWC UFS driver.
>
> That's "
el_dbi(pci, offset + reg, val);
> }
>
> -int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index, int bar,
> +static int dw_pcie_prog_inbound_atu_unroll(struct dw_pcie *pci, int index,
> int bar,
> u64 cpu_addr, enum dw_pcie_as_type as_type)
> {
> int type;
> --
> 2.11.0
>
That indeed escaped in the refactoring :) Thanks!
Acked-by: Joao Pinto
gt; goto err;
>
> - return;
> + return 0;
> err:
> qcom_ep_reset_assert(pcie);
> phy_power_off(pcie->phy);
> err_deinit:
> pcie->ops->deinit(pcie);
> +
> + return ret;
> }
>
> static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
> diff --git a/drivers/pci/dwc/pcie-spear13xx.c
> b/drivers/pci/dwc/pcie-spear13xx.c
> index 80897291e0fb..52000bc34600 100644
> --- a/drivers/pci/dwc/pcie-spear13xx.c
> +++ b/drivers/pci/dwc/pcie-spear13xx.c
> @@ -177,13 +177,15 @@ static int spear13xx_pcie_link_up(struct dw_pcie *pci)
> return 0;
> }
>
> -static void spear13xx_pcie_host_init(struct pcie_port *pp)
> +static int spear13xx_pcie_host_init(struct pcie_port *pp)
> {
> struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
>
> spear13xx_pcie_establish_link(spear13xx_pcie);
> spear13xx_pcie_enable_interrupts(spear13xx_pcie);
> +
> + return 0;
> }
>
> static const struct dw_pcie_host_ops spear13xx_pcie_host_ops = {
>
A step in the right direction :). In the future we should add host init
validation in the specific SoC drivers, like Layerscape and Qcom have, to assure
that any problem is treated properly in the core driver.
Acked-by: Joao Pinto
if (val == PCIE_ATU_ENABLE)
> + if (val & PCIE_ATU_ENABLE)
> return;
>
> usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
>
Make sense, turn it more accurate. Thanks!
Acked-by: Joao Pinto
Hi to all,
Às 10:38 AM de 7/4/2017, Ard Biesheuvel escreveu:
> On 4 July 2017 at 09:19, Jisheng Zhang wrote:
>> On Tue, 4 Jul 2017 09:02:06 +0100 Ard Biesheuvel wrote:
>>
>>> On 4 July 2017 at 07:58, Jisheng Zhang wrote:
On Mon, 3 Jul 2017 08:27:04 -0500 wrote:
> [+cc Jingoo, Joao]
Hello to all,
Às 2:16 PM de 6/7/2017, Christoph Hellwig escreveu:
> On Tue, Jun 06, 2017 at 02:35:31PM +0300, Adrian Hunter wrote:
>> Add PCI id and variant ops for Intel CNL UFS host controller.
>
> Looks good:
>
> Reviewed-by: Christoph Hellwig
>
> It would be great if we could fold tc-dwc-g
Às 4:20 PM de 5/8/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
>
> On Monday 08 May 2017 08:43 PM, Joao Pinto wrote:
>>
>> Hi Peter,
>>
>> Às 4:02 PM de 5/8/2017, Peter Senna Tschudin escreveu:
>>> Hello Kishon,
>>>
>>> Our
Hi Peter,
Às 4:02 PM de 5/8/2017, Peter Senna Tschudin escreveu:
> Hello Kishon,
>
> Our iMX6 hardware (imx6q-b850v3.dts) is not booting with latest
> linux-next and I could bisect until:
>
> commit 442ec4c04d1235f8c664a74004dae54a7a574d18
> Author: Kishon Vijay Abraham I
> Date: Wed Feb 15
Às 12:56 PM de 5/8/2017, Andy Shevchenko escreveu:
> On Mon, May 8, 2017 at 2:40 PM, Joao Pinto wrote:
>> Às 12:34 PM de 5/8/2017, Andy Shevchenko escreveu:
>>> On Mon, May 8, 2017 at 1:42 PM, Joao Pinto wrote:
>>>> Às 11:12 AM de 5/8/2017, Andy Shevchenko escreveu
Às 12:34 PM de 5/8/2017, Andy Shevchenko escreveu:
> On Mon, May 8, 2017 at 1:42 PM, Joao Pinto wrote:
>> Às 11:12 AM de 5/8/2017, Andy Shevchenko escreveu:
>>> On Mon, May 8, 2017 at 12:54 PM, Joao Pinto wrote:
>>>> Às 10:36 AM de 5/8/2017, Andy Shevchenko escreve
Às 11:12 AM de 5/8/2017, Andy Shevchenko escreveu:
> On Mon, May 8, 2017 at 12:54 PM, Joao Pinto wrote:
>> Hi Andy and Jan,
>>
>> Às 10:36 AM de 5/8/2017, Andy Shevchenko escreveu:
>>> On Mon, May 8, 2017 at 9:56 AM, Jan Kiszka wrote:
>>>> On 2017-03-15
Hi Andy and Jan,
Às 10:36 AM de 5/8/2017, Andy Shevchenko escreveu:
> On Mon, May 8, 2017 at 9:56 AM, Jan Kiszka wrote:
>> On 2017-03-15 12:04, Joao Pinto wrote:
>>> This patch prepares DMA Operation Mode configuration for multiple queues.
>>> The work consisted on
rent = <&vic1>;
> - interrupts = <24 23>;
> - interrupt-names = "macirq", "eth_wake_irq";
> + interrupts = <24 23 22>;
> + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
> mac-address = []; /* Filled in by U-Boot */
> max-frame-size = <3800>;
> phy-mode = "gmii";
>
Acked-By: Joao Pinto
Regards!
Hi Niklas,
Às 7:33 PM de 4/10/2017, Niklas Cassel escreveu:
> From: Niklas Cassel
>
> Field FL/TPL in register TDES3 is not correctly set on GMAC4.
> TX appears to be functional on GMAC 4.10a even if this field is not set,
> however, to avoid relying on undefined behavior, set the length in TDE
Hello Peppe,
Às 2:07 PM de 4/3/2017, Giuseppe CAVALLARO escreveu:
> Hello Joao
>
> On 3/30/2017 6:42 PM, Joao Pinto wrote:
>> Às 5:35 PM de 3/30/2017, Niklas Cassel escreveu:
>>> On 03/30/2017 04:34 PM, Thierry Reding wrote:
>>>> On Thu, Mar 30, 2017 at 09
Às 5:57 PM de 3/31/2017, David Miller escreveu:
> From: Joao Pinto
> Date: Fri, 31 Mar 2017 11:43:38 +0100
>
>> @David: Could you please create a branch in your git tree for us to work on
>> it
>> until the multiple buffers get stable for everyone? This way the patche
The QoS IP does not accept AVB capabilities to default/queue 0, this way we
guarantee 75% bandwidth for AVB. This patch assures that only queues >= 1
gets CBS confgured. Additional info was also added to stmmac.txt.
Reported-by: Niklas Cassel
Signed-off-by: Joao Pinto
---
Documentat
Às 11:14 AM de 3/31/2017, Joao Pinto escreveu:
> Às 6:48 PM de 3/30/2017, David Miller escreveu:
>> From: Thierry Reding
>> Date: Thu, 30 Mar 2017 16:34:36 +0200
>>
>>> On Thu, Mar 30, 2017 at 09:45:36AM +0200, Corentin Labbe wrote:
>>>> On Tue, Mar
Às 6:48 PM de 3/30/2017, David Miller escreveu:
> From: Thierry Reding
> Date: Thu, 30 Mar 2017 16:34:36 +0200
>
>> On Thu, Mar 30, 2017 at 09:45:36AM +0200, Corentin Labbe wrote:
>>> On Tue, Mar 28, 2017 at 06:01:05PM -0700, David Miller wrote:
From: Arnd Bergmann
Date: Tue, 28 Mar 20
Às 5:35 PM de 3/30/2017, Niklas Cassel escreveu:
> On 03/30/2017 04:34 PM, Thierry Reding wrote:
>> On Thu, Mar 30, 2017 at 09:45:36AM +0200, Corentin Labbe wrote:
>>> On Tue, Mar 28, 2017 at 06:01:05PM -0700, David Miller wrote:
From: Arnd Bergmann
Date: Tue, 28 Mar 2017 11:48:21 +0200
Às 7:19 AM de 3/23/2017, Niklas Cassel escreveu:
> On 03/22/2017 04:47 PM, Joao Pinto wrote:
>> Hi Niklas,
>>
>> Às 2:43 PM de 3/21/2017, Niklas Cassel escreveu:
>>> From: Niklas Cassel
>>>
>>> Fix the following crash, seen in dwc/pcie-artpec6
Às 10:56 AM de 3/23/2017, Joao Pinto escreveu:
> Às 10:51 AM de 3/23/2017, Giuseppe CAVALLARO escreveu:
>> On 3/23/2017 11:48 AM, Giuseppe CAVALLARO wrote:
>>> Hello
>>>
>>> On 3/23/2017 11:20 AM, Corentin Labbe wrote:
>>>>> I have a 4.21 Q
Às 10:51 AM de 3/23/2017, Giuseppe CAVALLARO escreveu:
> On 3/23/2017 11:48 AM, Giuseppe CAVALLARO wrote:
>> Hello
>>
>> On 3/23/2017 11:20 AM, Corentin Labbe wrote:
I have a 4.21 QoS Core with 4 RX + 4 TX and detected no regression.
>Could you please share the iperf cmds you are using in
Hi Peppe,
Às 10:48 AM de 3/23/2017, Giuseppe CAVALLARO escreveu:
> Hello
>
> On 3/23/2017 11:20 AM, Corentin Labbe wrote:
>>> I have a 4.21 QoS Core with 4 RX + 4 TX and detected no regression.
>>> >Could you please share the iperf cmds you are using in order for me to
>>> reproduce
>>> >in my s
Às 10:20 AM de 3/23/2017, Corentin Labbe escreveu:
> On Thu, Mar 23, 2017 at 10:12:18AM +0000, Joao Pinto wrote:
>>
>> Hi Corentin,
>>
>> Às 10:08 AM de 3/23/2017, Corentin Labbe escreveu:
>>> Hello
>>>
>>> Using next-20170323 produce a huge
Hi Corentin,
Às 10:08 AM de 3/23/2017, Corentin Labbe escreveu:
> Hello
>
> Using next-20170323 produce a huge performance regression on my sunxi boards.
> On dwmac-sun8i, iperf goes from 94mbs/s to 37 when sending.
>
> On cubieboard2(dwmac-sunxi), iperf made the kernel flood with
> "ndesc_get
Hi Niklas,
Às 2:43 PM de 3/21/2017, Niklas Cassel escreveu:
> From: Niklas Cassel
>
> Fix the following crash, seen in dwc/pcie-artpec6.
>
> Unable to handle kernel NULL pointer dereference at virtual address 0004
> pgd = c0204000
> [0004] *pgd=
> Internal error: Oops:
Às 4:50 PM de 3/21/2017, Joao Pinto escreveu:
> Às 4:42 PM de 3/21/2017, Thierry Reding escreveu:
>> On Tue, Mar 21, 2017 at 03:23:00PM +0000, Joao Pinto wrote:
>>> Às 3:12 PM de 3/21/2017, Thierry Reding escreveu:
>>>> From: Thierry Reding
>>>>
>&g
Às 4:42 PM de 3/21/2017, Thierry Reding escreveu:
> On Tue, Mar 21, 2017 at 03:23:00PM +0000, Joao Pinto wrote:
>> Às 3:12 PM de 3/21/2017, Thierry Reding escreveu:
>>> From: Thierry Reding
>>>
>>> Prior to the recent multi-queue changes the driver would con
Às 3:12 PM de 3/21/2017, Thierry Reding escreveu:
> From: Thierry Reding
>
> Prior to the recent multi-queue changes the driver would configure the
> queues to use the AVB mode, but the mode then got switched to DCB. The
> hardware still works fine in DCB mode, but my testing capabilities are
> l
ies, we fall back
> + * to one RX and TX queues each.
> + */
> + plat->rx_queues_to_use = 1;
> + plat->tx_queues_to_use = 1;
> +
> rx_node = of_parse_phandle(pdev->dev.of_node, "snps,mtl-rx-config", 0);
> if (!rx_node)
> return;
>
Acked-By: Joao Pinto
my attention a setup that has 1 RX queue and 2 TX queues, which
enables multiple queues mechanism inside the core (even with 1 RX) and so RX
needs to be enabled. Because of that I agree with this patch.
Acked-By: Joao Pinto
Hi Peppe,
Às 2:39 PM de 3/21/2017, Giuseppe CAVALLARO escreveu:
> Hello Corentin
>
> yes, bisect process is really good approach to me. Pls give us more details.
> Recently the multi DMA channel logic has been added so it could be that
> something is needed to allow your platform to manage the ne
Às 5:44 PM de 3/20/2017, Niklas Cassel escreveu:
> On 03/20/2017 06:42 PM, Joao Pinto wrote:
>> Às 5:29 PM de 3/20/2017, Niklas Cassel escreveu:
>>> From: Niklas Cassel
>>>
>>> It is usually possible to do
>>> ethtool -s autoneg on
>>> so that
Às 5:29 PM de 3/20/2017, Niklas Cassel escreveu:
> From: Niklas Cassel
>
> It is usually possible to do
> ethtool -s autoneg on
> so that you trigger an autoneg before calling
> ip link set dev eth0 up
>
> However, stmmac returns -EBUSY if !netif_running.
> The only reason for this appears to be
Às 11:36 AM de 3/10/2017, Kishon Vijay Abraham I escreveu:
> Hi,
>
> On Thursday 09 March 2017 08:35 PM, Niklas Cassel wrote:
>>
>>
>> On 03/09/2017 03:48 PM, Niklas Cassel wrote:
>>> On 03/09/2017 07:39 AM, Kishon Vijay Abraham I wrote:
dwc has 2 dbi address space labeled dbics and dbics2. T
Às 7:41 PM de 3/9/2017, Thierry Reding escreveu:
> On Thu, Mar 02, 2017 at 03:09:11PM +0000, Joao Pinto wrote:
>> Hi Thierry,
>>
>> Às 5:24 PM de 2/23/2017, Thierry Reding escreveu:
>>> From: Thierry Reding
>>>
>>> New version of this core encode th
-PCIE_ATU_UNR_REGION_CTRL2);
> - else
> - val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4);
> -
> + val = dw_pcie_read_dbi(pci, base, PCIE_ATU_CR2, 0x4);
> if (val == PCIE_ATU_ENABLE)
> return;
>
> usleep_range(LINK_WAIT_IATU_MIN, LINK_WAIT_IATU_MAX);
> }
> - dev_err(pci->dev, "iATU is not being enabled\n");
> + dev_err(pci->dev, "outbound iATU is not being enabled\n");
> }
>
> int dw_pcie_wait_for_link(struct dw_pcie *pci)
>
Acked-By: Joao Pinto
Hi Christoph,
Às 7:14 PM de 3/8/2017, Christoph Hellwig escreveu:
> On Wed, Mar 08, 2017 at 03:32:03PM +0000, Joao Pinto wrote:
>> #define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
>> ((0x3 <&l
Às 1:31 PM de 3/8/2017, Kishon Vijay Abraham I escreveu:
> Hi,
>
> On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
>> Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>>> Hi,
>>>
>>> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote
Às 3:32 PM de 3/8/2017, Joao Pinto escreveu:
> Às 1:31 PM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>> Hi,
>>
>> On Wednesday 08 March 2017 05:07 PM, Joao Pinto wrote:
>>> Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
>>>> Hi,
>>&
Às 11:35 AM de 3/8/2017, Kishon Vijay Abraham I escreveu:
> Hi,
>
> On Wednesday 08 March 2017 05:02 PM, Joao Pinto wrote:
>>
>> Hi Kishon,
>>
>>>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>>>> PCIE_GET_ATU_OUTB_UNR_REG_
Hi Kishon,
>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>
> Yes of course, I will send you the definition soon.
As promissed here is the definition for Inbound:
+/* register address builder */
+#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region
cessors must
> be used to access data of size 2. This is in preparation for
> adding endpoint mode support to designware driver.
>
> Cc: Jingoo Han
> Cc: Richard Zhu
> Cc: Lucas Stach
> Cc: Murali Karicheri
> Cc: Thomas Petazzoni
> Cc: Niklas Cassel
> Cc: Jesper
Hi Kishon,
Às 5:18 AM de 3/7/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
>
> On Friday 17 February 2017 10:50 PM, Joao Pinto wrote:
>> Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>>> Add endpoint mode support to designware driver. This uses the
>
. This is in preparation for adding EP mode support
> to dwc driver.
>
> Cc: Jingoo Han
> Cc: Richard Zhu
> Cc: Lucas Stach
> Cc: Murali Karicheri
> Cc: Thomas Petazzoni
> Cc: Niklas Cassel
> Cc: Jesper Nilsson
> Cc: Joao Pinto
> Cc: Zhou Wang
> Cc: Gabriele
ixup,
> +};
> +
> static int artpec6_pcie_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -252,6 +256,7 @@ static int artpec6_pcie_probe(struct platform_device
> *pdev)
> return -ENOMEM;
>
> pci->dev = dev;
> + pci->ops = &dw_pcie_ops;
>
> artpec6_pcie->pci = pci;
>
>
Simpler, no doubt.
Acked-By: Joao Pinto
gt; @@ -329,6 +329,7 @@ static int __init dra7xx_add_pcie_port(struct dra7xx_pcie
> *dra7xx,
> }
>
> static const struct dw_pcie_ops dw_pcie_ops = {
> + .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
> .link_up = dra7xx_pcie_link_up,
> };
>
>
Simpler, no doubt.
Acked-By: Joao Pinto
{
> };
>
> struct dw_pcie_ops {
> + u64 (*cpu_addr_fixup)(u64 cpu_addr);
> u32 (*readl_dbi)(struct dw_pcie *pcie, u32 reg);
> void(*writel_dbi)(struct dw_pcie *pcie, u32 reg, u32 val);
> int (*link_up)(struct dw_pcie *pcie);
>
Looks good.
Acked-by: Joao Pinto
Às 5:24 PM de 2/23/2017, Thierry Reding escreveu:
> From: Thierry Reding
>
> The NVIDIA Tegra186 SoC contains an instance of the Synopsys DWC
> ethernet QOS IP core. The binding that it uses is slightly different
> from existing ones because of the integration (clocks, resets, ...).
>
> Signed-o
platform_get_drvdata(pdev);
> + struct stmmac_priv *priv = netdev_priv(ndev);
> + const struct dwc_eth_dwmac_data *data;
> + int err;
> +
> + data = of_device_get_match_data(&pdev->dev);
> +
> + err = stmmac_dvr_remove(&pdev->dev);
> + if (err < 0)
> + dev_err(&pdev->dev, "failed to remove platform: %d\n", err);
> +
> + err = data->remove(pdev);
> + if (err < 0)
> + dev_err(&pdev->dev, "failed to remove subdriver: %d\n", err);
> +
> + stmmac_remove_config_dt(pdev, priv->plat);
> +
> + return err;
> }
>
> static const struct of_device_id dwc_eth_dwmac_match[] = {
> - { .compatible = "snps,dwc-qos-ethernet-4.10", },
> + { .compatible = "snps,dwc-qos-ethernet-4.10", .data = &dwc_qos_data },
> { }
> };
> MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match);
>
Reviewed-By: Joao Pinto
Às 5:24 PM de 2/23/2017, Thierry Reding escreveu:
> From: Thierry Reding
>
> Program the receive queue size based on the RX FIFO size and enable
> hardware flow control for large FIFOs.
>
> Signed-off-by: Thierry Reding
> ---
> drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 12 +++
> d
Hi Thierry,
Às 5:24 PM de 2/23/2017, Thierry Reding escreveu:
> From: Thierry Reding
>
> New version of this core encode the FIFO sizes in one of the feature
> registers. Use these sizes as default, but still allow device tree to
> override them for backwards compatibility.
>
> Signed-off-by: T
*pdev,
> const char **mac)
> plat->clk_ptp_ref = NULL;
> dev_warn(&pdev->dev, "PTP uses main clock\n");
> } else {
> - clk_prepare_enable(plat->clk_ptp_ref);
> plat->clk_ptp_rate = clk_get_rate(plat->clk_ptp_ref);
> dev_dbg(&pdev->dev, "PTP rate %d\n", plat->clk_ptp_rate);
> }
>
Reviewed-By: Joao Pinto
Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Add endpoint mode support to designware driver. This uses the
> EP Core layer introduced recently to add endpoint mode support.
> *Any* function driver can now use this designware device
> in order to achieve the EP functionality.
>
> Sig
| vendorid
> +| deviceid
> +| revid
> +| progif_code
> +| subclass_code
> +| baseclass_code
> +| cache_line_size
> +| subsys_vendor_id
> +| subsys_id
> +| interrupt_pin
> +
> +The following entry identifies the function driver that is bound to the
> +function device
> + | function
> +
> +[1] -> Documentation/PCI/endpoint/pci-endpoint.txt
> +[4] -> Documentation/PCI/endpoint/function/binding/
>
Good content.
Acked-By: Joao Pinto
Às 11:37 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
>
> On Friday 17 February 2017 04:56 PM, Joao Pinto wrote:
>>
>> Hi Kishon,
>>
>> Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>>> Introduce a new EP core layer in order
tion to the host.
> +
> +2.2.2 Other APIs
> +There are other APIs provided by the EPF library. These are used to notify
> +the function driver when the EPF device is bound to the EPC device.
> +pci-ep-cfs.c can be used as reference for using these APIs.
> +
> +*) pci_epf_create()
> +
> + Create a new PCI EPF device by passing the name of the PCI EPF device.
> + This name will be used to bind the the EPF device to a EPF driver.
> +
> +*) pci_epf_destroy()
> +
> + Destroy the created PCI EPF device.
> +
> +*) pci_epf_bind()
> +
> + pci_epf_bind() should be invoked when the EPF device has been bound to
> + a EPC device.
> +
> +*) pci_epf_unbind()
> +
> + pci_epf_unbind() should be invoked when the binding between EPC device
> + and EPF device is lost.
>
Good initial reference guide.
Acked-By: Joao Pinto
Hi Kishon,
Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Introduce a new EP core layer in order to support endpoint functions
> in linux kernel. This comprises of EPC library
> (Endpoint Controller Library) and EPF library (Endpoint
> Function Library). EPC library implements functi
Às 10:33 AM de 1/31/2017, Giuseppe CAVALLARO escreveu:
> On 1/31/2017 11:23 AM, Joao Pinto wrote:
>>
>> Hi Peppe,
>>
>> Às 10:00 AM de 1/31/2017, Giuseppe CAVALLARO escreveu:
>>> Hello Corentin
>>>
>>> On 1/31/2017 10:11 AM, Corentin Labbe
Hi Peppe,
Às 10:00 AM de 1/31/2017, Giuseppe CAVALLARO escreveu:
> Hello Corentin
>
> On 1/31/2017 10:11 AM, Corentin Labbe wrote:
>> Hello
>>
>> I am currently working on dwmac-sun8i glue driver for Allwinner H3/A83T/A64.
>> This serie is the result of all minor problem found in the stmmac driv
Às 4:34 PM de 1/20/2017, David Miller escreveu:
> From: Joao Pinto
> Date: Fri, 20 Jan 2017 16:30:41 +
>
>> Charade of renames? It is a bit strong, don't you agree?
>
> Not at all.
To avoid this kind of "charade" comments, I sent an RFC, not an
Às 4:20 PM de 1/20/2017, David Miller escreveu:
> From: Joao Pinto
> Date: Fri, 20 Jan 2017 12:27:33 +
>
>> For historical reasons the Designware eQOS IP Core started in version 4.x,
>> instead of starting in 1.x. This caused some misunderstanding, which resulted
>
Sorry, please ignore, wrong patch file.
Joao Pinto
Às 6:01 AM de 1/19/2017, Rayagond Kokatanur escreveu:
> On Thu, Dec 29, 2016 at 10:40 PM, Joao Pinto wrote:
>> This patch adds Energy Efficiency Ethernet to GMAC4.
>>
>> Signed-off-by: Joao Pinto
>> ---
>> dr
Hi Rayagond,
Às 6:01 AM de 1/19/2017, Rayagond Kokatanur escreveu:
> On Thu, Dec 29, 2016 at 10:40 PM, Joao Pinto wrote:
>> This patch adds Energy Efficiency Ethernet to GMAC4.
>>
>> Signed-off-by: Joao Pinto
>> ---
>> drivers/net/ethernet/stmicro/stmmac/dwm
Hello,
Às 10:53 PM de 1/18/2017, Bjorn Helgaas escreveu:
> I want to improve PCI bug tracking. It feels like our bugs don't get
> the attention they need, and I'm soliciting ideas for how to improve
> this.
>
> Current situation:
>
> - People often report bugs via email to linux-pci. I thin
Hello,
Às 11:38 AM de 1/17/2017, Lukasz Majewski escreveu:
> Hi Joao,
>
> Thank you for your reply.
>
>> Às 10:43 AM de 1/17/2017, Joao Pinto escreveu:
>>>
>>> Hi Lukasz,
>>>
>>> Às 9:44 PM de 1/16/2017, Lukasz Majewski escreveu:
>>&
Às 10:43 AM de 1/17/2017, Joao Pinto escreveu:
>
> Hi Lukasz,
>
> Às 9:44 PM de 1/16/2017, Lukasz Majewski escreveu:
>> Hi Joao,
>>
>>>
>>> Hi,
>>>
>>> Às 10:13 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
>>>> +
Hi Lukasz,
Às 9:44 PM de 1/16/2017, Lukasz Majewski escreveu:
> Hi Joao,
>
>>
>> Hi,
>>
>> Às 10:13 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
>>> + Joao, Jingoo
>>>
>>> Hi,
>>>
>>> On Monday 16 January 2017 03:01 PM, Lukasz Majewski wrote:
Hi Kishon,
> Hi Łukasz,
>
Hi,
Às 5:35 AM de 1/17/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
>
> On Monday 16 January 2017 10:31 PM, Joao Pinto wrote:
>>
>> Hi,
>>
>> Às 10:13 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
>>> + Joao, Jingoo
>>>
>>
Hi,
Às 10:13 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
> + Joao, Jingoo
>
> Hi,
>
> On Monday 16 January 2017 03:01 PM, Lukasz Majewski wrote:
>> Hi Kishon,
>>
>>> Hi Łukasz,
>>>
>>> On Monday 16 January 2017 12:19 PM, Lukasz Majewski wrote:
Hi Kishon,
> Hi,
>
> On
Hi,
Às 10:13 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
> + Joao, Jingoo
>
> Hi,
>
> On Monday 16 January 2017 03:01 PM, Lukasz Majewski wrote:
>> Hi Kishon,
>>
>>> Hi Łukasz,
>>>
>>> On Monday 16 January 2017 12:19 PM, Lukasz Majewski wrote:
Hi Kishon,
> Hi,
>
> On
Às 11:30 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
>
> On Monday 16 January 2017 03:57 PM, Joao Pinto wrote:
>>
>> Hi,
>>
>> Às 5:21 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
>>> Hi Joao,
>>>
>>> On Friday 13
Hi,
Às 5:21 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
>
> On Friday 13 January 2017 10:19 PM, Joao Pinto wrote:
>> Às 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>>> Split pcie-designware.c into pcie-designware-host.c that contains
>&g
Hi,
Às 5:19 AM de 1/16/2017, Kishon Vijay Abraham I escreveu:
> Hi,
>
> On Friday 13 January 2017 10:43 PM, Joao Pinto wrote:
>> Hi,
>>
>> Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
>>> *num-lanes* dt property is parsed in dw_pcie_host_init.
Hi Kishon,
Às 10:26 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
> Now that pci designware host has a separate file, create a new
> config symbol to select the host only driver. This is in preparation
> to enable endpoint support to designware driver.
>
> Signed-off-by: Kishon Vijay Abraham
Hi!
Às 10:25 AM de 1/12/2017, Kishon Vijay Abraham I escreveu:
> No functional change. Get device pointer at the beginning of
> dw_pcie_host_init instead of getting it all over dw_pcie_host_init.
> This is in preparation for splitting struct pcie_port into host and
> core structures (Once split p
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