> -Original Message-
> From: Schrempf Frieder
> Sent: Monday, October 7, 2019 2:23 AM
> To: Han Xu ; Mark Brown
> Cc: Schrempf Frieder ; sta...@vger.kernel.org;
> linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: [EXT] [PATCH] spi: spi-fsl-qs
> -Original Message-
> From: Kuldeep Singh
> Sent: Tuesday, October 1, 2019 3:59 AM
> To: Han Xu ; broo...@kernel.org; linux-...@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Cc: Kuldeep Singh ; Suresh Gupta
>
> Subject: [PATCH] spi: spi-fsl-qspi: I
> -Original Message-
> From: Mark Brown
> Sent: Thursday, July 11, 2019 7:41 AM
> To: Han Xu
> Cc: Ashish Kumar ; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; dl-linux-imx
> Subject: Re: [EXT] Re: [PATCH 1/3] spi: spi-nxp-fspi: dynamically allo
> -Original Message-
> From: Mark Brown
> Sent: Wednesday, July 10, 2019 10:16 AM
> To: Han Xu
> Cc: Ashish Kumar ; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; dl-linux-imx
> Subject: [EXT] Re: [PATCH 1/3] spi: spi-nxp-fspi: dynamically alloc
From: Han Xu
i.MX platforms reserved 256M memory area for FSPI/QSPI AHB memory, it
may failed to alloc all of them at once on some platforms. These patches
allow the controller alloc AHB as needed.
i.MX7D RX FIFO should be 128B rather than 512B.
Han Xu (3):
spi: spi-nxp-fspi: dynamically
From: Han Xu
dynamically alloc AHB memory for QSPI controller.
Signed-off-by: Han Xu
---
drivers/spi/spi-fsl-qspi.c | 58 +++---
1 file changed, 42 insertions(+), 16 deletions(-)
diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
index
From: Han Xu
dynamically alloc AHB memory for FSPI controller
Signed-off-by: Han Xu
---
drivers/spi/spi-nxp-fspi.c | 39 ++
1 file changed, 31 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index
From: Han Xu
The RX FIFO should be 128 byte rather than 512 byte. It's a typo on
reference manual.
Signed-off-by: Han Xu
---
drivers/spi/spi-fsl-qspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c
> -Original Message-
> From: tudor.amba...@microchip.com
> Sent: Thursday, June 6, 2019 12:46 AM
> To: Han Xu ; cyrille.pitc...@wedev4u.fr;
> marek.va...@gmail.com
> Cc: boris.brezil...@free-electrons.com; f.faine...@gmail.com;
> kdasu.k...@gmail.com; rich...
In the new implemented spi_nor_resume function, the spi_nor_init()
should be braced by prep/unprep functions._
Signed-off-by: Han Xu
---
drivers/mtd/spi-nor/spi-nor.c | 8
include/linux/mtd/spi-nor.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c
> -Original Message-
> From: Martin Kepplinger
> Sent: Tuesday, February 5, 2019 9:53 AM
> To: Han Xu ; bbrezil...@kernel.org;
> miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; marek.va...@gmail.com; linux-
> m...@lis
> -Original Message-
> From: Schrempf Frieder
> Sent: Tuesday, December 4, 2018 8:15 AM
> To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; linux-
> s...@vger.kernel.org; Marek Vasut ; Mark Brown
> ; Han Xu
> Cc: dw...@infradead.org; computersforpe
..@nod.at; miquel.ray...@bootlin.com; broo...@kernel.org; David
> Wolfe ; Fabio Estevam ;
> Prabhakar Kushwaha ; Yogesh Narayan
> Gaur ; Han Xu ;
> shawn...@kernel.org; Schrempf Frieder ;
> linux-kernel@vger.kernel.org
> Subject: [PATCH v7 6/9] mtd: fsl-quadspi: Remove the driver
> -Original Message-
> From: Schrempf Frieder
> Sent: Thursday, November 29, 2018 11:36 AM
> To: Han Xu ; Yogesh Narayan Gaur
> ; linux-...@lists.infradead.org;
> boris.brezil...@bootlin.com; linux-...@vger.kernel.org; Marek Vasut
> ; Mark Brown
>
> -Original Message-
> From: Schrempf Frieder
> Sent: Thursday, November 29, 2018 5:54 AM
> To: Yogesh Narayan Gaur ; linux-
> m...@lists.infradead.org; boris.brezil...@bootlin.com; linux-
> s...@vger.kernel.org; Marek Vasut ; Mark Brown
> ; Han Xu
>
supports 512 and 1024.
>
> The device tree may optionally contain sub-nodes describing partitions of
> the
> address space. See partition.txt for more detail.
>
Acked-by: Han Xu
> + || legacy_set_geometry(this)) {
> + if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0))
> + return -EINVAL;
> +
> + return set_geometry_by_ecc_info(this, chip->ecc_strength_ds,
> + chip->ecc_step_ds);
> + }
>
> return 0;
> }
>
Acked-by: Han Xu
On 02/06/2018 11:40 AM, Stefan Agner wrote:
> Add support for specified ECC strength/size using device tree
> properties nand-ecc-strength/nand-ecc-step-size.
>
> Signed-off-by: Stefan Agner
> ---
> .../devicetree/bindings/mtd/gpmi-nand.txt | 5
> drivers/mtd/nand/gpmi-nand/gpm
From: Gustavo A. R. Silva
Sent: Friday, November 3, 2017 3:31 PM
To: Han Xu; Boris Brezillon; Richard Weinberger; David Woodhouse; Brian Norris;
Marek Vasut; Cyrille Pitchen
Cc: linux-...@lists.infradead.org; linux-kernel@vger.kernel.org; Gustavo A. R
On 07/13/2017 03:15 PM, Boris Brezillon wrote:
> Hi Miquel,
>
> Le Thu, 13 Jul 2017 21:20:30 +0200,
> Miquel Raynal a écrit :
>
>> GPMI NFC driver fails to apply timing mode if the ->onfi_get_features()
>> does not return the mode that was previously applied.
>>
>> We can assume that a nand chip
On 06/08/2017 05:34 PM, Stefan Agner wrote:
> The Colibri iMX7 modules come with 512MB on-module SLC NAND flash
> populated. Make use of it by enabling the GPMI controller.
>
> Signed-off-by: Stefan Agner
> Tested-by: Fabio Estevam
Acked-by: Han Xu
> ---
> a
On 06/08/2017 05:34 PM, Stefan Agner wrote:
> Add i.MX 7 APBH DMA and GPMI NAND modules.
>
> Signed-off-by: Stefan Agner
> Tested-by: Fabio Estevam
Acked-by: Han Xu
> ---
> arch/arm/boot/dts/imx7s.dtsi | 31 +++
> 1 file changed, 31 inserti
H-Bridge-DMA.
>
> Add new clocks which represent the clock after the gate, and use a
> shared clock gate to correctly model the hardware.
>
> Signed-off-by: Stefan Agner
> Tested-by: Fabio Estevam
Acked-by: Han Xu
> ---
> drivers/clk/imx/clk-imx7d.c | 6 --
On 06/06/2017 01:30 AM, Stefan Agner wrote:
> Add i.MX 7 APBH DMA and GPMI NAND modules.
>
> Signed-off-by: Stefan Agner
> ---
> arch/arm/boot/dts/imx7s.dtsi | 32
> 1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot
On 06/01/2017 08:48 PM, Stefan Agner wrote:
> Hi Han,
>
> On 2017-06-01 14:14, Han Xu wrote:
>> On 06/01/2017 02:20 PM, Stefan Agner wrote:
>>> This are the missing device tree parts to add NAND support for i.MX 7.
>>> See previous patchset:
>>> https
On 06/01/2017 02:20 PM, Stefan Agner wrote:
> This are the missing device tree parts to add NAND support for i.MX 7.
> See previous patchset:
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flkml.org%2Flkml%2F2017%2F4%2F21%2F832&data=01%7C01%7Chan.xu%40nxp.com%7C3b9081a68c9447
On 05/04/2017 04:50 PM, Stefan Agner wrote:
> On 2017-05-04 12:13, Han Xu wrote:
>> On 04/21/2017 08:23 PM, Stefan Agner wrote:
>>> Add i.MX 7 GPMI NAND module.
>>>
>>> Signed-off-by: Stefan Agner
>>> ---
>>>arch/arm/boot/dts/imx7s.d
On 04/21/2017 08:23 PM, Stefan Agner wrote:
> Add i.MX 7 GPMI NAND module.
>
> Signed-off-by: Stefan Agner
> ---
> arch/arm/boot/dts/imx7s.dtsi | 31 +++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
ecc_strength = 62,
>>> .max_chain_delay = 12,
>>> .clks = gpmi_clks_for_mx7d,
>>> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>>> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>>> index 2e584e18d980..f2cc13abc896 100644
>>> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>>> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>>> @@ -123,7 +123,8 @@ enum gpmi_type {
>>> IS_MX23,
>>> IS_MX28,
>>> IS_MX6Q,
>>> - IS_MX6SX
>>> + IS_MX6SX,
>>> + IS_MX7D,
>>> };
>>>
>>> struct gpmi_devdata {
>>> @@ -307,6 +308,8 @@ void gpmi_copy_bits(u8 *dst, size_t dst_bit_off,
>>> #define GPMI_IS_MX28(x)((x)->devdata->type == IS_MX28)
>>> #define GPMI_IS_MX6Q(x)((x)->devdata->type == IS_MX6Q)
>>> #define GPMI_IS_MX6SX(x) ((x)->devdata->type == IS_MX6SX)
>>> +#define GPMI_IS_MX7D(x)((x)->devdata->type == IS_MX7D)
>>>
>>> -#define GPMI_IS_MX6(x) (GPMI_IS_MX6Q(x) || GPMI_IS_MX6SX(x))
>>> +#define GPMI_IS_MX6(x) (GPMI_IS_MX6Q(x) || GPMI_IS_MX6SX(x) ||
>>> \
>>> +GPMI_IS_MX7D(x))
>>> #endif
>>>
>>> --
>>> Stefan
>>>
>
> __
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
--
Sincerely,
Han XU
rn ret;
>> > > > > + if (cr3v & CR3V_4KB_ERASE_UNABLE)
>> > > > > + return 0;
>> > > > > + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
>> > > > > + if (ret)
>> > > > > +
On Thu, Sep 15, 2016 at 06:50:55AM +, Krzeminski, Marcin (Nokia -
PL/Wroclaw) wrote:
> Hello,
>
> > -Original Message-
> > From: linux-mtd [mailto:linux-mtd-boun...@lists.infradead.org] On Behalf
> > Of Han Xu
> > Sent: Wednesday, September 14, 2016 9:49
- WR EVCR typo in header file
- RD EVCR command in lut
This patch depends on Yunhui's patch set
https://patchwork.ozlabs.org/patch/660356/
Signed-off-by: Han Xu
---
drivers/mtd/spi-nor/fsl-quadspi.c | 111 +++---
include/linux/mtd/spi-nor.h | 6 +
t; + else
> + mem_base = q->memmap_phy;
> +
> + qspi_writel(q, nor_size + mem_base, base + QUADSPI_SFA1AD);
> + qspi_writel(q, nor_size * 2 + mem_base, base + QUADSPI_SFA2AD);
> + qspi_writel(q, nor_size * 3 + mem_base, base + QUADSPI_SFB1AD);
*/
> + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
> + ((q->devtype_data->ahb_buf_size / 8)
> + << QUADSPI_BUF3CR_ADATSZ_SHIFT),
> + base + QUADSPI_BUF3CR);
> + }
>
> /* We only use the buffer3 */
> qspi_writel(q, 0, base + QUADSPI_BUF0IND);
> --
> 2.1.0.27.g96db324
>
>
Acked-by: Han xu
> __
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
--
Sincerely,
Han XU
struct spi_nor *nor, const char
> *name, enum read_mode mode)
> spi_nor_wait_till_ready(nor);
> }
>
> + if (EXT_JEDEC(info) == SPINOR_S25FS_FAMILY_EXT_JEDEC) {
> + ret = spansion_s25fs_disable_4kb_erase(nor);
> + if (
WRAR;
> case SPINOR_OP_WREN:
> @@ -550,6 +573,8 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
> return SEQID_EN4B;
> case SPINOR_OP_BRWR:
> return SEQID_BRWR;
> + case SPINOR_OP_WD_EVCR:
> + return SEQID_WD_EVCR;
> default:
> if (cmd == q->nor[0].erase_opcode)
> return SEQID_SE;
> --
> 2.1.0.27.g96db324
>
>
Acked-by: Han xu
> __
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
--
Sincerely,
Han XU
ot;, .data = (void *)&imx7d_data, },
> { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
> { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
> + { .compatible = "fsl,ls2080a-qspi", .data = (void *)&ls2080a_data, },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
> --
> 2.1.0.27.g96db324
>
>
Acked-by: Han xu
> __
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
--
Sincerely,
Han XU
gt; /* Used for Spansion flashes only. */
> #define SPINOR_OP_BRWR 0x17/* Bank register write */
>
> +/* Used for Spansion S25FS-S family flash only. */
> +#define SPINOR_OP_SPANSION_RDAR0x65/* Read any device register */
> +#define SPINOR_OP_SP
_WREN * 4;
> @@ -468,6 +478,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
> {
> switch (cmd) {
> case SPINOR_OP_READ_1_1_4:
> + case SPINOR_OP_READ_FAST:
> return SEQID_READ;
> case SPINOR_OP_WREN:
>
468,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
> {
> switch (cmd) {
> case SPINOR_OP_READ_1_1_4:
> - return SEQID_QUAD_READ;
> + return SEQID_READ;
> case SPINOR_OP_WREN:
> return SEQID_WREN;
>
*/
> lut_base = SEQID_SE * 4;
>
> - cmd = q->nor[0].erase_opcode;
> - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
> -
> - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
> + qspi_writel(q, LUT0(CMD, PAD1, nor-
tic const struct fsl_qspi_devtype_data imx6ul_data = {
> .devtype = FSL_QUADSPI_IMX6UL,
> .rxfifo = 128,
> .txfifo = 512,
> --
> 2.7.3
>
Acked-by: Han Xu
>
> __
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
spi_nor_wait_till_ready(nor);
> }
>
> + if (EXT_ID(info) == SPINOR_S25FS_FAMILY_ID) {
> + ret = spansion_s25fs_disable_4kb_erase(nor);
> + if (ret)
> + return ret;
> + }
> +
> if (!mtd->name)
> mtd->name = dev_name(dev);
> mtd->priv = nor;
> --
> 2.1.0.27.g96db324
>
>
> __
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
--
Sincerely,
Han XU
comment, but since you're pinging
> again...
>
> Your patchset doesn't build on the latest. You need to refresh.
>
> Also, has Han Xu reviewed this?
I sent comments for v1 in [PATCH 6/9] mtd: spi-nor: Support R/W for
S25FS-S family flash,
but nothing changed in v2. Brian, could y
On Tue, Jun 28, 2016 at 3:55 PM, Rob Herring wrote:
> On Fri, Jun 24, 2016 at 04:40:07PM -0500, Han Xu wrote:
>> add the clocks and clock-names in DT property, gpmi-io clock is
>> mandatory for all platforms, but some platforms, such as i.MX6Q may
>> need more extra clocks
support GPMI NAND on i.MX7D
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi-nand/bch-regs.h | 14 +++---
drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 10 ++
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 30 --
drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 7
listed all supported chips in DT.
Signed-off-by: Han Xu
---
Documentation/devicetree/bindings/mtd/gpmi-nand.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
index
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to ecc_strength and if bitflip detected, GPMI driver
will correct the data to all 0xFF.
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi
support GPMI NAND on i.MX6QP
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 9 +
drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 5 -
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
b/drivers/mtd/nand/gpmi-nand/gpmi
support GPMI NAND on i.MX6UL
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 9 +
drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 5 -
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
b/drivers/mtd/nand/gpmi-nand/gpmi
add the clocks and clock-names in DT property, gpmi-io clock is
mandatory for all platforms, but some platforms, such as i.MX6Q may
need more extra clocks for submodules. More details please refer to the
SoC reference manual.
Signed-off-by: Han Xu
---
Documentation/devicetree/bindings/mtd/gpmi
lit bitflip and i.MX6QP code
v2 ---> v3:
calculate erased chunks and fix bitflip after loop
add more details for i.MX7 clock name
fix the patch name for documentation
Han Xu (6):
mtd: nand: gpmi: add GPMI NAND support for i.MX7D
Documentation: dt: mtd: gpmi: document the clocks and clock-na
On Tue, Jun 14, 2016 at 2:14 PM, Boris Brezillon
wrote:
> On Fri, 10 Jun 2016 12:01:32 -0500
> Han Xu wrote:
>
>> i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
>> bitflip number for erased NAND page. So for these two platform, set the
>> erase th
support GPMI NAND on i.MX6UL
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 9 +
drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 5 -
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
b/drivers/mtd/nand/gpmi-nand/gpmi
listed all supported chips in DT.
Signed-off-by: Han Xu
---
Documentation/devicetree/bindings/mtd/gpmi-nand.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
index
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to ecc_strength and if bitflip detected, GPMI driver
will correct the data to all 0xFF.
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi
add the clocks and clock-names in DT property, gpmi-io clock is
mandatory for all platforms, but some platforms, such as i.MX6Q may
need more extra clocks for submodules. More details please refer to the
SoC reference manual.
Signed-off-by: Han Xu
---
Documentation/devicetree/bindings/mtd/gpmi
support GPMI NAND on i.MX7D
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi-nand/bch-regs.h | 14 +++---
drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 10 ++
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 30 --
drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 7
lit bitflip and i.MX6QP code
Han Xu (6):
mtd: nand: gpmi: add GPMI NAND support for i.MX7D
mtd: nand: gpmi: document the clocks and clock-names in DT property
mtd: nand: gpmi: add GPMI NAND support for i.MX6QP
mtd: nand: gpmi: correct bitflip for erased NAND page
mtd: nand: gpmi: supp
support GPMI NAND on i.MX6QP
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 9 +
drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 5 -
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
b/drivers/mtd/nand/gpmi-nand/gpmi
On Wed, Apr 20, 2016 at 5:34 PM, Han Xu wrote:
>
>
>
> From: Yunhui Cui
> Sent: Wednesday, April 13, 2016 9:50 PM
> To: dw...@infradead.org; computersforpe...@gmail.com; han...@freescale.com
> Cc: linux-kernel@v
From: Boris Brezillon
Sent: Friday, April 29, 2016 2:31 AM
To: Han Xu
Cc: rich...@nod.at; dw...@infradead.org; computersforpe...@gmail.com;
linux-...@lists.infradead.org; linux-kernel@vger.kernel.org
Subject: Re: [PATCH] mtd: nand: gpmi: get correct
From: Yunhui Cui
Sent: Thursday, April 21, 2016 9:52 PM
To: Han Xu; Yunhui Cui; dw...@infradead.org; computersforpe...@gmail.com;
han...@freescale.com
Cc: linux-kernel@vger.kernel.org; linux-...@lists.infradead.org;
linux-arm-ker...@lists.infradead.org
From: Yunhui Cui
Sent: Thursday, April 21, 2016 3:41 AM
To: Han Xu; Yunhui Cui; dw...@infradead.org; computersforpe...@gmail.com;
han...@freescale.com
Cc: linux-kernel@vger.kernel.org; linux-...@lists.infradead.org;
linux-arm-ker...@lists.infradead.org
From: Yunhui Cui
Sent: Wednesday, April 13, 2016 9:50 PM
To: dw...@infradead.org; computersforpe...@gmail.com; han...@freescale.com
Cc: linux-kernel@vger.kernel.org; linux-...@lists.infradead.org;
linux-arm-ker...@lists.infradead.org; Yao Yuan; Yunhui Cu
From: Yunhui Cui
Sent: Wednesday, April 13, 2016 9:50 PM
To: dw...@infradead.org; computersforpe...@gmail.com; han...@freescale.com
Cc: linux-kernel@vger.kernel.org; linux-...@lists.infradead.org;
linux-arm-ker...@lists.infradead.org; Yao Yuan; Yunhui Cu
change the way to calculate pagesize to get correct free oob space for
legacy_set_geometry function.
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
b/drivers/mtd/nand
fix the raw_buffer pointer double free issue found by coverify.
CID 18344 (#2 of 2): Double free (USE_AFTER_FREE)
3. double_free: Calling gpmi_alloc_dma_buffer frees pointer
this->raw_buffer which has already been freed
Signed-off-by: Han Xu
---
changes in v2:
- add coverity check
fix the raw_buffer pointer double free issue found by coverify.
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 8122c69..dcb60b0 100644
1427 nor->flash_read = SPI_NOR_DUAL;
> 1428 }
>
>
> Thanks
> Yunhui
> -Original Message-
> From: Han Xu [mailto:xhnj...@gmail.com]
> Sent: Saturday, February 27, 2016 12:32 AM
> To: Yunhui Cui
> Cc: Yunhui Cui; dw...@infradead.org; com
#x27;t think QuadSPI driver need to check the m25p,fast-read property again
since spi-nor layer has already done that. Adding the property in flash node
should work in the same way.
>
> Thanks
> Yunhui
>
> -Original Message-
> From: Han Xu [mailto:xhnj...@gmail
listed all supported chips in DT.
Signed-off-by: Han Xu
---
Documentation/devicetree/bindings/mtd/gpmi-nand.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt
index
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to ecc_strength and if bitflip detected, GPMI driver will
correct the data to all 0xFF.
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi
add support for gpmi nand on i.MX6UL and i.MX7D, document the related
properties in DT and add the HW bitflip detection and correction for
i.MX6QP and i.MX7D.
The two document related patch are new and other three patches have no code
change.
Han Xu (5):
mtd: nand: gpmi: add GPMI NAND support
add the clocks and clock-names in DT property, gpmi-io clock is
mandatory for all platforms, but some platforms, such as i.MX6Q may
need more extra clocks for submodules. More details please refer to the
SoC reference manual.
Signed-off-by: Han Xu
---
Documentation/devicetree/bindings/mtd/gpmi
From: Han Xu
support GPMI NAND on i.MX6UL
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 9 +
drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 4 +++-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
b/drivers/mtd/nand
From: Han Xu
support GPMI NAND on i.MX7D
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi-nand/bch-regs.h | 14 +++---
drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 10 ++
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 27 ++-
drivers/mtd/nand/gpmi-nand/gpmi
On Tue, Feb 2, 2016 at 7:28 AM, Markus Pargmann wrote:
> Hi,
>
> On Saturday, January 23, 2016 03:01:47 PM Brian Norris wrote:
>> + Markus Pargmann
>>
>> On Wed, Dec 02, 2015 at 04:47:45PM -0600, Han Xu wrote:
>> > i.MX6QP and i.MX7D BCH module integrated a ne
On Mon, Feb 01, 2016 at 07:30:07PM +0800, Yunhui Cui wrote:
> The qspi driver add generic fast-read mode for different
> flash venders. There are some different board flash work on
> different mode, such fast-read, quad-mode.
> So we have to modify the third entrace parameter of spi_nor_scan().
>
hes connected to the
> bus, you should enable this property.
> (Please check the board's schematic.)
> + - big-endian : That means the IP register is big endian
>
> Example:
>
> --
> 2.1.0.27.g96db324
>
>
qspi: quadspi@20c {
> status = "disabled";
> - compatible = "fsl,vf610-qspi";
> + compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0x0 0x20c 0x0 0x1>,
> --
> 2.1.0.27.g96db324
>
>
Acked-by: Han xu
> __
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
or
> + "fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"
>- reg : the first contains the register location and length,
>the second contains the memory mapping address and length
>- reg-names: Should contain the reg names "Q
depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST
> depends on HAS_IOMEM
> help
> This enables support for the Quad SPI controller in master mode.
> --
> 2.1.0.27.g96db324
>
>
Acked-by: Han xu
> __
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
085a-dspi"
> + or
> + "fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
> - reg : Offset and length of the register set for the device
> - interrupts : Should contain SPI controller interrupt
> - clocks: from common clock binding: handle to dspi clock.
> --
> 2.1.0.27.g96db324
>
>
Acked-by: Han xu
> __
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
On Tue, Jan 26, 2016 at 03:23:56PM +0800, Yuan Yao wrote:
> LS1021a also support Freescale Quad SPI controller.
> Add fsl-quadspi support for ls1021a chip and make SPI_FSL_QUADSPI
> selectable for LS1021A SOC hardwares.
>
> Signed-off-by: Yuan Yao
> Acked-by: Han xu
> ---
-by: Yuan Yao
> Acked-by: Han xu
> ---
> Changed in v4:
> No changes.
>
> Changed in v3:
> Update my email to
>
> Changed in v2:
> Rebase to the lastest code.
> ---
> drivers/mtd/spi-nor/fsl-quadspi.c | 157
> +++---
>
On Fri, Jan 22, 2016 at 3:01 AM, Yao Yuan wrote:
> On Thu, Jan 21, 2016 at 11:42 PM, Han Xu < xhnj...@gmail.com > wrote:
>> On Thu, Jan 21, 2016 at 1:53 AM, Yuan Yao wrote:
>> > This patch set is used for add the fsl-quadspi support for ls1021a and
>> > ls104
On Thu, Jan 21, 2016 at 1:53 AM, Yuan Yao wrote:
> This patch set is used for add the fsl-quadspi support for ls1021a and
> ls1043a, so remove the patch:
> mtd: spi-nor: fsl-quadspi: extend support for some special requerment.
Please use --cover-letter to generate cover letter.
>
> This patch wi
On Thu, Dec 24, 2015 at 07:00:21PM +0800, Yuan Yao wrote:
> Add extra info in LUT table to support some special requerments.
> Spansion S25FS-S family flash need some special operations.
What's the special requirement, detail it.
>
> Signed-off-by: Yuan Yao
> ---
> Changed in v2:
> Update my em
On Thu, Dec 24, 2015 at 07:00:18PM +0800, Yuan Yao wrote:
> Add R/W functions for big- or little-endian registers:
> The qSPI controller's endian is independent of the CPU core's endian.
> So far, the qSPI have two versions for big-endian and little-endian.
>
> Signed-off-by: Yuan Yao
> ---
> Cha
On Wed, Dec 02, 2015 at 10:38:20AM +, Michal Suchanek wrote:
> The spi-nor write loop assumes that what is passed to the hardware
> driver write() is what gets written.
>
> When write() writes less than page size at once data is dropped on the
> floor. Check the amount of data writen and exit
From: Huang Shijie
Deep Sleep Mode(dsm) turns off the power for APBH DMA module, DMA
need to be re-initialized when system resumed back.
Signed-off-by: Huang Shijie
Signed-off-by: Han Xu
---
drivers/dma/mxs-dma.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff
From: Adrian Alonso
supports APBH DMA on i.MX7D by add extra clock clk_io
Signed-off-by: Fugang Duan
Signed-off-by: Adrian Alonso
Signed-off-by: Han Xu
---
drivers/dma/mxs-dma.c | 52 ---
1 file changed, 45 insertions(+), 7 deletions(-)
diff
e empty line
simplify mxs_dma_init return check
Adrian Alonso (1):
dmaengine: mxs: add i.MX7D APBH DMA support
Han Xu (4):
mtd: nand: gpmi: may use minimum required ecc for 744 oobsize NAND
mtd: nand: gpmi: add GPMI NAND support for i.MX7D
mtd: nand: gpmi: correct bitflip for erased NAND p
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to ecc_strength and if bitflip detected, GPMI driver will
correct the data to all 0xFF.
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi
support GPMI NAND on i.MX7D
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi-nand/bch-regs.h | 14 +++---
drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 10 ++
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 27 ++-
drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 7
registers value for
i.MX6QDL, the code doesn't distinguish different platforms to keep the
code simple.
Signed-off-by: Huang Shijie
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 47 +-
1 file changed, 46 insertions(+), 1 deletion(-)
diff --
failed to use the highest ecc, even without explicitly
claiming "fsl,use-minimum-ecc" in dts.
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi
support GPMI NAND on i.MX6UL
Signed-off-by: Han Xu
---
drivers/mtd/nand/gpmi-nand/gpmi-nand.c | 9 +
drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 4 +++-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
b/drivers/mtd/nand/gpmi-nand/gpmi
On Wed, Dec 02, 2015 at 10:38:19AM +, Michal Suchanek wrote:
> Return amount of data read/written or error as read(2)/write(2) does.
>
> Signed-off-by: Michal Suchanek
> ---
> drivers/mtd/spi-nor/fsl-quadspi.c | 18 +++---
> 1 file changed, 11 insertions(+), 7 deletions(-)
>
> d
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