Hi Sam/Daniel,
This is all very useful feedback, thank you.
On Tue, Apr 28, 2020 at 19:24 PM Daniel Vetter wrote:
>
> On Tue, Apr 28, 2020 at 8:18 PM Sam Ravnborg wrote:
> >
> > Hi Gareth.
> >
> > On Mon, Apr 27, 2020 at 09:21:47AM +0100, Gareth Williams wrote:
Hi Rob,
On Tue, Oct 01, 2019 at 13:02:34AM +0100, Rob Herring wrote:
> On Wed, Sep 18, 2019 at 09:04:34AM +0100, Gareth Williams wrote:
> > Note in the bindings documentation that pclk should be renamed if a
> > clock domain is used to enable the optional bus clock.
> >
>
Hi Mark,
On Wed, Sep 19, 2019 at 14:31:32AM +0100, Mark Brown wrote:
> On Wed, Sep 18, 2019 at 09:04:32AM +0100, Gareth Williams wrote:
>
> > Gareth Williams (1):
> > dt-bindings: snps,dw-apb-ssi: Add optional clock domain information
> >
> > Phil Edworthy (3):
From: Phil Edworthy
Enable runtime PM so that the clock used to access the registers in the
peripheral is turned on using a clock domain.
Signed-off-by: Phil Edworthy
Signed-off-by: Gareth Williams
---
v2:
- set spi_controller.auto_runtime_pm instead of using
pm_runtime_get_sync.
- Added
use gpios for the CS
signals.
Signed-off-by: Gareth Williams
Signed-off-by: Phil Edworthy
---
v2: no changes
---
drivers/spi/spi-dw-mmio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index edb3cf6..3640b01 100644
--- a/drivers/spi
Note in the bindings documentation that pclk should be renamed if a clock
domain is used to enable the optional bus clock.
Signed-off-by: Gareth Williams
---
v2: Introduced this patch.
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 ++-
1 file changed, 2 insertions(+), 1
domain in the
bindings documentation.
- Set spi_controller.auto_runtime_pm instead of using
pm_runtime_get_sync.
- Added pm_runtime_disable calls to dw_spi_remove_host and the error
condition of dw_spi_add_host.
Gareth Williams (1):
dt-bindings: snps,dw-apb-ssi: Add optional clock domain
also not needed as
Linux can use gpios for the CS signals.
Add a compatible string to handle any unforeseen issues that may arise, and
pave the way for DMA support.
Signed-off-by: Gareth Williams
Signed-off-by: Phil Edworthy
---
Note: All the other manufacturers detail their compatible strings
Hi Geert,
> On Mon, Sep 17, 2019 at 07:36 PM Geert Uytterhoeven
> wrote:
>
> Hi Gareth,
>
> On Mon, Sep 16, 2019 at 6:14 PM Gareth Williams
> wrote:
> > > On Mon, Sep 16, 2019 at 15:36 PM Geert Uytterhoeven
> > > wrote:
> > > On Fri, Sep
Hi Geert,
I appreciate the feedback.
> On Mon, Sep 16, 2019 at 15:36 PM Geert Uytterhoeven
> wrote:
> Hi Gareth,
>
> On Fri, Sep 13, 2019 at 2:13 PM Gareth Williams
> wrote:
> > From: Phil Edworthy
> >
> > Enable runtime PM so that the clock used to access
From: Phil Edworthy
Enable runtime PM so that the clock used to access the registers in the
peripheral is turned on using a clock domain.
Signed-off-by: Phil Edworthy
Signed-off-by: Gareth Williams
---
drivers/spi/spi-dw.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/spi
The Renesas RZ/N1 SPI Controller is based on the Synopsys DW SSI. This
series enables power mode in the driver so the clock domain will enable
the bus clock, adds the compatible string and updates the associated bindings
documentation.
Phil Edworthy (3):
dt: spi: Add Renesas RZ/N1 binding docume
also not needed as
Linux can use gpios for the CS signals.
Add a compatible string to handle any unforeseen issues that may arise, and
pave the way for DMA support.
Signed-off-by: Gareth Williams
Signed-off-by: Phil Edworthy
---
Note: All the other manufacturers detail their compatible strings
use gpios for the CS
signals.
Signed-off-by: Gareth Williams
Signed-off-by: Phil Edworthy
---
drivers/spi/spi-dw-mmio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index edb3cf6..3640b01 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b
The driver is gaining power domain support, so add the new property
to the DT binding and update the examples.
Signed-off-by: Gareth Williams
Reviewed-by: Geert Uytterhoeven
---
v4:
- Added missing HCLK to UART0 example to show the clock added
to the driver.
- Added Geert's Review
There are several clocks on the r9a06g032 which are currently not
enabled in their drivers that can be delegated to clock domain system
for power management. Therefore add support for clock domain
functionality to the r9a06g032 clock driver.
Signed-off-by: Gareth Williams
---
v4:
- Removed
e_add_module_clock.
- changed r9a06g032_detach_dev to a static function.
- Added new #power-domain-cells property to the required properties.
- Added "#power-domain-cells" and "power-domains" lines to examples.
v2:
- Rebased onto kernel/git/geert/renesas-drivers.git
Gareth Williams (2
There are several clocks on the r9ag032 which are currently not enabled
in their drivers that can be delegated to clock domain system for power
management. Therefore add support for clock domain functionality to the
r9a06g032 clock driver.
Signed-off-by: Gareth Williams
---
drivers/clk/renesas
The driver is gaining power domain support, so add the new property
to the DT binding and update the examples.
Signed-off-by: Gareth Williams
---
Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation
There are several clocks on the r9ag032 which are currently not enabled
in their drivers that can be delegated to clock domain system for power
management. Therefore add support for clock domain functionality to the
r9a06g032 clock driver after updating the relevant dt-bindings file.
Gareth
Hi Geert,
Thanks for the feedback. I added some additional information about the
logic I used for the USB clocks inline below and will send V3 shortly.
On Tue, May 22, 2019 at 1:02 PM Gareth Williams
wrote:
> Hi Gareth,
>
> On Tue, May 21, 2019 at 2:35 PM Gareth Williams
> wrot
There are several clocks on the r9ag032 which are currently not enabled
in their drivers that can be delegated to clock domain system for power
management. Therefore add support for clock domain functionality to the
r9a06g032 clock driver.
Signed-off-by: Gareth Williams
---
v2:
- Rebased onto
There are several clocks on the r9ag032 which are currently not enabled
in their drivers that can be delegated to clock domain system for power
management. Therefore add support for clock domain functionality to the
r9a06g032 clock driver.
Signed-off-by: Gareth Williams
---
drivers/clk/renesas
Signed-off-by: Gareth Williams
---
v2:
- Added dependancy information to patch notes.
- Expanded on optional clock comment for clarity
Depends on commit 60b8f0ddf1a ("clk: Add (devm_)clk_get_optional()
functions")
---
drivers/spi/spi-dw-mmio.c | 12
1 file changed, 12
Add documentation to the Synopsys SPI dt-bindings to support an
optional interface clock that may be used for register access.
Signed-off-by: Phil Edworthy
Signed-off-by: Gareth Williams
---
v2: Created this separate patch to detail the optional interface clock
property. This includes the
From: Phil Edworthy
The Synopsys SSI driver uses a mandatory clock that is not documented,
so detail it in the device tree bindings. Also correct the spelling of
"pins" in the "Optional Properties" section for the driver.
Signed-off-by: Phil Edworthy
Signed-off-by: Gar
expanded for clarity.
Gareth Williams (1):
dt-bindings: snps,dw-apb-ssi: Add optional clock bindings
documentation
Phil Edworthy (2):
dt-bindings: snps,dw-apb-ssi: Add mandatory clock bindings
documentation
spi: dw: Add support for an optional interface clock
Documentation/devicetree
> On Sat, Mar 03, 2019 at 23:32 +0100, Mark Brown wrote:
> > On Thu, Feb 28, 2019 at 01:25:41PM +0000, Gareth Williams wrote:
> > From: Phil Edworthy
> >
> > The driver requires a clock property, so detail it in the docs.
> > Fix a typo, 'pis' to &
Hi Mark,
> On Mon, Mar 04, 2019 00:05:00, Mark Brown wrote:
>
> On Thu, Feb 28, 2019 at 01:25:42PM +0000, Gareth Williams wrote:
> > From: Phil Edworthy
> >
> > The Synopsys SSI Controller has an interface clock, but most SoCs hide
> > this away. However, o
Signed-off-by: Gareth Williams
Acked-by: Wolfram Sang
---
v5:
- Updated comments to reference "interface clock" instead of
"peripheral clock".
- Corrected spelling in commit message, changing "explicity" to
"explicitly".
v4:
- Updated comments to re
The Synopsys I2C Controller has an interface clock that some SoCs
require to access the registers. This series also details the new clock
property in the bindings documentation.
v5:
- Code comments and commit messages updated to reference "interface clock"
instead of "peripheral clock".
v4:
Signed-off-by: Gareth Williams
---
drivers/spi/spi-dw-mmio.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 4bd59a9..7cbc173 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -30,6 +30,7
From: Phil Edworthy
The driver requires a clock property, so detail it in the docs.
Fix a typo, 'pis' to 'pins'.
Add documentation for a separate, optional, interface clock.
Signed-off-by: Phil Edworthy
Signed-off-by: Gareth Williams
---
Documentation/devicetree/bind
The Synopsys SSI Controller has an interface clock that must be
explicitly enabled in order to access the registers. This patch series
adds support for the interface clock and adds the associated bindings
documentation.
Phil Edworthy (2):
dt: snps,dw-apb-ssi: Add clock bindings documentation
> On Sat, Feb 23, 2019 at 09:32 +0100, w...@the-dreams.de wrote:
>> On Thu, Feb 21, 2019 at 04:10:57PM +0000, Gareth Williams wrote:
>> The Synopsys I2C Controller has a peripheral clock that some SoCs
>> require to access the registers. This series also details the new
>
-off-by: Gareth Williams
Acked-by: Wolfram Sang
---
v4:
- Updated comments to reference "peripheral clock"
instead of "bus clock".
- Added Wolfram's Acked-by
v3:
- busclk renamed to pclk.
- Added comment with dw_i2c_dev struct definition describing pclk.
- Added
The Synopsys I2C Controller has a peripheral clock that some SoCs
require to access the registers. This series also details the new clock
property in the bindings documentation.
v4:
- Code comments and commit messages updated to reference "peripheral clock"
instead of "bus clock".
- Rebased
From: Phil Edworthy
The Synopsys I2C Controller has a bus clock, but most SoCs hide this away.
However, on some SoCs you need to explicity enable the bus clock in order
to access the registers. Therefore, add support for an optional bus clock.
Signed-off-by: Phil Edworthy
Signed-off-by: Gareth
The Synopsys I2C Controller has a bus clock that some SoCs require to access
the registers. This series also details the new clock property in the bindings
documentation.
v3:
- busclk renamed to pclk.
- Added comment with dw_i2c_dev struct definition describing pclk.
- Added enable rollback of
Sorry, the email below was sent prematurely and will be resent shortly.
-Gareth
> On 20 February 2019 13:26 Gareth Williams wrote:
> The Synopsys I2C Controller has a bus clock that some SoCs require to access
> the registers. This series also details the new clock property in the
The Synopsys I2C Controller has a bus clock that some SoCs require to access
the registers. This series also details the new clock property in the bindings
documentation.
v3:
- busclk renamed to pclk.
- Added comment with dw_i2c_dev struct definition describing pclk.
- Added enable rollback of
From: Phil Edworthy
The Synopsys I2C Controller has a bus clock, but most SoCs hide this away.
However, on some SoCs you need to explicity enable the bus clock in order
to access the registers. Therefore, add support for an optional bus clock.
Signed-off-by: Phil Edworthy
Signed-off-by: Gareth
The Synopsys I2C Controller has a bus clock that some SoCs require to access
the registers. This series also details the new clock property in the bindings
documentation.
v2:
- Use new devm_clk_get_optional() function as it simplifies handling when
the optional clock is not present.
Phil Edwo
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