On Sun, 1 Nov 2020 at 08:20, Jernej Skrabec wrote:
>
> RX/TX delay on OrangePi One Plus board is set on PHY. Reflect that in
> ethernet node.
>
> Fixes: 7ee32a17e0d6 ("arm64: dts: allwinner: h6: orangepi-one-plus: Enable
> ethernet")
> Signed-off-by: Jernej Skrabec
Hi Jernej,
Tested-by: Marcus C
On Wed, 16 Oct 2019 at 10:04, Maxime Ripard wrote:
>
> On Wed, Oct 16, 2019 at 09:07:34AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > On the newer SoCs the offset is used to set the mode of the
> > connection. As it is to be used elsewhere then it makes sense
> > to move it
On Wed, 16 Oct 2019 at 10:06, Maxime Ripard wrote:
>
> Hi,
>
> On Wed, Oct 16, 2019 at 09:07:35AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > Newer SoCs like the H6 have the channel offset bits in a different
> > position to what is on the H3. As we will eventually add mult
On Fri, 30 Aug 2019 at 13:45, Mark Brown wrote:
>
> On Wed, Aug 21, 2019 at 06:23:20PM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > Fixes: 21faaea1343f ("ASoC: sun4i-i2s: Add support for A83T")
> > Signed-off-by: Marcus Cooper
> > ---
>
> This doesn't apply against current
On Tue, 27 Aug 2019 at 11:34, Maxime Ripard wrote:
>
> On Mon, Aug 26, 2019 at 08:07:33PM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > On the newer SoCs such as the H3 and A64 this is set by default
> > to transfer a 0 after each sample in each slot. However the A10
> > and
On Tue, 27 Aug 2019 at 09:01, Maxime Ripard wrote:
>
> On Mon, Aug 26, 2019 at 08:07:34PM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > Some codecs such as i2s based HDMI audio and the Pine64 DAC require
> > a different amount of bit clocks per frame than what is calculated
>
On Tue, 27 Aug 2019 at 10:01, Chen-Yu Tsai wrote:
>
> On Tue, Aug 27, 2019 at 1:55 PM Code Kipper wrote:
> >
> > On Tue, 27 Aug 2019 at 06:13, Chen-Yu Tsai wrote:
> > >
> > > On Tue, Aug 27, 2019 at 2:07 AM wrote:
> > > >
> > > > From
On Tue, 27 Aug 2019 at 06:13, Chen-Yu Tsai wrote:
>
> On Tue, Aug 27, 2019 at 2:07 AM wrote:
> >
> > From: Marcus Cooper
> >
> > The regmap configuration is set up for the legacy block on the
> > A83T whereas it uses the new block with a larger register map.
>
> Looking at the code Allwinner pre
On Wed, 14 Aug 2019 at 08:09, wrote:
>
> From: Jernej Skrabec
>
> I2S doesn't work if parent rate couldn't be change. Difference between
> wanted and actual rate is too big.
>
> Fix this by adding CLK_SET_RATE_PARENT flag to I2S clocks.
>
> Signed-off-by: Jernej Skrabec
Signed-off-by: Marcus Co
ThanksI've added to my next patch series but if you could add it
when applying that would be great.
BR,
CK
On Wed, 21 Aug 2019 at 06:07, Chen-Yu Tsai wrote:
>
> On Wed, Aug 14, 2019 at 2:09 PM wrote:
> >
> > From: Jernej Skrabec
> >
> > I2S doesn't work if parent rate couldn't be change. Di
On Wed, 14 Aug 2019 at 13:08, Maxime Ripard wrote:
>
> Hi,
>
> On Wed, Aug 14, 2019 at 08:08:41AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > Codecs without a control connection such as i2s based HDMI audio and
> > the Pine64 DAC require a different amount of bit clocks per
On Wed, 14 Aug 2019 at 11:30, Mark Brown wrote:
>
> On Wed, Aug 14, 2019 at 08:08:41AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > Codecs without a control connection such as i2s based HDMI audio and
> > the Pine64 DAC require a different amount of bit clocks per frame than
On Wed, 14 Aug 2019 at 13:08, Maxime Ripard wrote:
>
> Hi,
>
> On Wed, Aug 14, 2019 at 08:08:40AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > On the newer SoCs such as the H3 and A64 this is set by default
> > to transfer a 0 after each sample in each slot. However the A10
On Wed, 14 Aug 2019 at 13:08, Maxime Ripard wrote:
>
> On Wed, Aug 14, 2019 at 08:08:43AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > There is a need to support more formats on the newer SoCs(H3 and later).
> > Extend the formats supported to include DSP_A and DSP_B modes.
On Wed, 14 Aug 2019 at 13:08, Maxime Ripard wrote:
>
> On Wed, Aug 14, 2019 at 08:08:51AM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > The i2s block supports multi-lane i2s output however this functionality
> > is only possible in earlier SoCs where the pins are exposed and
On Wed, 14 Aug 2019 at 09:57, Jernej Škrabec wrote:
>
> Hi!
>
> Dne sreda, 14. avgust 2019 ob 08:08:50 CEST je codekip...@gmail.com
> napisal(a):
> > From: Jernej Skrabec
> >
> > H6 I2S is very similar to that in H3, except it supports up to 16
> > channels.
> >
> > Signed-off-by: Jernej Skrabec
On Wed, 14 Aug 2019 at 10:28, Jernej Škrabec wrote:
>
> Hi!
>
> Dne sreda, 14. avgust 2019 ob 08:08:53 CEST je codekip...@gmail.com
> napisal(a):
> > From: Marcus Cooper
> >
> > Extend the functionality of the driver to include support of 20 and
> > 24 bits per sample for the earlier SoCs.
> >
>
On Wed, 14 Aug 2019 at 10:38, Jernej Škrabec wrote:
>
> Hi!
>
> Dne sreda, 14. avgust 2019 ob 08:08:54 CEST je codekip...@gmail.com
> napisal(a):
> > From: Marcus Cooper
> >
> > Bypass the regmap cache when flushing the i2s FIFOs and modify the tables
> > to reflect this.
> >
> > Signed-off-by: M
On Tue, 4 Jun 2019 at 09:53, Chen-Yu Tsai wrote:
>
> On Tue, Jun 4, 2019 at 1:47 AM wrote:
> >
> > From: Marcus Cooper
> >
> > On the newer SoCs this is set by default to transfer a 0 after
> > each sample in each slot. However the platform that this driver
> > was developed on had the default s
On Tue, 4 Jun 2019 at 11:02, Christopher Obbard wrote:
>
> On Tue, 4 Jun 2019 at 09:43, Code Kipper wrote:
> >
> > On Tue, 4 Jun 2019 at 09:58, Maxime Ripard
> > wrote:
> > >
> > > On Mon, Jun 03, 2019 at 07:47:32PM +0200, codekip...@gm
On Tue, 4 Jun 2019 at 09:46, Maxime Ripard wrote:
>
> On Mon, Jun 03, 2019 at 07:47:30PM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > We have a number of flags used to identify the functionality
> > of the IP block found on the sun8i-h3 and later devices. As it
> > is only n
On Tue, 4 Jun 2019 at 09:58, Maxime Ripard wrote:
>
> On Mon, Jun 03, 2019 at 07:47:32PM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > The i2s block supports multi-lane i2s output however this functionality
> > is only possible in earlier SoCs where the pins are exposed and f
On Tue, 4 Jun 2019 at 09:39, Chen-Yu Tsai wrote:
>
> On Tue, Jun 4, 2019 at 3:34 PM Maxime Ripard
> wrote:
> >
> > On Mon, Jun 03, 2019 at 07:47:27PM +0200, codekip...@gmail.com wrote:
> > > From: Marcus Cooper
> > >
> > > Although not causing any noticeable issues, the mask for the
> > > chann
On 13 March 2018 at 09:23, Maxime Ripard wrote:
> On Tue, Mar 13, 2018 at 09:15:49AM +0100, Code Kipper wrote:
>> On 13 March 2018 at 09:00, Maxime Ripard wrote:
>> > On Mon, Mar 12, 2018 at 04:57:51PM +0100, codekip...@gmail.com wrote:
>> >> From: Marcus Coo
On 13 March 2018 at 09:00, Maxime Ripard wrote:
> On Mon, Mar 12, 2018 at 04:57:51PM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The i2s block supports multi-lane i2s output however this functionality
>> is only possible in earlier SoCs where the pins are exposed and for
>> th
On 29 January 2018 at 12:32, Mark Brown wrote:
> On Mon, Jan 29, 2018 at 08:34:00AM +0100, Code Kipper wrote:
>
>> I'm not sure..I was looking for a clean example of being able to
>> override the number of bclks in the lrclk width and some other
>> devices(Rpi) were
On 29 January 2018 at 08:38, Chen-Yu Tsai wrote:
> On Mon, Jan 29, 2018 at 3:34 PM, Code Kipper wrote:
>> On 29 January 2018 at 02:50, Chen-Yu Tsai wrote:
>>> On Wed, Jan 24, 2018 at 10:10 PM, wrote:
>>>> From: Marcus Cooper
>>>>
>>>>
On 29 January 2018 at 02:50, Chen-Yu Tsai wrote:
> On Wed, Jan 24, 2018 at 10:10 PM, wrote:
>> From: Marcus Cooper
>>
>> Some codecs require a different amount of a bit clocks per frame than
>> what is calculated by the sample width. Use the tdm slot bindings to
>> provide this mechanism.
>>
>>
On 25 January 2018 at 09:41, Maxime Ripard
wrote:
> Hi,
>
> On Wed, Jan 24, 2018 at 03:11:01PM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> On the newer SoCs this is set by default to transfer a 0 after
>> each sample in each slot. Add the regmap field to configure this
>> and
On 24 January 2018 at 15:11, wrote:
> From: Marcus Cooper
>
> On the newer SoCs this is set by default to transfer a 0 after
> each sample in each slot. Add the regmap field to configure this
> and set it so that it pads the sample with 0s.
>
> Signed-off-by: Marcus Cooper
NACK missing regmap f
On 14 December 2017 at 08:29, Chen-Yu Tsai wrote:
> When any of the DAI hardware configuration callbacks (.hw_param,
> .set_fmt, .set_sysclk) fails, there is no explanation about why it
> failed. This is particularly confusing for .hw_param, which covers
> many parameters of the DAI. Telling the u
On 31 August 2017 at 16:52, Maxime Ripard
wrote:
> On Thu, Aug 31, 2017 at 01:36:09AM +0200, Stefan Brüns wrote:
>> The A64 SoC has the same dma engine as the H3 (sun8i), with a
>> reduced amount of physical channels. Add the proper config data
>> and compatible string to support it.
>>
>> Signed-
On 31 August 2017 at 13:50, Code Kipper wrote:
> Hi Mark,
>
> Wens has given this patch series his blessing so it's good to go.
>
> Let us know if you need me to resubmit,
I take that back as I can see that's all been submitted.
Thanks,
CK
>
> BR,
> CK
>
Hi Mark,
Wens has given this patch series his blessing so it's good to go.
Let us know if you need me to resubmit,
BR,
CK
On 19 August 2017 at 14:48, wrote:
> From: Marcus Cooper
>
> Hi All,
> please find attached a series of patches to bring i2s support to the
> Allwinner H3 SoC. This has be
On 31 August 2017 at 01:36, Stefan Brüns wrote:
> The A64 SoC has the same dma engine as the H3 (sun8i), with a
> reduced amount of physical channels. Add the proper config data
> and compatible string to support it.
>
> Signed-off-by: Stefan Brüns
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a6
On 25 August 2017 at 12:32, Antony Antony wrote:
> Add initial DT support for NanoPi NEO Plus 2 by FriendlyELEC
> Allwinner quad core H5 Cortex A53 with an ARM Mali-450MP GPU
> 1 GB DDR3 RAM
> 8GB eMMC flash (Samsung KLM8G1WEPD-B031)
>
On 12 August 2017 at 14:27, Chen-Yu Tsai wrote:
> On Sat, Aug 12, 2017 at 7:00 PM, wrote:
>> From: Marcus Cooper
>>
>> The sun8i-h3 introduces a lot of changes to the i2s block such
>> as different register locations, extended clock division and
>> more operational modes. As we have to consider
On 1 August 2017 at 10:31, Chen-Yu Tsai wrote:
> On Sat, Jul 29, 2017 at 10:17 PM, wrote:
>> From: Marcus Cooper
>>
>> On the original i2s block the channel mapping and selection were
>> configured for stereo audio by default: This is not the case with
>> the newer SoCs and they are also locate
On 1 August 2017 at 04:55, Chen-Yu Tsai wrote:
> On Sat, Jul 29, 2017 at 10:17 PM, wrote:
>> From: Marcus Cooper
>>
>> The BCLKDIV and MCLKDIV found on newer SoCs start from an offset of 1.
>> Add the functionality to adjust the division values according to the
>> needs to the device being used
On 31 July 2017 at 09:05, Olliver Schinagl wrote:
> Hey Marcus,
>
> On 29-07-17 16:17, codekip...@gmail.com wrote:
>>
>> From: Marcus Cooper
>>
>> Hi All,
>> please find attached a series of patches to bring i2s support to the
>> Allwinner H3 SoC. This has been tested with the following setups:
>
On 25 July 2017 at 16:36, Maxime Ripard
wrote:
> Hi,
>
> On Sat, Jul 22, 2017 at 08:53:52AM +0200, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The sun8i-h3 introduces a lot of changes to the i2s block such
>> as different register locations, extended clock division and
>> more operat
On 25 July 2017 at 07:52, Maxime Ripard
wrote:
> Hi Markus,
>
> On Sat, Jul 22, 2017 at 08:53:51AM +0200, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> In preparation for changing this driver to support newer SoC
>> implementations then where needed there has been a switch from
>> regm
On 5 July 2017 at 18:20, Maxime Ripard wrote:
> On Wed, Jul 05, 2017 at 05:43:24PM +0200, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> There are a lot of changes to the sun8i-h3 i2s block but not enough
>> to warrant to a new driver.
>>
>> Signed-off-by: Marcus Cooper
>> ---
>> .../
On 19 January 2017 at 18:03, Mark Brown wrote:
> On Wed, Jan 18, 2017 at 08:09:00AM +0100, Code Kipper wrote:
>
>> I missed the binding documentation on the patch for the driver so I
>> pushed it separately instead of pushing a new patch version.
>> You can find it under t
On 17 January 2017 at 19:15, Mark Brown wrote:
> On Thu, Jan 12, 2017 at 06:33:43PM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The H3 SoC uses the same SPDIF block as found in earlier SoCs, but the
>> transmit fifo is at a different address.
>>
>> Signed-off-by: Marcus Cooper
On 20 December 2016 at 20:16, Maxime Ripard
wrote:
> Hi,
>
> On Tue, Dec 20, 2016 at 03:55:24PM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> Newer SoCs have additional functionality so a quirks structure
>> has been added to handle them. So far we've seen the use of a
>> reset
On 11 November 2016 at 11:05, Chen-Yu Tsai wrote:
> The audio module clocks are supposed to be set according to the sample
> rate of the audio stream. The audio PLL provides the clock signal for
> thees module clocks, and only it is freely tunable.
nick! these
CK
>
> Set CLK_SET_RATE_PARENT for th
On 4 October 2016 at 11:46, Mylène Josserand
wrote:
> Add the audio card for sun8i SoC. This card links the codec driver
> (digital part) with the DAI driver. The analog codec driver is
> added as an aux_device.
>
> Signed-off-by: Mylène Josserand
> ---
> sound/soc/sunxi/Kconfig | 14 +++
>
On 4 October 2016 at 11:46, Mylène Josserand
wrote:
> Add APB deassert function for sun4i-i2s driver.
>
> Signed-off-by: Mylène Josserand
> ---
> sound/soc/sunxi/sun4i-i2s.c | 16 +++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/sound/soc/sunxi/sun4i-i2s.c b/so
On 4 October 2016 at 11:46, Mylène Josserand
wrote:
> Add the analog part of the sun8i (A33) codec driver. This driver
> implements all the analog part of the codec using PRCM registers.
>
> The read/write regmap functions must be handled in a custom way as
> the PRCM register behaves as "mailbox"
On 4 October 2016 at 11:46, Mylène Josserand
wrote:
> Add the audio card for sun8i SoC. This card links the codec driver
> (digital part) with the DAI driver. The analog codec driver is
> added as an aux_device.
>
> Signed-off-by: Mylène Josserand
> ---
> sound/soc/sunxi/Kconfig | 14 +++
>
On 29 August 2016 at 20:03, Danny Milosavljevic wrote:
>
> Note: Mic1 Capture Volume is in a different register on A20 than on A10.
> Note: Mic2 Capture Volume is in a different register on A20 than on A10.
> ---
> sound/soc/sunxi/sun4i-codec.c | 256
> ++
On 30 July 2016 at 17:17, Maxime Ripard
wrote:
> On Sat, Jul 30, 2016 at 04:27:15PM +0200, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The A31 SoC uses the same SPDIF block as found in earlier SoCs, but its
>> reset is controlled via a separate reset controller.
>>
>> Signed-off-by:
snip
> +
> + /* Always favor the highest oversampling rate */
> + for (i = (ARRAY_SIZE(sun4i_i2s_oversample_rates) - 1); i >= 0; i--) {
> + unsigned int oversample_rate = sun4i_i2s_oversample_rates[i];
> +
> + bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample
Hi Danny,
I've got some patches to go which covers pretty much everything that
we can manage with the sun4i-codec. I'm only lacking testing of
certain bits as I don't have capable hardware(i.e. FM capture). I've
ignored the phone out part of the A20 as I couldn't find the pins.
I'll try to upload t
On 22 February 2016 at 04:12, Mark Brown wrote:
> On Sun, Feb 21, 2016 at 12:13:36PM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> For now just the SPDIF transmitter has been tested on a Mele A2000(A10)
>> and a Itead Ibox(A20).
>
> This was already applied. If any updates are
NAK...last bunch of changes introduced a warning which slipped
through, I'll fix that and send a new patch series.
CK
On 8 February 2016 at 16:26, wrote:
> From: Marcus Cooper
>
> This patch set adds support for the Allwinner SPDIF transceiver.
>
> For now just the SPDIF transmitter has been te
On 5 February 2016 at 10:27, Maxime Ripard
wrote:
> Hi,
>
> On Thu, Feb 04, 2016 at 12:09:22PM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The sun4i, sun5i and sun7i SoC families have an SPDIF
>> block which is capable of playback and capture.
>>
>> This patch enables the play
On 2 February 2016 at 22:17, Maxime Ripard
wrote:
> Hi,
>
> It looks mostly good on my side, a few comments though.
>
> On Tue, Feb 02, 2016 at 03:49:54PM +0100, codekip...@gmail.com wrote:
>> +#ifdef CONFIG_PM
>> +static int sun4i_spdif_runtime_suspend(struct device *dev)
>> +{
>> + struct su
On 2 February 2016 at 23:31, Maxime Ripard
wrote:
> Hi,
>
> On Tue, Feb 02, 2016 at 03:49:53PM +0100, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> Add devicetree bindings for the SPDIF transceiver found on
>> found on Allwinners A10 and A20 SoCs.
>>
>> Signed-off-by: Marcus Cooper
>>
On 6 October 2015 at 11:00, Maxime Ripard
wrote:
> On Fri, Oct 02, 2015 at 08:44:03AM +0200, Code Kipper wrote:
>> >> +config SND_SOC_SUNXI_DAI_SPDIF
>> >> +tristate
>> >> + depends on OF
>> >> +select SND_SOC_GENE
On 5 October 2015 at 10:41, Maxime Ripard
wrote:
> On Fri, Oct 02, 2015 at 07:24:20AM +0200, Code Kipper wrote:
>> >> +
>> >> + - compatible : should be one of the following:
>> >> +- "allwinner,sun4i-a10-spdif": for the Allwinne
>> +config SND_SOC_SUNXI_DAI_SPDIF
>> +tristate
>> + depends on OF
>> +select SND_SOC_GENERIC_DMAENGINE_PCM
>> +select REGMAP_MMIO
>> +
>> +config SND_SOC_SUNXI_MACHINE_SPDIF
>> +tristate "APB on-chip sun4i/sun5i/sun7i SPDIF"
>> + depends on OF
>> +se
>> +
>> + - compatible : should be one of the following:
>> +- "allwinner,sun4i-a10-spdif": for the Allwinner A10 SoC
>> +- "allwinner,sun7i-a20-spdif": for the Allwinner A20 SoC
>> +- "allwinner,sun6i-a31-spdif": for the Allwinner A31 SoC
>
> Are all these compatibles re
On 28 September 2015 at 10:25, Maxime Ripard
wrote:
> On Thu, Sep 24, 2015 at 04:30:05PM +0200, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The sun4i, sun6i and sun7i SoC families have an SPDIF
>> block which is capable of playback and capture.
>>
>> This patch enables the playback o
On 24 September 2015 at 19:29, Mark Brown wrote:
> On Thu, Sep 24, 2015 at 04:30:05PM +0200, codekip...@gmail.com wrote:
>> From: Marcus Cooper
>>
>> The sun4i, sun6i and sun7i SoC families have an SPDIF
>> block which is capable of playback and capture.
>
> I'm not seeing patches 1 or 2 - what's
On 23 September 2015 at 20:41, Code Kipper wrote:
> Hi All,
> I'm getting a "fatal: 'send-email'" response with the last patch(even
> though the dry run of the patch series worked) and I've not been able
> to work around it. I'll post it as soon a
Hi All,
I'm getting a "fatal: 'send-email'" response with the last patch(even
though the dry run of the patch series worked) and I've not been able
to work around it. I'll post it as soon as I can work out what the
issue is,
BR,
CK
On 23 September 2015 at 20:04, wrote:
> From: Marcus Cooper
>
>
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