Anup Patel
Reviewed-by: Andrew Jones
Signed-off-by: Atish Patra
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 132 +++
1 file changed, 132 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c
b/tools/testing/selftests/kvm/riscv/get-reg-list.c
This series improves the following tests.
1. Get-reg-list : Adds vector support
2. SBI PMU test : Distinguish between different types of illegal exception
The first patch is just helper patch that adds stval support during
exception handling.
Signed-off-by: Atish Patra
---
Changes in v3
The current exeception register structure in selftests are missing
few registers (e.g stval). Instead of adding it manually, change
the ex_regs to align with pt_regs to make it future proof.
Suggested-by: Andrew Jones
Reviewed-by: Andrew Jones
Signed-off-by: Atish Patra
---
.../selftests/kvm
Reviewed-by: Andrew Jones
Signed-off-by: Atish Patra
---
.../testing/selftests/kvm/include/riscv/processor.h | 13 +
tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 20 +++-
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/tools/testing/selftests/kvm
On 4/30/25 12:17 AM, Andrew Jones wrote:
On Tue, Apr 29, 2025 at 05:18:47PM -0700, Atish Patra wrote:
Add vector related tests with the ISA extension standard template.
However, the vector registers are bit tricky as the register length is
variable based on vlenb value of the system. That&#
On 4/30/25 12:09 AM, Andrew Jones wrote:
On Tue, Apr 29, 2025 at 05:18:46PM -0700, Atish Patra wrote:
Currently, the sbi_pmu_test continues if the exception type is illegal
instruction because access to hpmcounter will generate that. However
illegal instruction exception may occur due to the
On 4/30/25 12:05 AM, Andrew Jones wrote:
On Tue, Apr 29, 2025 at 05:18:45PM -0700, Atish Patra wrote:
The current exeception register structure in selftests are missing
few registers (e.g stval). Instead of adding it manually, change
the ex_regs to align with pt_regs to make it future proof
The current exeception register structure in selftests are missing
few registers (e.g stval). Instead of adding it manually, change
the ex_regs to align with pt_regs to make it future proof.
Suggested-by: Andrew Jones
Signed-off-by: Atish Patra
---
.../selftests/kvm/include/riscv/processor.h
This series improves the following tests.
1. Get-reg-list : Adds vector support
2. SBI PMU test : Distinguish between different types of illegal exception
The first patch is just helper patch that adds stval support during
exception handling.
Signed-off-by: Atish Patra
---
Changes in v2
Anup Patel
Signed-off-by: Atish Patra
---
tools/testing/selftests/kvm/riscv/get-reg-list.c | 133 +++
1 file changed, 133 insertions(+)
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c
b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index 569f2d67c9b8..814dd98
instructions and which csrs are
being accessed if it is csr access instructions. Assert in all cases
except if it is a csr access instructions that access valid PMU related
registers.
Reviewed-by: Anup Patel
Signed-off-by: Atish Patra
---
.../testing/selftests/kvm/include/riscv/processor.h | 13
On 4/25/25 7:20 AM, Andrew Jones wrote:
On Mon, Mar 24, 2025 at 05:40:31PM -0700, Atish Patra wrote:
Add vector related tests with the ISA extension standard template.
However, the vector registers are bit tricky as the register length is
variable based on vlenb value of the system. That&#
On 4/25/25 6:33 AM, Andrew Jones wrote:
On Mon, Mar 24, 2025 at 05:40:30PM -0700, Atish Patra wrote:
Currently, the sbi_pmu_test continues if the exception type is illegal
instruction because access to hpmcounter will generate that. However, we
may get illegal for other reasons as well which
On 4/25/25 6:50 AM, Andrew Jones wrote:
On Mon, Mar 24, 2025 at 05:40:29PM -0700, Atish Patra wrote:
Save stval during exception handling so that it can be decoded to
figure out the details of exception type.
Signed-off-by: Atish Patra
---
tools/testing/selftests/kvm/include/riscv
Add vector related tests with the ISA extension standard template.
However, the vector registers are bit tricky as the register length is
variable based on vlenb value of the system. That's why the macros are
defined with a default and overidden with actual value at runtime.
Signed-off-by:
Save stval during exception handling so that it can be decoded to
figure out the details of exception type.
Signed-off-by: Atish Patra
---
tools/testing/selftests/kvm/include/riscv/processor.h | 1 +
tools/testing/selftests/kvm/lib/riscv/handlers.S | 2 ++
2 files changed, 3 insertions
are
being accessed if it is csr access instructions. Assert in all cases
except if it is a csr access instructions that access valid PMU related
registers.
Signed-off-by: Atish Patra
---
tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 32
1 file changed, 32 insertions
This series improves the following tests.
1. Get-reg-list : Adds vector support
2. SBI PMU test : Distinguish between different types of illegal exception
The first patch is just helper patch that adds stval support during
exception handling.
Signed-off-by: Atish Patra
---
Atish Patra (3
This series adds a fix for KVM PMU code and improves the pmu selftest
by allowing generating precise number of interrupts. It also provided
another additional option to the overflow test that allows user to
generate custom number of LCOFI interrupts.
Signed-off-by: Atish Patra
---
Changes in v2
as well.
Reviewed-by: Andrew Jones
Signed-off-by: Atish Patra
---
tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
to run via perf_event_enable during
either the above mentioned scenario.
Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling")
Reviewed-by: Andrew Jones
Signed-off-by: Atish Patra
---
arch/riscv/kvm/vcpu_pmu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/
It is helpful to vary the number of the LCOFI interrupts generated
by the overflow test. Allow additional argument for overflow test
to accommodate that. It can be easily cross-validated with
/proc/interrupts output in the host.
Signed-off-by: Atish Patra
---
tools/testing/selftests/kvm/riscv
: Andrew Jones
Signed-off-by: Atish Patra
---
tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 40 +++-
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
index
as well.
Signed-off-by: Atish Patra
---
tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
index f45c0ecc902d
It is helpful to vary the number of the LCOFI interrupts generated
by the overflow test. Allow additional argument for overflow test
to accommodate that. It can be easily cross-validated with
/proc/interrupts output in the host.
Signed-off-by: Atish Patra
---
tools/testing/selftests/kvm/riscv
-by: Atish Patra
---
tools/testing/selftests/kvm/riscv/sbi_pmu_test.c | 40 +++-
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
index 284bc80193bd..533b76d0de82
This series adds a fix for KVM PMU code and improves the pmu selftest
by allowing generating precise number of interrupts. It also provided
another additional option to the overflow test that allows user to
generate custom number of LCOFI interrupts.
Signed-off-by: Atish Patra
---
Atish Patra (4
to run via perf_event_enable during
either the above mentioned scenario.
Fixes: 0cb74b65d2e5 ("RISC-V: KVM: Implement perf support without sampling")
Signed-off-by: Atish Patra
---
arch/riscv/kvm/vcpu_pmu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/kvm/vcpu_pm
On Sat, Apr 17, 2021 at 8:36 PM Atish Patra wrote:
>
> On Mon, Mar 29, 2021 at 10:04 AM Vitaly Wool wrote:
> >
> > On Sat, Mar 27, 2021 at 6:24 PM Alex Ghiti wrote:
> > >
> > > Hi Atish,
> > >
> > > Le 3/3/21 à 3:02 PM, Atish Patra a écri
On Mon, Mar 29, 2021 at 10:04 AM Vitaly Wool wrote:
>
> On Sat, Mar 27, 2021 at 6:24 PM Alex Ghiti wrote:
> >
> > Hi Atish,
> >
> > Le 3/3/21 à 3:02 PM, Atish Patra a écrit :
> > > Add initial DTS for Microchip ICICLE board having only
> > > es
On Mon, Mar 29, 2021 at 9:17 PM Palmer Dabbelt wrote:
>
> On Wed, 03 Mar 2021 12:02:48 PST (-0800), Atish Patra wrote:
> > This series adds minimal support for Microchip Polar Fire Soc Icicle kit.
> > It is rebased on v5.12-rc1 and depends on clock support.
> > Only MMC
Signed-off-by: Atish Patra
---
arch/riscv/include/asm/csr.h | 58
1 file changed, 58 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index caadfc1d7487..7ce8df8f1683 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch
in this core driver wile PMU specific driver can implement PMU
specific features. For example, the SBI specific functionality will be
implemented in the SBI specific driver.
Signed-off-by: Atish Patra
---
drivers/perf/Kconfig | 8 +
drivers/perf/Makefile | 1 +
drivers
provides an easy way out in future where we can remove the
legacy driver.
Signed-off-by: Atish Patra
---
drivers/perf/Kconfig| 9
drivers/perf/Makefile | 3 ++
drivers/perf/riscv_pmu.c| 2 +
drivers/perf/riscv_pmu_legacy.c | 88
This patch adds all the definitions defined by the SBI PMU extension.
Signed-off-by: Atish Patra
---
arch/riscv/include/asm/sbi.h | 80
1 file changed, 80 insertions(+)
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index
/g/tech-unixplatformspec/message/598
[2] https://github.com/atishp04/qemu/tree/riscv_pmu_v1
[3] https://github.com/atishp04/opensbi/tree/riscv_pmu_v1
[4] https://github.com/atishp04/linux/tree/riscv_pmu_v1
Atish Patra (6):
RISC-V: Remove the current perf implementation
RISC-V: Add CSR encodings for a
most of the missing functionality.
Signed-off-by: Atish Patra
---
arch/riscv/Kconfig | 13 -
arch/riscv/include/asm/perf_event.h | 72 -
arch/riscv/kernel/Makefile | 1 -
arch/riscv/kernel/perf_event.c | 485
4 files changed, 571
of firmware counters that can provide
insights into firmware activity during a performance analysis.
Signed-off-by: Atish Patra
---
drivers/perf/Kconfig | 8 +
drivers/perf/Makefile | 1 +
drivers/perf/riscv_pmu.c | 12 +-
drivers/perf/riscv_pmu_sbi.c | 464
> sizeof(*mem_res);
> mem_res = memblock_alloc(mem_res_sz, SMP_CACHE_BYTES);
> if (!mem_res)
> panic("%s: Failed to allocate %zu bytes\n", __func__,
> mem_res_sz);
> --
> 2.25.1
>
>
> _______
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Thanks for catching the bug & fixing it.
Reviewed-by: Atish Patra
--
Regards,
Atish
pr_info("SBI RFENCE extension detected\n");
> } else {
> __sbi_rfence= __sbi_rfence_v01;
> }
> --
> 2.25.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Reviewed-by: Atish Patra
--
Regards,
Atish
On Tue, 2021-03-09 at 13:30 +, lewis.ha...@microchip.com wrote:
>
>
> From: Ben Dooks
> Sent: Tuesday, March 9, 2021 10:56 AM
> To: Atish Patra ; linux-kernel@vger.kernel.org <
> linux-kernel@vger.kernel.org>
> Cc: Albert Ou ; Alistair Francis <
> alis
On Mon, Mar 8, 2021 at 2:55 AM Anup Patel wrote:
>
> On Mon, Mar 8, 2021 at 1:19 PM Atish Patra wrote:
> >
> > On Sat, Mar 6, 2021 at 4:12 AM Anup Patel wrote:
> > >
> > > On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt
> > > wrote:
> > &
On Sun, Mar 7, 2021 at 11:49 PM Atish Patra wrote:
>
> On Sat, Mar 6, 2021 at 4:12 AM Anup Patel wrote:
> >
> > On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt
> > wrote:
> > >
> > > The constants in enum sbi_ext_rfence_fid should match th
On Sat, Mar 6, 2021 at 4:12 AM Anup Patel wrote:
>
> On Sat, Mar 6, 2021 at 11:19 AM Heinrich Schuchardt
> wrote:
> >
> > The constants in enum sbi_ext_rfence_fid should match the SBI
> > specification. See
> > https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc#78-function-listing
From: Conor Dooley
Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC
directory
Signed-off-by: Conor Dooley
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d92f85ca831d..cf186eca1784 100644
--- a/MAINTAINERS
+++ b/MAI
Enable Microchip PolarFire ICICLE soc config in defconfig.
It allows the default upstream kernel to boot on PolarFire ICICLE board.
Signed-off-by: Atish Patra
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/configs/defconfig | 4
1 file changed, 4 insertions(+)
diff --git a
Add Microchip PolarFire kconfig option which selects SoC specific
and common drivers that is required for this SoC.
Signed-off-by: Atish Patra
Reviewed-by: Bin Meng
Reviewed-by: Anup Patel
---
arch/riscv/Kconfig.socs | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv
Add initial DTS for Microchip ICICLE board having only
essential devices (clocks, sdhci, ethernet, serial, etc).
The device tree is based on the U-Boot patch.
https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.beg...@microchip.com/
Signed-off-by: Atish Patra
Add YAML DT binding documentation for the Microchip PolarFire SoC.
It is documented at:
https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide
Signed-off-by: Atish Patra
---
.../devicetree/bindings/riscv/microchip.yaml | 27 +++
1 file changed, 27
the DT to match the device tree in U-Boot.
2. Added both eMMC & SDcard entries in DT. However, SD card is only enabled
as it allows larger storage option for linux distros.
Atish Patra (4):
RISC-V: Add Microchip PolarFire SoC kconfig option
dt-bindings: riscv: microchip: Add YAML document
wer_off = sbi_srst_power_off;
> + sbi_srst_reboot_nb.notifier_call = sbi_srst_reboot;
> + sbi_srst_reboot_nb.priority = 192;
> + register_restart_handler(&sbi_srst_reboot_nb);
> + }
> } else {
> __sbi_set_timer = __sbi_set_timer_v01;
> __sbi_send_ipi = __sbi_send_ipi_v01;
> --
> 2.25.1
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Reviewed-by: Atish Patra
--
Regards,
Atish
On Mon, Feb 22, 2021 at 5:52 PM Palmer Dabbelt wrote:
>
> On Mon, 22 Feb 2021 14:38:28 PST (-0800), ati...@atishpatra.org wrote:
> > On Mon, Feb 22, 2021 at 12:23 PM Guenter Roeck wrote:
> >>
> >> On Wed, Feb 03, 2021 at 09:26:43PM -0800, Atish Patra wrote:
> &
On Mon, Feb 22, 2021 at 12:23 PM Guenter Roeck wrote:
>
> On Wed, Feb 03, 2021 at 09:26:43PM -0800, Atish Patra wrote:
> > SBI v0.2 functions can return an error code from SBI implementation.
> > We are already processing the SBI error code and coverts it to the Li
On Sat, Feb 6, 2021 at 2:02 AM Heinrich Schuchardt wrote:
>
> * Mention RISC-V.
> * Update code references.
> * initrd= does not specify a path relative on the ESP but to the partition
> from which the EFI stub was loaded (as specified in the loaded image
> protocol).
> * Mention that ACPI tab
SBI RESET extension allows OS to initiate a system wide reboot or shutdown.
Implement the SBI RESET extension so that guests can issue shutdown/reset
requests as well.
Signed-off-by: Atish Patra
---
arch/riscv/include/asm/kvm_vcpu_sbi.h | 1 +
arch/riscv/kvm/vcpu_sbi.c | 17
the guest OS doesn't implement HSM
extension, only single vcpu will be available to OS.
Signed-off-by: Atish Patra
---
arch/riscv/include/asm/sbi.h | 1 +
arch/riscv/kvm/Makefile | 2 +-
arch/riscv/kvm/vcpu.c | 19 ++
arch/riscv/kvm/vcpu_sbi.c | 4 ++
arch/risc
SBI v0.2 base extension defined to allow backward compatibility and
probing of future extensions. This is also the only mandatory SBI
extension that must be implemented by SBI implementors.
Signed-off-by: Atish Patra
---
arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 +
arch/riscv/include/asm/sbi.h
.
Signed-off-by: Atish Patra
---
arch/riscv/include/asm/kvm_vcpu_sbi.h | 1 +
arch/riscv/kvm/Makefile | 2 +-
arch/riscv/kvm/vcpu_sbi.c | 126 +
arch/riscv/kvm/vcpu_sbi_legacy.c | 129 ++
4 files changed, 136
The SBI v0.2 contains some of the improved versions of required v0.1
extensions such as remote fence, timer and IPI.
This patch implements those extensions.
Signed-off-by: Atish Patra
---
arch/riscv/kvm/Makefile | 2 +-
arch/riscv/kvm/vcpu_sbi.c | 6 ++
arch/riscv/kvm
ith Rocket core design.
[1] https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
[2] http://lists.infradead.org/pipermail/linux-riscv/2021-January/004251.html
Atish Patra (6):
RISC-V: Mark the existing SBI v0.1 implementation as legacy
RISC-V: Reorganize SBI code by moving legacy SBI
The existing SBI specification impelementation follows v0.1 or legacy
specification. The latest specification known as v0.2 allows more
scalability and performance improvements.
Rename the existing implementation as legacy and provide a way to allow
future extensions.
Signed-off-by: Atish Patra
SBI v0.2 functions can return an error code from SBI implementation.
We are already processing the SBI error code and coverts it to the Linux
error code.
Propagate to the error code to the caller as well. As of now, kvm is the
only user of these error codes.
Signed-off-by: Atish Patra
---
arch
GENERIC_ARCH_NUMA
> select OF_NUMA
> select ARCH_SUPPORTS_NUMA_BALANCING
> --
> 2.26.2
>
>
> ___
> linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Reviewed-by: Atish Patra
--
Regards,
Atish
linux-riscv mailing list
> linux-ri...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Reviewed-by: Atish Patra
--
Regards,
Atish
From: Sebastien Van Cauwenberghe
Allows the sections to be aligned on smaller boundaries and
therefore results in a smaller kernel image size.
Signed-off-by: Sebastien Van Cauwenberghe
Reviewed-by: Atish Patra
---
arch/riscv/include/asm/set_memory.h | 6 +++---
1 file changed, 3 insertions
64
2, MAXPHYSMEM_2GB & RV32
Fixes: e557793799c5 ("RISC-V: Fix maximum allowed phsyical memory for RV32")
Fix this by restricting MAXPHYSMEM_1GB for RV32 and MAXPHYSMEM_2GB only for
RV64.
Reported-by: Randy Dunlap
Acked-by: Randy Dunlap
Tested-by: Geert Uytterhoeven
Signed-off-by: Atis
Signed-off-by: Atish Patra
---
arch/riscv/kernel/setup.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
index 3fa3f26dde85..c7c0655dd45b 100644
--- a/arch/riscv/kernel/setup.c
+++ b/arch/riscv/kernel/setup.c
@@ -29
g is defined
> here
> 435 | pr_info("Faking a node at [mem %#018Lx-%#018Lx]\n", start,
> end - 1);
>
> Fixes: ae3c107cd8be ("numa: Move numa implementation to common code")
> Signed-off-by: Randy Dunlap
> Reported-by: kernel test robot
> Cc: Atish Patra
On Wed, Jan 27, 2021 at 7:18 PM Randy Dunlap wrote:
>
> Hi,
>
> I took a riscv-32 .config from kernel test robot (it was for a clang build)
> and did a "make olddefconfig" (using gcc tools) and got build errors
> due to this config item from arch/riscv/Kconfig;
>
>
> config PAGE_OFFSET
> h
On Thu, Jan 14, 2021 at 11:59 PM Geert Uytterhoeven
wrote:
>
> Hi Atish,
>
> On Thu, Jan 14, 2021 at 10:11 PM Atish Patra wrote:
> > On Thu, Jan 14, 2021 at 11:46 AM Palmer Dabbelt wrote:
> > > On Thu, 14 Jan 2021 10:33:01 PST (-0800), ati...@atishpatra.org wrote:
&
On Thu, Jan 14, 2021 at 11:46 AM Palmer Dabbelt wrote:
>
> On Thu, 14 Jan 2021 10:33:01 PST (-0800), ati...@atishpatra.org wrote:
> > On Wed, Jan 13, 2021 at 9:10 PM Palmer Dabbelt wrote:
> >>
> >> On Thu, 07 Jan 2021 01:26:51 PST (-0800), Atish Patra wrote:
> &g
On Wed, Jan 13, 2021 at 9:10 PM Palmer Dabbelt wrote:
>
> On Thu, 07 Jan 2021 01:26:51 PST (-0800), Atish Patra wrote:
> > SMP_CACHE_BYTES/L1_CACHE_BYTES should be defined as 32 instead of
> > 64 for RV32. Otherwise, there will be hole of 32 bytes with each memblock
>
On Mon, Jan 11, 2021 at 6:38 PM wrote:
>
> From: Guo Ren
>
> PAGE_KERNEL_EXEC has been defined above.
>
> Signed-off-by: Guo Ren
> Cc: Palmer Dabbelt
> Cc: Pekka Enberg
> ---
> arch/riscv/include/asm/pgtable.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/pgta
On Mon, 2021-01-11 at 15:13 -0800, Jakub Kicinski wrote:
> On Mon, 11 Jan 2021 11:55:53 -0800 Atish Patra wrote:
> > There is no usrio config defined for default gem config leading to
> > a kernel panic devices that don't define a data. This issue can be
> > reprdouced
generic kernel issue where kernel pointers can not use
last 4k of addressable memory. I am open to other better alternate
suggestions.
Changes from v1->v2:
1. Added Reviewed/Tested by tags.
2. Replaced PHYS_ADDR_MAX with explicit __pa(~(ulong)0).
Atish Patra (4):
RISC-V: Do not allocate membl
technically valid.
Fix this issue by limiting the memblock if available memory spans the
entire address space.
Reviewed-by: Anup Patel
Signed-off-by: Atish Patra
---
arch/riscv/mm/init.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/mm/init.c
to allow 2GB physical address space.
Reviewed-by: Anup Patel
Signed-off-by: Atish Patra
---
arch/riscv/Kconfig | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 81b76d44725d..e9e2c1f0a690 100644
--- a/arch/riscv/Kconfig
+++ b
SMP_CACHE_BYTES/L1_CACHE_BYTES should be defined as 32 instead of
64 for RV32. Otherwise, there will be hole of 32 bytes with each memblock
allocation if it is requested to be aligned with SMP_CACHE_BYTES.
Reviewed-by: Anup Patel
Tested-by: Geert Uytterhoeven
(on vexriscv)
Signed-off-by: Atish
not going through memblock allocation code every time.
Fixes: 00ab027a3b82 ("RISC-V: Add kernel image sections to the resource tree")
Reviewed-by: Anup Patel
Tested-by: Geert Uytterhoeven
Signed-off-by: Atish Patra
---
arch/riscv/kernel/setup.c | 24 +---
1 file c
atform configuration")
Signed-off-by: Atish Patra
---
drivers/net/ethernet/cadence/macb_main.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/cadence/macb_main.c
b/drivers/net/ethernet/cadence/macb_main.c
index 814a5b10141d..47ee72ab7002 100644
--- a/drivers/net/ethernet/
On Sat, Jan 9, 2021 at 12:51 PM Palmer Dabbelt wrote:
>
> On Sun, 13 Dec 2020 17:02:19 PST (-0800), ati...@atishpatra.org wrote:
> > On Wed, Nov 18, 2020 at 4:39 PM Atish Patra wrote:
> >>
> >> This series attempts to move the ARM64 numa implementation to commo
On Sun, Jan 10, 2021 at 7:59 PM Anup Patel wrote:
>
> On Thu, Jan 7, 2021 at 2:57 PM Atish Patra wrote:
> >
> > Currently, linux kernel can not use last 4k bytes of addressable space
> > because
> > IS_ERR_VALUE macro treats those as an error. This will be an issu
On Thu, 2021-01-07 at 11:34 +, daire.mcnam...@microchip.com wrote:
> From: Daire McNamara
>
> This patchset adds support for the Microchip PolarFire clkcfg
> hardware block.
>
> Major changes since v1:
> * Dependency on SOC_MICROCHIP_POLARFIRE
Does the sdcard work for with latest kernel ?
On Thu, Jan 7, 2021 at 3:44 AM wrote:
>
> Hi Atish,
>
> On 12/4/20 8:58 AM, Atish Patra wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > Add initial DTS for Microchip ICICLE board having only
On Thu, Jan 7, 2021 at 3:40 AM wrote:
>
> Hi Atish,
>
> On 12/4/20 8:58 AM, Atish Patra wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> > content is safe
> >
> > Add Microchip PolarFire kconfig option which selects SoC
to allow 2GB physical address space.
Signed-off-by: Atish Patra
---
arch/riscv/Kconfig | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 81b76d44725d..e9e2c1f0a690 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
SMP_CACHE_BYTES/L1_CACHE_BYTES should be defined as 32 instead of
64 for RV32. Otherwise, there will be hole of 32 bytes with each memblock
allocation if it is requested to be aligned with SMP_CACHE_BYTES.
Signed-off-by: Atish Patra
---
arch/riscv/include/asm/cache.h | 4
1 file changed, 4
technically
valid.
Fix this issue by limiting the memblock if available memory spans the entire
address space.
Signed-off-by: Atish Patra
---
arch/riscv/mm/init.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
generic kernel issue where kernel pointers can not use
last 4k of addressable memory. I am open to other better alternate
suggestions.
Atish Patra (4):
RISC-V: Do not allocate memblock while iterating reserved memblocks
RISC-V: Set current memblock limit
RISC-V: Fix L1_CACHE_BYTES for RV32
RISC-V
not going through memblock allocation code every time.
Fixes: 00ab027a3b82 ("RISC-V: Add kernel image sections to the resource tree")
Signed-off-by: Atish Patra
---
arch/riscv/kernel/setup.c | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/
a0 <+22>:addisp,sp,16
>0xffe0002081a2 <+24>:ret
>
> (gdb) frame 5
> (rec=0xffe01ae40c30, enable=3) at kernel/trace/ftrace.c:2503
> 2503return ftrace_make_call(rec, ftrace_addr);
> (gdb) p /x rec->ip
> $2 = 0xffe0002081
On Mon, Dec 21, 2020 at 7:19 PM Palmer Dabbelt wrote:
>
> On Fri, 04 Dec 2020 00:58:30 PST (-0800), Atish Patra wrote:
> > This series adds minimal support for Microchip Polar Fire Soc Icicle kit.
> > It is rebased on v5.10-rc6 and depends on clock support.
> > Only MMC
nable LOCKDEP_SUPPORT & fixup
TRACE_IRQFLAGS_SUPPORT")
Cc: sta...@vger.kernel.org
Signed-off-by: Atish Patra
---
arch/riscv/kernel/entry.S | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 524d918f3601..7dea5
: Bin Meng
Tested-by: Bin Meng
Acked-by: Mike Rapoport
Signed-off-by: Atish Patra
---
Changes from v1->v2:
1. Added stable-kernel in cc.
2. Added reported/tested by tag.
---
arch/riscv/mm/init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/mm/init.c b/arch/ri
On Thu, Dec 17, 2020 at 12:33 AM Atish Patra wrote:
>
> On Wed, Dec 16, 2020 at 10:51 PM Palmer Dabbelt wrote:
> >
> > On Tue, 15 Dec 2020 22:02:54 PST (-0800), Palmer Dabbelt wrote:
> > > On Wed, 04 Nov 2020 16:04:37 PST (-0800), Atish Patra wrote:
> > &
On Thu, Dec 17, 2020 at 12:53 AM Bin Meng wrote:
>
> Hi Atish,
>
> On Thu, Dec 17, 2020 at 4:43 PM Atish Patra wrote:
> >
> > On Thu, Dec 17, 2020 at 12:12 AM Bin Meng wrote:
> > >
> > > Hi Atish,
> > >
>
On Thu, Dec 17, 2020 at 12:12 AM Bin Meng wrote:
>
> Hi Atish,
>
> On Thu, Dec 17, 2020 at 3:49 PM Atish Patra wrote:
> >
> > memblock_enforce_memory_limit accepts the maximum memory size not the last
> > address. Fix the function invocation correctly.
> &
On Wed, Dec 16, 2020 at 10:51 PM Palmer Dabbelt wrote:
>
> On Tue, 15 Dec 2020 22:02:54 PST (-0800), Palmer Dabbelt wrote:
> > On Wed, 04 Nov 2020 16:04:37 PST (-0800), Atish Patra wrote:
> >> In order to improve kernel text protection, we need separate .init.text/
>
memblock_enforce_memory_limit accepts the maximum memory size not the last
address. Fix the function invocation correctly.
Fixes: 1bd14a66ee52 ("RISC-V: Remove any memblock representing unusable memory
area")
Signed-off-by: Atish Patra
---
arch/riscv/mm/init.c | 2 +-
1 file
On Wed, Nov 18, 2020 at 4:39 PM Atish Patra wrote:
>
> This series attempts to move the ARM64 numa implementation to common
> code so that RISC-V can leverage that as well instead of reimplementing
> it again.
>
> RISC-V specific bits are based on initial work done by Gr
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