Hi Marc,
> On 10/9/19 6:01 AM, Appana Durga Kedareswara Rao wrote:
> > Hi,
> >
> >
> >> On 18.3.2019 13.32, Appana Durga Kedareswara rao wrote:
> >>> AXI CAN IP and CANPS IP supports tx fifo empty feature, this patch
> >>> updates the flags
AXI CANIP doesn't support tx fifo empty interrupt feature(TXFEMP),
update the flags filed in the driver for AXI CAN case accordingly.
Fixes: 3281b380ec9f ("can: xilinx_can: Fix flags field initialization for axi
can and canps")
Reported-by: Anssi Hannula
Signed-off-by: Appana Du
Hi,
> On 18.3.2019 13.32, Appana Durga Kedareswara rao wrote:
> > AXI CAN IP and CANPS IP supports tx fifo empty feature, this patch
> > updates the flags field for the same.
> >
> > Signed-off-by: Appana Durga Kedareswara rao
> >
> > ---
> > dr
Hi Alan,
Did you get a chance to send your framework changes to upstream?
@Moritz Fischer: If Alan couldn't send his patch series, Can we take this patch
series??
Please let me know your thoughts on this.
Regards,
Kedar.
> On Fri, Jul 27, 2018 at 1:22 AM, Appana Durga Kedareswara rao
n the case of deferred probe.
Fixes: b1201e44 ("can: xilinx CAN controller support")
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Venkatesh Yadav Abbarapu
Signed-off-by: Michal Simek
---
drivers/net/can/xilinx_can.c | 3 ++-
1 file changed, 2 insertions(+), 1 delet
ti Datta
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Michal Simek
---
drivers/net/can/xilinx_can.c | 29 -
1 file changed, 8 insertions(+), 21 deletions(-)
diff --git a/drivers/net/can/xilinx_can.c b/drivers/net/can/xilinx_can.c
index 2d3399e..c9b951b
From: Srinivas Neeli
While calculating bitrate for the data phase, the driver is using phase
segment 1 of the arbitration phase instead of the data phase.
Fixes: c223da6 ("can: xilinx_can: Add support for CANFD FD frames")
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by
For CANFD 2.0 IP configuration existing driver is using incorrect mask
values for FSR register FL and RI fields.
Fixes: c223da6 ("can: xilinx_can: Add support for CANFD FD frames")
Signed-off-by: Appana Durga Kedareswara rao
Acked-by: Shubhrajyoti Datta
Signed-off-by: Michal Simek
--
essary fsr register checks in
xcanfd_rx() API.
Fixes: c223da6 ("can: xilinx_can: Add support for CANFD FD frames")
Reviewed-by: Radhey Shyam Pandey
Reviewed-by: Shubhrajyoti Datta
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Michal Simek
---
drivers/net/ca
g in the commit description
Appana Durga Kedareswara rao (3):
can: xilinx_can: Fix FSR register handling in the rx path
can: xilinx_can: Fix the data updation logic for CANFD FD frames
can: xilinx_can: Fix FSR register FL and RI mask values for canfd 2.0
Srinivas Neeli (1):
can: xilinx_can: Fix
Hi Marc,
Thanks for the review.
> On 8/12/19 9:28 AM, Appana Durga Kedareswara rao wrote:
> > This patch series fixes below issues
> > --> Bugs in the driver w.r.to CANFD 2.0 IP support Defer the probe if
> > --> clock is not found
> >
> > Appa
Hi Marc,
Thanks for the review...
> On 8/12/19 9:28 AM, Appana Durga Kedareswara rao wrote:
> > From: Venkatesh Yadav Abbarapu
> >
> > It's not always the case that clock is already available when can
> > driver get probed at the first time, e.g. the clock
From: Venkatesh Yadav Abbarapu
It's not always the case that clock is already available when can
driver get probed at the first time, e.g. the clock is provided by
clock wizard which may be probed after can driver. So let's defer
the probe when devm_clk_get() call fails and give it chance to
try
commit c223da689324 ("can: xilinx_can: Add support for CANFD FD frames")
is writing data to a wrong offset for FD frames.
This patch fixes this issue.
Reviewed-by: Radhey Shyam Pandey
Reviewed-by: Shubhrajyoti Datta
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Mi
essary fsr register checks in
xcanfd_rx() API.
Reviewed-by: Radhey Shyam Pandey
Reviewed-by: Shubhrajyoti Datta
Signed-off-by: Appana Durga Kedareswara rao
Signed-off-by: Michal Simek
---
drivers/net/can/xilinx_can.c | 139 ---
1 file changed, 63 inserti
From: Srinivas Neeli
While calculating bitrate for the data phase, the driver is using phase
segment 1 of the arbitration phase instead of the data phase.
Signed-off-by: Srinivas Neeli
Acked-by: Shubhrajyoti Datta
Signed-off-by: Michal Simek
---
drivers/net/can/xilinx_can.c | 2 +-
1 file ch
For CANFD 2.0 IP configuration existing driver is using incorrect mask
values for FSR register FL and RI fields.
Signed-off-by: Appana Durga Kedareswara rao
Acked-by: Shubhrajyoti Datta
Signed-off-by: Michal Simek
---
drivers/net/can/xilinx_can.c | 13 ++---
1 file changed, 10
This patch series fixes below issues
--> Bugs in the driver w.r.to CANFD 2.0 IP support
--> Defer the probe if clock is not found
Appana Durga Kedareswara rao (3):
can: xilinx_can: Fix FSR register handling in the rx path
can: xilinx_can: Fix the data updation logic for CANFD FD frames
Hi Marc,
Friendly ping !!
> -Original Message-
> From: Appana Durga Kedareswara Rao
> Sent: Tuesday, April 23, 2019 12:08 PM
> To: 'Marc Kleine-Budde' ; 'w...@grandegger.com'
> ; 'da...@davemloft.net' ;
> Michal Simek
> Cc:
Hi Andre,
>
> On 3/9/19 3:07 PM, Appana Durga Kedareswara rao wrote:
> > While stress testing the CAN interface on xilinx axi can in loopback
> > mode getting message "write: no buffer space available"
> > Increasing device tx queue length resolved the abov
While stress testing the CAN interface on xilinx axi can
in loopback mode getting message "write: no buffer space available"
Increasing device tx queue length resolved the above mentioned issue.
Signed-off-by: Appana Durga Kedareswara rao
---
--> Network devices default tx_queue_le
> -Original Message-
> From: Radhey Shyam Pandey
> Sent: Saturday, September 29, 2018 10:48 PM
> To: vk...@kernel.org; dan.j.willi...@intel.com; Michal Simek
> ; Appana Durga Kedareswara Rao
> ; Radhey Shyam Pandey
> Cc: dmaeng...@vger.kernel.org; linux-arm-ker..
ndey
Reviewed-by: Appana Durga Kedareswara Rao
Regards,
Kedar.
> ---
> Changes for v2:
> New patch- Preparatory change for 4/4 fix.
> ---
> drivers/dma/xilinx/xilinx_dma.c |2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/dma/xilinx/xili
Hi,
Thanks for the patch...
>
> In axidma alloc_chan_resources merge BD and cyclic BD allocation.
>
> Signed-off-by: Radhey Shyam Pandey
> Signed-off-by: Michal Simek
Acked-for-series: Appana Durga Kedareswara rao
Regards,
Kedar.
> ---
> drivers/dma/xilin
Hi Alan,
Thanks for the review...
> On Fri, Jul 27, 2018 at 1:22 AM, Appana Durga Kedareswara rao
> wrote:
>
> Hi Appana,
>
> There should be some documentation for the debugfs added under
> Documentation/driver-api/fpga/
>
> Also there are a lot of #if
Inorder to debug issues with fpga's users would
like to read the fpga configuration information.
This patch adds readback support for fpga configuration data
in the framework through debugfs interface.
Usage:
cat /sys/kernel/debug/fpga/fpga0/image
Signed-off-by: Appana Durga Kedare
This patch adds support for readback of FPGA configuration data and registers.
Usage:
Readback of PL configuration data
cat /sys/kernel/debug/fpga/fpga0/image
Readback of PL configuration registers
cat /sys/kernel/debug/fpga/f8007000.devcfg/cfg_reg
Signed-off-by: Appana Durga
Hi Alan,
Thanks for the review...
> > In Zynq Case it supports two types of the readback (Configuration registers,
> Configuration data(fpga image)) which may not be the same case for other
> vendors.
> > Since I need to support both the use cases I have differentiated them using
> modu
Hi Alan,
Thanks for the review...
> Another minor thing.
>
> > +
> >
> +/**
> **
> > +/
>
> Let's keep the coding style consistent by not having
Sure will fix in v4...
> '***'
>
> > +/**
Hi Alan,
Thanks for the review...
> >
> >
> >> > +static bool readback_type;
> >> > +module_param(readback_type, bool, 0644);
> >> > +MODULE_PARM_DESC(readback_type,
> >> > + "readback_type 0-configuration register read "
> >> > + "1- configuration d
Hi Moritz,
Thanks for the review...
> Can you please make the commit message such that you have full sentences?
>
> "Add support for readback of FPGA configuration data and registers" of
> example.
Sure will fix in v4.
>
> >
> > Usage:
> > Readback of PL configuration registers
> >
ys/module/zynqmp_fpga/parameters/readback_type
cat /sys/kernel/debug/fpga/fpga0/image
Signed-off-by: Appana Durga Kedareswara rao
---
Changes for v3:
--> Added support for pl configuration data readback
--> Improved the pl configuration register readback logic.
Changes for v2:
-->
Inorder to debug issues with fpga's users would
like to read the fpga configuration information.
This patch adds readback support for fpga configuration data
in the framework through debugfs interface.
Usage:
cat /sys/kernel/debug/fpga/fpga0/image
Signed-off-by: Appana Durga Kedare
This patch adds support for Read-back of
configuration registers in zynq.
Signed-off-by: Appana Durga Kedareswara rao
---
Changes for v2:
--> Removed locks from the read ops as
lock handling is done in the framework.
drivers/fpga/zynq-fpga.c |
Inorder to debug issues with fpga's users would
like to read the fpga configuration information.
This patch adds readback support for fpga configuration data
in the framework through debugfs interface.
Usage:
cat /sys/kernel/debug/fpga/fpga0/image
Signed-off-by: Appana Durga Kedare
fpga manager, not one entry for the whole
> framework, so
>
> cat /sys/kernel/debug/fpga/fpga0/image
Sure will fix in v2...
>
> >
> > Signed-off-by: Appana Durga Kedareswara rao
> >
> > ---
> > drivers/fpga/fpga-mgr.c | 52
>
This patch adds support for Read-back of
configuration registers in zynq.
Signed-off-by: Appana Durga Kedareswara rao
---
drivers/fpga/zynq-fpga.c | 254 +++
1 file changed, 254 insertions(+)
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq
Inorder to debug issues with fpga's users would
like to read the fpga configuration information.
This patch adds readback support for fpga configuration data
in the framework through debugfs interface.
Usage:
cat /sys/kernel/debug/fpga/readback
Signed-off-by: Appana Durga Kedareswar
>
> The AXI VDMA core supports Vertical flip in S2MM path when Enable Vertical
> Flip (Advanced tab) is selected. To allow vertical flip programming define an
> optional 'xlnx,enable-vert-flip' channel child node property.
>
> Signed-off-by: Radhey Shyam Pandey
> Signed-off-by: Michal Simek
>
> Vertical flip state is exported in xilinx_vdma_config and depending on IP
> configuration(c_enable_vert_flip) vertical flip state is programmed in
> hardware.
>
> Signed-off-by: Radhey Shyam Pandey
> Signed-off-by: Michal Simek
Acked-by: Kedareswara rao Appana
> ---
> drivers/dma/x
Hi,
Thanks for the review...
>On Tue, Jan 09, 2018 at 04:48:10AM +0000, Appana Durga Kedareswara Rao
>wrote:
>> Hi,
>>
>> >On Mon, Jan 08, 2018 at 05:25:01PM +0000, Appana Durga Kedareswara
>> >Rao
>> >wrote:
>> >> Hi,
>&g
Hi,
>On Mon, Jan 08, 2018 at 05:25:01PM +0000, Appana Durga Kedareswara Rao
>wrote:
>> Hi,
>>
>>
>> >> >> + xdev->common.dst_addr_widths = BIT(addr_width / 8);
>> >> >> + xdev->common.src_addr_widths = BIT(addr_width /
Hi,
>> >> + xdev->common.dst_addr_widths = BIT(addr_width / 8);
>> >> + xdev->common.src_addr_widths = BIT(addr_width / 8);
>> >
>> >Do you not support trf of 1byte, 2 bytes, or 4 bytes wide transfers?
>> >What is value of addr_width here typically? Usually controllers can
>> >support different w
Hi Vinod,
Thanks for the review
>> @@ -2398,6 +2398,7 @@ static int xilinx_dma_chan_probe(struct
>xilinx_dma_device *xdev,
>> chan->direction = DMA_MEM_TO_DEV;
>> chan->id = chan_id;
>> chan->tdest = chan_id;
>> +xdev->common.directi
Hi,
>>> >BTW whats with LINUX tag in patches, pls drop them
>>>
>>> Ok will mention the Linux tag info in the cover letter patch from the
>>> next patch series on wards...
>>
>>Please wrap your replies within 80chars. It is very hard to read! I have
>>reflown
>for
>>readability
>
>Sure will take
Hi Vinod,
>On Wed, Jan 03, 2018 at 05:13:29AM +0000, Appana Durga Kedareswara Rao
>wrote:
>> Hi Vinod,
>>
>> Thanks for the review...
>>
>> >
>> >On Thu, Dec 21, 2017 at 03:41:37PM +0530, Kedareswara rao Appana wrote:
>> >
>> &
Hi Vinod,
Thanks for the review...
>
>On Thu, Dec 21, 2017 at 03:41:37PM +0530, Kedareswara rao Appana wrote:
>
>Fix title here too
Sure will fix in v2...
>
>BTW whats with LINUX tag in patches, pls drop them
Ok will mention the Linux tag info in the cover letter patch from the next
Hi Vinod,
Thanks for the review...
>
>On Thu, Dec 21, 2017 at 03:41:36PM +0530, Kedareswara rao Appana wrote:
>
>same issue for patch title here too
Ok will fix in v2...
>
>> when hardware is idle we need to toggle the SG bit in the control
>> register, inorder to update new value to
Hi Vinod,
Thanks for the review...
>
>On Thu, Dec 21, 2017 at 03:41:35PM +0530, Kedareswara rao Appana wrote:
>
>Patch title should say what is does, not the cause/effect
Sure will fix in v2...
>
>An apt title might be "populate dma caps properly"
>
>> When client driver uses dma_get_s
Hi,
Thanks for the review...
>
>On Thu, Dec 07, 2017 at 10:51:02AM +0530, Kedareswara rao Appana wrote:
>
>> @@ -2029,6 +2006,7 @@ static int xilinx_dma_terminate_all(struct
>> dma_chan *dchan)
>>
>> /* Remove and free all of the descriptors in the lists */
>> xilinx_dma_free_d
Hi Vinod,
>
>On Thu, Dec 07, 2017 at 10:51:01AM +0530, Kedareswara rao Appana wrote:
>> This patch series fixes below bugs in DMA and VDMA IP's
>> ---> Added channel idle checks in the driver before submitting the buffer
>descriptor to h/w.
>> ---> Fixes bug in Multi frame sotres handling in VDMA
Hi Mike Looijmans,
Thanks for the review...
Sorry for the long delay in the reply...
Please find comments inline...
>On 14-01-17 06:35, Kedareswara rao Appana wrote:
>> When VDMA is configured for more than one frame in the h/w.
>> For example h/w is configured for n number of
Hi Vinod,
Thanks for the review...
[Snip]
> > > Btw how and when does DMA stop, assuming it is circular it never
> > > would, isn't there a valid/stop flag associated with a descriptor
> > > which tells DMA engine what to do next
> >
> > There are two registers that controls the D
Hi Vinod,
Thanks for the review...
[Snip]
> >
> > > On Sat, Jan 07, 2017 at 12:15:30PM +0530, Kedareswara rao Appana wrote:
> > > > When driver is handling AXI DMA SoftIP When user submits multiple
> > > > descriptors back to back on the S2MM(recv) side with the current
> > > > driver flo
Hi Vinod,
Thanks for the review...
>
> On Fri, Jan 13, 2017 at 04:28:11AM +, Appana Durga Kedareswara Rao
> wrote:
> > Hi Vinod,
> >
> > Thanks for the review...
> > >
> > > On Sat, Jan 07, 2017 at 12:15:28PM +0530, Kedareswa
Hi Vinod,
Thanks for the review...
>
> On Sat, Jan 07, 2017 at 12:15:28PM +0530, Kedareswara rao Appana wrote:
> > Add channel idle state to ensure that dma descriptor is not
> > submitted when VDMA engine is in progress.
>
> any reason why you want to make your own varible and not use t
Hi Vinod,
Thanks for the review...
>
> On Sat, Jan 07, 2017 at 12:15:29PM +0530, Kedareswara rao Appana wrote:
> > When VDMA is configured for more than one frame in the h/w for example
> > h/w is configured for n number of frames and user Submits n number of
> > frames and triggered t
Hi Vinod,
Thanks for the review...
> On Sat, Jan 07, 2017 at 12:15:30PM +0530, Kedareswara rao Appana wrote:
> > When driver is handling AXI DMA SoftIP When user submits multiple
> > descriptors back to back on the S2MM(recv) side with the current
> > driver flow the last buffer descr
Hi Rob,
Thanks for the review...
[Snip]
> > -- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> >> > +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
> >> > @@ -66,6 +66,8 @@ Optional child node properties:
> >> > Optional child node properties for VDMA:
Hi Rob,
Thanks for the review
> On Wed, Jan 04, 2017 at 07:05:53PM +0530, Kedareswara rao Appana wrote:
> > When VDMA is configured for more than one frame in the h/w for example
> > h/w is configured for n number of frames and user Submits n number of
> > frames and triggered the DMA
Hi
Thanks for the review...
>
> Hi Kedar,
>
>
> On 04-01-2017 06:54, Kedareswara rao Appana wrote:
> > When VDMA is configured for more than one frame in the h/w for example
> > h/w is configured for n number of frames and user Submits n number of
> > frames and triggered the DMA using
Hi Jose Miguel Abreu,
Thanks for the review...
> >> If so then there is no race condition, but the HW image that I have
> >> does not have this register enabled so I was getting this result
> >> (memory corruption because not all framebuffers had addresses set).
> > Thanks for the explana
Hi Jose Miguel Abreu,
Thanks for the review...
[snip]...
>
> I just noticed there is a write to XILINX_DMA_REG_FRMSTORE which, by the
> description in the VDMA databook, allows to modify the total number of
> framebuffers.
>
> Does it correct this situation: Lets assume VDMA has 10 fram
Hi Jose Miguel Abreu,
Thanks for the review
Sorry for the delay in the reply please see comments inline...
> > if (chan->has_sg) {
> > dma_ctrl_write(chan, XILINX_DMA_REG_TAILDESC,
> > tail_segment->phys);
> > + list_splice
Hi Laurent Pinchart,
Sorry for the delay in the reply.
Thanks for the review...
>
> Hi Kedar,
>
> On Monday 19 Dec 2016 15:39:43 Appana Durga Kedareswara Rao wrote:
> > Hi Laurent Pinchart,
> >
> > Thanks for the review...
>
Hi Laurent Pinchart,
Thanks for the review...
> >
> > + if (!chan->idle)
> > + return;
>
> Don't you need to perform the same check for the DMA and CDMA channels ? If
> so, shouldn't this be moved to common code ?
Will fix it in v2...
>
> There's another problem (not stric
Hi Jose Miguel Abreu,
Thanks for the review...
> >
> >>> - last = segment;
> >>> + for (j = 0; j < chan->num_frms; ) {
> >>> + list_for_each_entry(segment, &desc->segments, node)
> >> {
> >>> + if (chan->ext_addr)
> >>> +
Hi Laurent Pinchart,
Thanks for the review...
> > + int i = 0, j = 0;
> >
> > if (chan->desc_submitcount < chan->num_frms)
> > i = chan->desc_submitcount;
>
> I don't get this. i seems to index into a segment start address array, but
> gets
> in
Hi Jose Miguel Abreu,
Thanks for the review
> > - last = segment;
> > + for (j = 0; j < chan->num_frms; ) {
> > + list_for_each_entry(segment, &desc->segments, node)
> {
> > + if (chan->ext_addr)
> > +
Hi Jose Miguel Abreu,
Thanks for the review...
> > + chan->idle = true;
> >
> > spin_lock_init(&chan->lock);
> > INIT_LIST_HEAD(&chan->pending_list);
>
> I think there is missing a set to true in idle when a channel reset is
> performed.
> Otherwise: Reviewed-by: Jose Abreu
Hi Jose Abreu,
Thanks for the patch...
I have just posted different patch series for fixing these issues just
now...
Please take a look into it...
Regards,
Kedar.
> Subject: [PATCH] dmaengine: xilinx_dma: Add support for multiple buffers
>
> Xilinx VDMA supports multiple frame
Hi Jose Abreu,
Thanks for the patch...
>
> Xilinx VDMA supports multiple framebuffers. This patch adds correct handling
> for
> the scenario where multiple framebuffers are available in the HW and parking
> mode is not set.
>
> We corrected these situations:
> 1) Do not start VDM
> -Original Message-
> From: Eugeniy Paltsev [mailto:eugeniy.palt...@synopsys.com]
> Sent: Wednesday, September 14, 2016 11:11 PM
> To: dmaeng...@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org; Appana Durga Kedareswara Rao
> ; vinod.k...@intel.com; dan.j.
Hi Andrew,
Thanks for the review...
> > - mdiobus_write(phydev->mdio.bus, priv->addr,
> XILINX_GMII2RGMII_REG, val);
> > + err = mdiobus_write(phydev->mdio.bus, priv->addr,
> XILINX_GMII2RGMII_REG,
> > + val);
> > + if (err < 0)
> > + return err;
> >
Hi Andrew,
Thanks for the review...
>
> > Agree with you my intention is if there is a MDIO bus on the
> > device-tree The MAC driver should create PHY/MDIO devices using
> of_mdiobus_register().
>
> What you suggest is better, and is similar to what other drivers use.
>
> In order to
Hi Andrew,
Thanks for the review...
>
> > +static int xgmiitorgmii_read_status(struct phy_device *phydev) {
> > + struct gmii2rgmii *priv = phydev->priv;
> > + u16 val = 0;
> > +
> > + priv->phy_drv->read_status(phydev);
>
> This can return an error, in which case phydev->speed sh
Hi Andrew
>
> On Tue, Aug 16, 2016 at 11:58:29AM +0530, Kedareswara rao Appana wrote:
> > For implementing this driver most of the inputs is provided by Andrew
> > Lunn.
> >
> > Updating the driver with Andrew Copy right.
> >
> > Signed-off-by: Kedareswara rao Appana
>
> O.K, so this is a start
Hi David Miller,
Thanks for the review...
>
> From: Kedareswara rao Appana
> Date: Sat, 13 Aug 2016 15:31:49 +0530
>
> > @@ -445,7 +445,13 @@ static int macb_mii_init(struct macb *bp)
> > dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
> >
> > np = bp->pdev->dev.of_node;
> > - i
Hi Andrew,
>
> > Signed-off-by: Kedareswara rao Appana
> > ---
> > Thanks a lot Andrew for your inputs.
> > Changes for v5:
> > --> Fixed return values in the probe as suggested by punnaiah.
> > --> Added a mask for the converter speed as suggested by punnaiah.
> > +/* Xilinx GMII2RGMII Converte
Hi Florian,
Thanks for the review...
>
> On 08/09/2016 02:34 AM, Kedareswara rao Appana wrote:
> > Device-tree binding documentation for xilinx gmiitorgmii converter.
> >
> > Signed-off-by: Kedareswara rao Appana
> > ---
> > Changes for v5:
> > ---> Fixed Indentation in the example as s
Hi Florian,
Thanks for the review...
> >
> > This converter sits between the MAC and the external phy MAC <==>
> > GMII2RGMII <==> RGMII_PHY
>
> This looks good, just a few things, see below:
Thanks...
> > +config XILINX_GMII2RGMII
> > + tristate "Xilinx GMII2RGMII converter driv
Hi Punnaiah,
Thanks for the review...
> > +
> > +#define XILINX_GMII2RGMII_REG 0x10
> > +#define BMCR_SPEED10 0x00
>
> Move this macro to mii.h
Sure will fix in the next version...
>
> > +
> > +struct gmii2rgmii {
> > + struct phy_device *phy_dev;
> > + struct p
Hi Michal,
> On 8.8.2016 09:15, Kedareswara rao Appana wrote:
> > Device-tree binding documentation for xilinx gmiitorgmii converter.
> >
> > Signed-off-by: Kedareswara rao Appana
> > ---
> > Changes for v4:
> > --> Modified compatible as suggested by Rob.
> > --> Removed underscores from the con
Hi Rob,
Thanks for the review...
> > +XILINX GMIITORGMII Converter Driver Device Tree Bindings
> > +
> > +
> > +The Gigabit Media Independent Interface (GMII) to Reduced Gigabit
> > +Media Independent Interface (RGMII) core provide
Hi zhuyj,
Thanks for the review...
>
> + switch (phydev->speed) {
> + case SPEED_1000:
> + val |= BMCR_SPEED1000;
> + case SPEED_100:
> + val |= BMCR_SPEED100;
> + }
>
> Are there only 2 kinds of speed?
Converter supports 3 different
Hi Florian,
>
> On 27/07/2016 01:05, Andrew Lunn wrote:
> > Hi Appana
> >
> > Here is roughly what i was thinking:
> >
> > struct priv {
> >phy_device *master;
> >phy_device *slave;
> >struct phy_driver *slave_drv;
> > };
> >
> > phy_status_clone(phy_device *master, phy_de
Hi Andrew,
Thanks for the inputs...
> >
> > > > Hi Kedareswara
> > > >
> > > > So looking at the device tree, you have the gmiitorgmii as an mdio
> > > > device. It will get probed as an mdio device, and from that you
> > > > know the address on the bus. However, your driver does not
> >
>
> We get a warning about the missing MODULE_LICENSE tag for this newly added
> driver module:
>
> WARNING: modpost: missing MODULE_LICENSE() in
> drivers/dma/xilinx/zynqmp_dma.o see include/linux/module.h for more
> information
>
> This adds a "GPL" license, matching the "version 2 or later"
Hi Dan,
Thanks for the review...
> On Wed, Jul 13, 2016 at 04:12:16PM +0530, Kedareswara rao Appana wrote:
> > diff --git a/drivers/dma/xilinx/zynqmp_dma.c
> > b/drivers/dma/xilinx/zynqmp_dma.c index f777a5b..2248704 100644
> > --- a/drivers/dma/xilinx/zynqmp_dma.c
> > +++ b/drivers/dma/x
Hi Vinod,
Thanks for the review...
> > +
> > + chan->is_dmacoherent = of_property_read_bool(node, "dma-
> coherent");
> > + zdev->chan = chan;
> > + tasklet_init(&chan->tasklet, zynqmp_dma_do_tasklet, (ulong)chan);
>
> where is this killed?
This is killed in the zynqmp_dma_chan_r
Hi Vinod,
> On Fri, Jul 01, 2016 at 05:07:05PM +0530, Kedareswara rao Appana wrote:
> > Device-tree binding documentation for Xilinx zynqmp dma engine used in
> > Zynq UltraScale+ MPSoC.
>
> And I missed the cleanup part, so both applied now
Thanks for applying the patches will send patch for t
Hi Nicolas,
> >
> > #ifdef CONFIG_NET_VENDOR_XILINX
>
> You may need to have:
> #if defined(CONFIG_NET_VENDOR_XILINX) &&
> defined(CONFIG_XILINX_GMII2RGMII)
>
> > extern int gmii2rgmii_phyprobe(struct gmii2rgmii *xphy); #else extern
> > void gmii2rgmii_phyprobe(struct gmii2rgmii *xphy);
>
> N
Hi Nicolas,
Thanks for the review...
> > diff --git a/include/linux/xilinx_gmii2rgmii.h
> > b/include/linux/xilinx_gmii2rgmii.h
> > new file mode 100644
> > index 000..b328ee7
> > --- /dev/null
> > +++ b/include/linux/xilinx_gmii2rgmii.h
> > @@ -0,0 +1,24 @@
>
>
> Here, header of th
Hi Andrew,
> On Fri, Jul 01, 2016 at 11:50:10AM +0530, Kedareswara rao Appana wrote:
> > This patch series does the following
> > ---> Add support for gmii2rgmii converter.
>
> How generic is this gmii2rgmii IP block? Could it be used with any GMII and
> RGMII device?
This converter does GMII2RG
Hi Florian,
Thanks for the review.
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +static void xgmii2rgmii_fix_mac_speed(void *priv, unsigned int speed)
> > +{
> > + struct gmii2rgmii *xphy
Hi Florian,
Thanks for the review...
> Le 30/06/2016 23:20, Kedareswara rao Appana a écrit :
> > This patch series does the following
> > ---> Add support for gmii2rgmii converter.
> > ---> Add support for gmii2rgmii converter in the macb driver.
> >
> > Earlier sent one RFC patch https:/
Hi,
> >>> +static inline void macb_hw_fix_mac_speed(struct macb *bp,
> >>> + struct phy_device *phydev)
> >>> +{
> >>> + if (likely(bp->converter_phy.fix_mac_speed))
> >>
> >> What is the purpose of this branch bias? The code isn't in some hot
> >> path, so I suspe
Hi Nicolas Ferre,
Thanks for the quick review...
>
> Le 01/07/2016 08:20, Kedareswara rao Appana a écrit :
> > This patch adds support for gmii2rgmii phy converter in the macb
> > driver.
>
> Okay, I'd like more explanation here.
> Hints & key words:
> - dt property
> - mdio bus
Hi Vinod,
>
> On Thu, Jun 09, 2016 at 09:07:47PM +0530, Kedareswara rao Appana wrote:
>
> > + dma_set_mask(&pdev->dev, DMA_BIT_MASK(44));
> > + dma_cap_set(DMA_SG, zdev->common.cap_mask);
> > + dma_cap_set(DMA_MEMCPY, zdev->common.cap_mask);
>
> > /**
> > + * struct zynqmp_dma_config - Z
Hi Vinod,
> > > > > > > /**
> > > > > > > + * struct xilinx_mcdma_config - DMA Multi channel
> > > > > > > +configuration structure
> > > > > > > + * @tdest: Channel to operate on
> > > > > > > + * @tid: Channel configuration
> > > > > > > + * @tuser: Tuser configuration
> > > > > >
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