using the Coccinelle software.
>
> Signed-off-by: Markus Elfring
Acked-by: Andrew Bresticker
> ---
> drivers/pinctrl/pinctrl-pistachio.c | 19 ++-
> 1 file changed, 10 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-pistachio.c
>
gned-off-by: Alexandre Courbot
Acked-by: Andrew Bresticker
> ---
> arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
> b/arch/arm64/boot/dts/nvidia/tegra210-sma
> +Required properties:
> +
> +- compatible: Must be:
> + - Tegra124: "nvidia,tegra124-xusb-padctl"
> + - Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
> +- reg: Physical base address and length of the controller's registers.
> +- resets: Must contain
On Fri, Mar 4, 2016 at 8:19 AM, Thierry Reding wrote:
> From: Thierry Reding
>
> Extend the binding to cover the set of feature found in Tegra210.
>
> Signed-off-by: Thierry Reding
> +PCIe pad:
> +-
> +
> +Required properties:
> +- clocks: Must contain an entry for each entry in clock-n
Hi Thierry,
On Fri, Mar 4, 2016 at 8:19 AM, Thierry Reding wrote:
> From: Thierry Reding
>
> The NVIDIA Tegra XUSB pad controller provides a set of pads, each with a
> set of lanes that are used for PCIe, SATA and USB.
>
> Signed-off-by: Thierry Reding
Thanks, this binding looks much better, I
Hi Martyn,
On Mon, Nov 2, 2015 at 3:55 AM, Martyn Welch
wrote:
> This series is based on commits that can be found in the git tree here:
>
> https://github.com/thierryreding/linux/commits/staging/xhci
>
> I have included the patches I've used from that tree as patches 1-5.
>
> The above patches w
Hi Fabio,
On Sun, Nov 1, 2015 at 5:55 AM, Fabio Estevam wrote:
> Hi Andrew,
>
> On Mon, Mar 30, 2015 at 1:56 AM, Andrew Bresticker
> wrote:
>
>>> I'd rather we have it defined explicitly in the binding, i.e. make it a
>>> required property?
>>
>&
>
> -__clk_get_name(E->clk)
> +clk_hw_get_name(E)
>
> Cc: Heiko Stuebner
> Cc: Sylwester Nawrocki
> Cc: Tomasz Figa
> Cc: Peter De Schrijver
> Cc: Prashant Gaikwad
> Cc: Stephen Warren
> Cc: Thierry Reding
> Cc: Alexandre Courbot
> Cc: Tero Kristo
>
Hi Roger,
On Wed, Jul 15, 2015 at 6:26 AM, Roger Quadros wrote:
> Hi Andrew,
>
> On 13/07/15 22:14, Andrew Bresticker wrote:
>> Hi Roger,
>>
>> On Wed, Jul 8, 2015 at 3:19 AM, Roger Quadros wrote:
>>> Usage model:
>>> ---
>>>
>&
Hi Peter,
On Mon, Jul 13, 2015 at 5:59 PM, Peter Chen wrote:
> On Mon, Jul 13, 2015 at 12:14:43PM -0700, Andrew Bresticker wrote:
>> Hi Roger,
>>
>> On Wed, Jul 8, 2015 at 3:19 AM, Roger Quadros wrote:
>> > Usage model:
>> > ---
>> >
>&
ink
> error instead of calling a random platform's implementation.
>
> Signed-off-by: Bjorn Helgaas
> CC: Andrew Bresticker
Reviewed-by: Andrew Bresticker
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Hi Roger,
On Wed, Jul 8, 2015 at 3:19 AM, Roger Quadros wrote:
> Usage model:
> ---
>
> - The OTG controller device is assumed to be the parent of
> the host and gadget controller. It must call usb_otg_register()
> before populating the host and gadget devices so that the OTG
> core is aw
On Wed, Jun 3, 2015 at 8:44 AM, Andrew Bresticker wrote:
> On Tue, Jun 2, 2015 at 11:07 PM, Kishon Vijay Abraham I wrote:
>>
>>
>> On Monday 11 May 2015 08:15 PM, Kishon Vijay Abraham I wrote:
>>>
>>>
>>>
>>> On Tuesday 05 May
On Tue, Jun 2, 2015 at 11:07 PM, Kishon Vijay Abraham I wrote:
>
>
> On Monday 11 May 2015 08:15 PM, Kishon Vijay Abraham I wrote:
>>
>>
>>
>> On Tuesday 05 May 2015 11:43 PM, Ezequiel Garcia wrote:
>>>
>>> Hi Kishon,
>>>
This series adds support for the USB2.0 PHY present on the IMG Pis
Hi Mathias,
On Mon, May 25, 2015 at 8:05 AM, Mathias Nyman
wrote:
>
> I've been testing add/remove HCD extensively and didn't observe any
> issues after applying
> these 5 patches. Well there is one issue that comes up but it has nothing
> to do with xhci
> not being all
Hi Jassi,
On Mon, May 11, 2015 at 8:56 PM, Jassi Brar wrote:
> Applied patches 2, 3, 6 & 7
Please drop patches 6 and 7. Lee Jones has NAK'ed the MFD driver, so
I'll have to re-spin this series without using an MFD.
Thanks,
andrew
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On Fri, May 22, 2015 at 10:52 AM, Ezequiel Garcia
wrote:
>
>
> On 05/22/2015 02:42 PM, Andrew Bresticker wrote:
>> On Thu, May 21, 2015 at 4:57 PM, Ezequiel Garcia
>> wrote:
>>> This commit passes CLK_SET_RATE_PARENT to the "mips_div",
>>> &qu
message could be more descriptive, e.g. explaining which
additional clocks must be enabled at all times and why, especially
since forcing on clocks form the clock driver is very much frowned
upon unless absolutely necessary. Otherwise,
Reviewed-by: Andrew Bresticker
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: Kevin Cernekee
> Signed-off-by: Ezequiel Garcia
Reviewed-by: Andrew Bresticker
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Please read the FAQ at http://www.tux.org/lkml/
On Thu, May 21, 2015 at 4:57 PM, Ezequiel Garcia
wrote:
> This commit adds a rate parameter table, which makes it possible for
> the MIPS PLL to support rate change.
>
> Signed-off-by: Govindraj Raja
> Signed-off-by: Ezequiel Garcia
> ---
> drivers/clk/pistachio/clk-pistachio.c | 12 +++
On Thu, May 21, 2015 at 4:57 PM, Ezequiel Garcia
wrote:
> This commit passes CLK_SET_RATE_PARENT to the "mips_div",
> "mips_internal_div", and "mips_pll_mux" clocks. This flag is needed for the
> "mips" clock to propagate rate changes up to the "mips_pll" root clock.
>
> Signed-off-by: Govindraj R
On Thu, May 21, 2015 at 4:57 PM, Ezequiel Garcia
wrote:
> As preparation work to support MIPS PLL rate change propagation, this
> commit adds a MUX_F macro to pass clk_flags.
>
> Signed-off-by: Govindraj Raja
> Signed-off-by: Ezequiel Garcia
> --- a/drivers/clk/pistachio/clk.h
> +++ b/drivers/c
On Thu, May 21, 2015 at 4:57 PM, Ezequiel Garcia
wrote:
> As preparation work to support MIPS PLL rate change propagation, this
> commit extends the DIV_F macro to pass clk_flags in addition to div_flags.
>
> Signed-off-by: Govindraj Raja
> Signed-off-by: Ezequiel Garcia
Revi
On Thu, May 21, 2015 at 4:57 PM, Ezequiel Garcia
wrote:
> This commit implements small rate changes to the fractional PLL.
> This is done using the PLL frac parameter. The .set_rate function
> first finds the parameters associated to the closest nominal rate.
>
> Then the new rate is set, using pa
On Thu, May 21, 2015 at 3:25 PM, Ezequiel Garcia
wrote:
>
>
> On 05/21/2015 07:24 PM, Andrew Bresticker wrote:
>> On Thu, May 21, 2015 at 2:37 PM, Ezequiel Garcia
>> wrote:
>>> This is preparation work for the introduction of clockevent frequency
>>> upd
On Thu, May 21, 2015 at 2:43 PM, Ezequiel Garcia
wrote:
> This commit introduces a new config, so the user can choose to enable
> the General Purpose Timer based clocksource. This option is required
> to have CPUFreq support.
>
> Signed-off-by: Ezequiel Garcia
> ---
> arch/mips/Kconfig
On Thu, May 21, 2015 at 2:41 PM, Ezequiel Garcia
wrote:
> The Pistachio SoC provides four general purpose timers, and allow
> to implement a clocksource driver.
>
> This driver can be used as a replacement for the MIPS GIC and MIPS R4K
> clocksources and sched clocks, which are clocked from the CP
On Thu, May 21, 2015 at 2:41 PM, Ezequiel Garcia
wrote:
> Add a device-tree binding document for the clocksource driver provided
> by Pistachio SoC general purpose timers.
>
> Signed-off-by: Ezequiel Garcia
Reviewed-by: Andrew Bresticker
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On Thu, May 21, 2015 at 2:37 PM, Ezequiel Garcia
wrote:
> This commit introduces the clockevent frequency update, using
> a clock notifier. It will be used to support CPUFreq on platforms
> using MIPS GIC based clockevents.
>
> Signed-off-by: Ezequiel Garcia
> ---
> drivers/clocksource/mips-gic-
On Thu, May 21, 2015 at 2:37 PM, Ezequiel Garcia
wrote:
> This is preparation work for the introduction of clockevent frequency
> update with a clock notifier. This is only possible when the device
> is passed a clk struct, so let's split the legacy and devicetree
> initialization.
>
> Signed-off-
On Thu, May 21, 2015 at 2:37 PM, Ezequiel Garcia
wrote:
> This commit adds the required checks on the functions that return
> an error. Some of them are not critical, so only a warning is
> printed.
>
> Signed-off-by: Ezequiel Garcia
Reviewed-by: Andrew Bresticker
--
To unsubs
_put.
>
> Signed-off-by: Ezequiel Garcia
Reviewed-by: Andrew Bresticker
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Please read the FAQ at http://www.tux.org/lkml/
Hi Mathias,
On Mon, May 4, 2015 at 10:36 AM, Andrew Bresticker
wrote:
> xhci_gen_setup() sets the hcd_priv field for the primary HCD, but not
> for the shared HCD, requiring xHCI host-controller drivers to set it
> between usb_create_shared_hcd() and usb_add_hcd(). There&#x
Lee,
On Thu, May 14, 2015 at 10:38 AM, Andrew Bresticker
wrote:
> On Thu, May 14, 2015 at 12:40 AM, Lee Jones wrote:
>> On Thu, 14 May 2015, Jon Hunter wrote:
>>
>>> Hi Lee,
>>>
>>> On 13/05/15 15:39, Lee Jones wrote:
>>> > On Mon, 04
blocks PM suspend/resume functions (Debian Bug#666406).
>
> Signed-off-by: Arthur Demchenkov
Oops, sorry about that! Anyway,
Reviewed-by: Andrew Bresticker
I suppose this should be a considered a stable fix for v3.18 and later.
Thanks,
Andrew
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On Mon, May 11, 2015 at 7:45 AM, Kishon Vijay Abraham I wrote:
>
>
> On Tuesday 05 May 2015 11:43 PM, Ezequiel Garcia wrote:
>>
>> Hi Kishon,
>>
>>>
>>> This series adds support for the USB2.0 PHY present on the IMG Pistachio
>>> SoC.
>>>
>>> Based on mips-for-linux-next and tested on the IMG Pist
On Thu, May 14, 2015 at 12:40 AM, Lee Jones wrote:
> On Thu, 14 May 2015, Jon Hunter wrote:
>
>> Hi Lee,
>>
>> On 13/05/15 15:39, Lee Jones wrote:
>> > On Mon, 04 May 2015, Andrew Bresticker wrote:
>> >
>> >> Add a binding document for the XUS
On Wed, May 13, 2015 at 9:50 AM, Lee Jones wrote:
> On Wed, 13 May 2015, Andrew Bresticker wrote:
>
>> Lee,
>>
>> On Wed, May 13, 2015 at 7:39 AM, Lee Jones wrote:
>> > On Mon, 04 May 2015, Andrew Bresticker wrote:
>> >
>> >> Add a binding
Lee,
On Wed, May 13, 2015 at 7:37 AM, Lee Jones wrote:
> On Mon, 04 May 2015, Andrew Bresticker wrote:
>
>> Add an MFD driver for the XUSB host complex found on NVIDIA Tegra124
>> and later SoCs.
>
> What else does it do besides USB?
Nothing - it's just the xHCI hos
Lee,
On Wed, May 13, 2015 at 7:39 AM, Lee Jones wrote:
> On Mon, 04 May 2015, Andrew Bresticker wrote:
>
>> Add a binding document for the XUSB host complex on NVIDIA Tegra124
>> and later SoCs. The XUSB host complex includes a mailbox for
>> communication with the XUSB
On Fri, May 8, 2015 at 1:42 PM, Benson Leung wrote:
> On Mon, May 4, 2015 at 10:36 AM, Andrew Bresticker
> wrote:
>> + - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-mbox".
>> + Otherwise, must contain '"nvidia,-xusb-mbox",
>> +
Signed-off-by: Andrew Bresticker
Cc: James Hartley
Cc: James Hogan
---
Changes from v4:
- Switched to using gpiochip_add_pin_range().
- Fixed up Kconfig entry.
Changes from v3:
- Addressed review comments from Ezequiel.
Changes from v2:
- Removed module stuff which would be compiled out
Hi Linus,
On Wed, May 6, 2015 at 12:14 AM, Linus Walleij wrote:
> Hi Andrew and sorry for a slow review process, I've been
> overloaded :(
>
> On Wed, Apr 29, 2015 at 3:13 AM, Andrew Bresticker
> wrote:
>
>> Add a driver for the pin controller present on the IMG
On Tue, May 5, 2015 at 4:35 PM, James Hogan wrote:
> On Tue, May 05, 2015 at 04:09:31PM -0700, Andrew Bresticker wrote:
>> On Tue, May 5, 2015 at 3:43 PM, James Hogan wrote:
>> > On Tue, May 05, 2015 at 03:16:23PM -0700, Andrew Bresticker wrote:
>> >> Hi James,
>
On Tue, May 5, 2015 at 3:43 PM, James Hogan wrote:
> On Tue, May 05, 2015 at 03:16:23PM -0700, Andrew Bresticker wrote:
>> Hi James,
>>
>> On Tue, May 5, 2015 at 3:01 PM, James Hogan wrote:
>> > Hi Andrew,
>> >
>> > On Tue, Apr 07, 2015 at 03:04:
Hi James,
On Tue, May 5, 2015 at 3:01 PM, James Hogan wrote:
> Hi Andrew,
>
> On Tue, Apr 07, 2015 at 03:04:16PM -0700, Andrew Bresticker wrote:
>> Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC.
>>
>> Signed-off-by: Andrew Bresticker
>&
Hi Rhyland,
On Mon, May 4, 2015 at 9:37 AM, Rhyland Klein wrote:
> Tegra210 has significant differences in muxes for peripheral clocks.
> One of the most important changes is that pll_m isn't to be used
> as a source for peripherals. Therefore, we need to define the new
> muxes and new clocks to
NULL so that the
error can be propagated back to the caller of mbox_request_channel().
Signed-off-by: Benson Leung
Signed-off-by: Andrew Bresticker
Acked-by: Suman Anna
Cc: Jassi Brar
---
No changes from v7.
Changes from v6:
- Update omap-mailbox's xlate() to return error codes.
No changes
Add an MFD driver for the XUSB host complex found on NVIDIA Tegra124
and later SoCs.
Signed-off-by: Andrew Bresticker
Cc: Samuel Ortiz
Cc: Lee Jones
---
Changes from v7:
- Have child nodes get non-shared memory and interrupts from DT.
- Use of_platform_populate rather than mfd_add_devices
Add device-tree bindings for the Tegra XUSB mailbox which will be used
for communication between the Tegra xHCI controller's firmware and the
host processor.
Signed-off-by: Andrew Bresticker
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: Jassi
Add device-tree binding documentation for the xHCI controller present
on Tegra124 and later SoCs.
Signed-off-by: Andrew Bresticker
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: Mathias Nyman
Cc: Greg Kroah-Hartman
---
Changes from v7:
- Added back
x27;s firmware.
The controller also supports USB device mode as well as powergating
of the SuperSpeed and host-controller logic when not in use, but
support for these is not yet implemented.
Based on work by:
Ajay Gupta
Bharath Yadav
Signed-off-by: Andrew Bresticker
Cc: Mathias Nyman
Cc: Greg
oller driver. The requesting driver is assigned
one of two virtual channels when the single physical channel is
requested. All incoming messages are sent to both virtual channels.
Signed-off-by: Andrew Bresticker
Cc: Jassi Brar
---
Changes from v7:
- Don't reset ownership of mailbox fo
Add a binding document for the XUSB host complex on NVIDIA Tegra124
and later SoCs. The XUSB host complex includes a mailbox for
communication with the XUSB micro-controller and an xHCI host-controller.
Signed-off-by: Andrew Bresticker
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian
bit out of the host-controller drivers and into xhci_gen_setup().
Signed-off-by: Andrew Bresticker
Reviewed-by: Felipe Balbi
Cc: Mathias Nyman
Cc: Greg Kroah-Hartman
---
No changes from v5/v6/v7.
New for v5.
Peviously posted here: https://lkml.org/lkml/2014/10/30/726
---
drivers/usb/host/
The mailbox controller's channel ops ought to be read-only. Update
all the mailbox drivers to make their mbox_chan_ops const as well.
Signed-off-by: Andrew Bresticker
Cc: Jassi Brar
Cc: Suman Anna
Cc: Ashwin Chaugule
Cc: Ley Foon Tan
---
Changes from v7:
- Constify all dr
sed Stephen's review comments.
- Misc. cleanups.
Andrew Bresticker (8):
xhci: Set shared HCD's hcd_priv in xhci_gen_setup
mailbox: Make mbox_chan_ops const
mfd: Add binding document for NVIDIA Tegra XUSB
mfd: Add driver for NVIDIA Tegra XUSB
mailbox: Add NVIDIA Tegra XUSB mailbox
Hi Rhyland,
On Wed, Apr 29, 2015 at 10:21 AM, Rhyland Klein wrote:
> Implement clock support for Tegra210.
>
> Signed-off-by: Rhyland Klein
> --- /dev/null
> +++ b/drivers/clk/tegra/clk-tegra210.c
> + /* PLLU */
> + val = readl(clk_base + pll_u_params.base_reg);
> + val &= ~B
On Thu, Apr 30, 2015 at 3:06 AM, Lee Jones wrote:
> On Wed, 29 Apr 2015, Andrew Bresticker wrote:
>
>> On Wed, Apr 29, 2015 at 11:34 AM, Lee Jones wrote:
>> > On Wed, 29 Apr 2015, Andrew Bresticker wrote:
>> >
>> >> Lee,
>> >>
>> >
On Wed, Apr 29, 2015 at 11:34 AM, Lee Jones wrote:
> On Wed, 29 Apr 2015, Andrew Bresticker wrote:
>
>> Lee,
>>
>> On Wed, Apr 29, 2015 at 2:25 AM, Lee Jones wrote:
>> > On Mon, 27 Apr 2015, Andrew Bresticker wrote:
>> >
>> >> Add a binding
Hi Rhyland,
On Wed, Apr 29, 2015 at 10:21 AM, Rhyland Klein wrote:
> On Tegra210 SoC's, the logic to enable several of the plls is different
> from previous generations. Therefore, add registeration functions specific
> to Tegra210 which will handle them appropriately.
>
> Signed-off-by: Rhyland
Lee,
On Wed, Apr 29, 2015 at 2:23 AM, Lee Jones wrote:
> On Mon, 27 Apr 2015, Andrew Bresticker wrote:
>
>> Add an MFD driver for the XUSB host complex found on NVIDIA Tegra124
>> and later SoCs.
>>
>> Signed-off-by: Andrew Bresticker
>> Cc: Samuel Ortiz
Lee,
On Wed, Apr 29, 2015 at 2:25 AM, Lee Jones wrote:
> On Mon, 27 Apr 2015, Andrew Bresticker wrote:
>
>> Add a binding document for the XUSB host complex on NVIDIA Tegra124
>> and later SoCs. The XUSB host complex includes a mailbox for
>> communication with the XUSB
Add a device-tree binding document for the pin controller present
on the IMG Pistachio SoC.
Signed-off-by: Damien Horsley
Signed-off-by: Ezequiel Garcia
Signed-off-by: Andrew Bresticker
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
---
No changes from v2
Signed-off-by: Andrew Bresticker
---
Changes from v3:
- Addressed review comments from Ezequiel.
Changes from v2:
- Removed module stuff which would be compiled out.
Changes from v1:
- Addressed review comments from Linus.
- Changed compatible string to "img,pistachio-system-pinctrl"
odule stuff that ends up being compiled out.
Changes from v1:
- Documented pin + function generic binding.
- Changed compatible string to "img,pistachio-system-pinctrl".
- Addressed some review comments.
- A couple of bug fixes.
Cc: Ezequiel Garcia
Cc: James Hartley
Cc: James Hogan
An
On Tue, Apr 28, 2015 at 4:24 PM, Ezequiel Garcia
wrote:
> Andrew,
>
> On 04/07/2015 04:44 PM, Andrew Bresticker wrote:
> [..]
>> +static int pistachio_pinmux_enable(struct pinctrl_dev *pctldev,
>> +unsigned func, unsigned grou
On Tue, Apr 28, 2015 at 3:40 PM, Ezequiel Garcia
wrote:
> Just a silly comment.
>
> On 04/07/2015 04:44 PM, Andrew Bresticker wrote:
> [..]
>> +
>> +static const struct pinmux_ops pistachio_pinmux_ops = {
>> + .get_functions_count = pistac
Add device-tree binding documentation for the xHCI controller present
on Tegra124 and later SoCs.
Signed-off-by: Andrew Bresticker
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: Mathias Nyman
Cc: Greg Kroah-Hartman
---
Changes from v6:
- Removed
oller driver. The requesting driver is assigned
one of two virtual channels when the single physical channel is
requested. All incoming messages are sent to both virtual channels.
Signed-off-by: Andrew Bresticker
Cc: Jassi Brar
---
Changes from v6:
- Access FPCI registers using parent MFD
The mailbox controller's channel ops ought to be read-only.
Signed-off-by: Andrew Bresticker
Cc: Jassi Brar
---
No changes from v5/v6.
New for v5.
---
include/linux/mailbox_controller.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/mailbox_controller
NULL so that the
error can be propagated back to the caller of mbox_request_channel().
Signed-off-by: Benson Leung
Signed-off-by: Andrew Bresticker
Cc: Jassi Brar
Cc: Suman Anna
---
Changes from v6:
- Update omap-mailbox's xlate() to return error codes.
No changes from v5.
New f
bit out of the host-controller drivers and into xhci_gen_setup().
Signed-off-by: Andrew Bresticker
Reviewed-by: Felipe Balbi
Cc: Mathias Nyman
Cc: Greg Kroah-Hartman
---
No changes from v5/v6.
New for v5.
Peviously posted here: https://lkml.org/lkml/2014/10/30/726
---
drivers/usb/host/
Add device-tree bindings for the Tegra XUSB mailbox which will be used
for communication between the Tegra xHCI controller's firmware and the
host processor.
Signed-off-by: Andrew Bresticker
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: Jassi
Add a binding document for the XUSB host complex on NVIDIA Tegra124
and later SoCs. The XUSB host complex includes a mailbox for
communication with the XUSB micro-controller and an xHCI host-controller.
Signed-off-by: Andrew Bresticker
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian
x27;s firmware.
The controller also supports USB device mode as well as powergating
of the SuperSpeed and host-controller logic when not in use, but
support for these is not yet implemented.
Based on work by:
Ajay Gupta
Bharath Yadav
Signed-off-by: Andrew Bresticker
Cc: Mathias Nyman
Cc: Greg
Add an MFD driver for the XUSB host complex found on NVIDIA Tegra124
and later SoCs.
Signed-off-by: Andrew Bresticker
Cc: Samuel Ortiz
Cc: Lee Jones
---
New for v7.
---
drivers/mfd/Kconfig | 7 ++
drivers/mfd/Makefile | 1 +
drivers/mfd/tegra-xusb.c | 167
ts.
Changes from v1:
- Converted mailbox driver to use the common mailbox framework.
- Fixed up host driver so that it can now be built and used as a module.
- Addressed Stephen's review comments.
- Misc. cleanups.
Andrew Bresticker (8):
xhci: Set shared HCD's hcd_priv in xhci_ge
Hi Kevin,
On Mon, Apr 20, 2015 at 8:12 AM, Kevin Cernekee wrote:
> On Mon, Apr 20, 2015 at 5:21 AM, Mark Brown wrote:
>> On Sat, Apr 18, 2015 at 01:07:07PM -0700, Kevin Cernekee wrote:
>>> On Sat, Apr 18, 2015 at 10:11 AM, Mark Brown wrote:
>>
>>> > Someone trying to use the atmel_wm8904 driver
Hi Ezequiel,
On Thu, Apr 16, 2015 at 10:27 PM, Ezequiel Garcia
wrote:
>
> Hi Andrew,
>
> On 04/07/2015 04:44 PM, Andrew Bresticker wrote:
> [..]
>> +static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
>> +{
>> + struct device_node *node = pc
Imagination has recommended that the SPFI controller be reset after
each message, regardless of success or failure. Do this in an
unprepare_message() callback.
Signed-off-by: Andrew Bresticker
---
New for v2.
---
drivers/spi/spi-img-spfi.c | 13 +++--
1 file changed, 11 insertions
From: Ezequiel Garcia
The driver can be greatly simplified by moving the transfer timeout
handling to a handle_err() callback.
Signed-off-by: Ezequiel Garcia
Signed-off-by: Andrew Bresticker
---
Changes from v1:
- Moved timeout handling from unprepare_message() to handle_err()
---
drivers
ff-by: Ezequiel Garcia
Signed-off-by: Andrew Bresticker
---
This breaks device-tree backwards compatibility, but all existing
device-trees using this binding have been updated.
No changes from v1.
---
.../devicetree/bindings/spi/spi-img-spfi.txt | 1 +
drivers/spi/spi-img-s
Add a driver for the USB2.0 PHY found on the IMG Pistachio SoC.
Signed-off-by: Andrew Bresticker
---
Changes from v1:
- Fixed a couple of typos
---
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile| 1 +
drivers/phy/phy-pistachio-usb.c | 206
Add a binding document for the USB2.0 PHY found on the IMG Pistachio SoC.
Signed-off-by: Andrew Bresticker
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
---
No changes from v1.
---
.../devicetree/bindings/phy/pistachio-usb-phy.txt | 29
d patch to enable PHY driver in pistachio_defconfig
- Fixed a couple of spelling errors
Andrew Bresticker (3):
phy: Add binding document for Pistachio USB2.0 PHY
phy: Add driver for Pistachio USB2.0 PHY
MIPS: pistachio: Enable USB PHY driver in defconfig
.../devicetree/bindings/phy/pis
Update pistachio_defconfig to enable Pistachio's USB PHY driver.
Signed-off-by: Andrew Bresticker
---
New for v2.
---
arch/mips/configs/pistachio_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/configs/pistachio_defconfig
b/arch/mips/configs/pistachio_defconfig
On Tue, Apr 7, 2015 at 10:16 AM, James Hartley wrote:
>
>
>> -Original Message-
>> From: abres...@google.com [mailto:abres...@google.com] On Behalf Of
>> Andrew Bresticker
>> Sent: 06 April 2015 23:28
>> To: Arnd Bergmann; James Hartley
>> Cc: Da
The DWMAC block on certain SoCs (such as IMG Pistachio) have a second
clock which must be enabled in order to access the peripheral's
register interface, so add support for requesting and enabling an
optional "pclk".
Signed-off-by: Andrew Bresticker
Cc: James Hartley
Cc
Add a device-tree binding document for the pin controller present
on the IMG Pistachio SoC.
Signed-off-by: Damien Horsley
Signed-off-by: Ezequiel Garcia
Signed-off-by: Andrew Bresticker
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
---
No changes from v2
Signed-off-by: Andrew Bresticker
Cc: Paul Bolle
---
Changes from v2:
- Removed module stuff which would be compiled out.
Changes from v1:
- Addressed review comments from Linus.
- Changed compatible string to "img,pistachio-system-pinctrl".
- Look for GPIO sub-nodes by name.
- A
from v1:
- Documented pin + function generic binding.
- Changed compatible string to "img,pistachio-system-pinctrl".
- Addressed some review comments.
- A couple of bug fixes.
Cc: Ezequiel Garcia
Cc: James Hartley
Cc: James Hogan
Andrew Bresticker (2):
pinctrl: Add Pistachio
On Tue, Apr 7, 2015 at 4:23 AM, Mark Brown wrote:
> On Mon, Apr 06, 2015 at 02:29:06PM -0700, Andrew Bresticker wrote:
>> From: Sifan Naeem
>>
>> Setting the transfer length in the TRANSACTION register after the
>> CONTROL register is programmed causes intermitten
On Mon, Apr 6, 2015 at 3:10 PM, Arnd Bergmann wrote:
> On Monday 06 April 2015 14:42:38 Andrew Bresticker wrote:
>> At the moment, the only additional setup required for the DWMAC
>> on the IMG Pistachio SoC is to request and enable a separate gate
>> clock for t
At the moment, the only additional setup required for the DWMAC
on the IMG Pistachio SoC is to request and enable a separate gate
clock for the register interface.
Signed-off-by: Andrew Bresticker
Signed-off-by: Govindraj Raja
Cc: James Hartley
---
Changes from v1:
- Do not potentially assign
Add a binding document for the DWMAC ethernet controller found on the
IMG Pistachio SoC.
Signed-off-by: Andrew Bresticker
Cc: Rob Herring
Cc: Pawel Moll
Cc: Mark Rutland
Cc: Ian Campbell
Cc: Kumar Gala
Cc: James Hartley
---
No changes from v1.
---
.../devicetree/bindings/net/pistachio
CONTROL register.
Signed-off-by: Sifan Naeem
Signed-off-by: Andrew Bresticker
---
drivers/spi/spi-img-spfi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c
index 30c89f9..adeaa2f 100644
--- a/drivers/spi/spi-img-spfi.c
From: Ezequiel Garcia
In preparation for switching to using the SPI core's CS GPIO handling,
move setup of the PORT_STATE register, which must be configured before
CS is asserted, to a prepare_message() callback.
Signed-off-by: Ezequiel Garcia
Signed-off-by: Andrew Bresticker
---
driver
ff-by: Ezequiel Garcia
Signed-off-by: Andrew Bresticker
---
This breaks device-tree backwards compatibility, but all existing
device-trees using this binding have been updated.
---
.../devicetree/bindings/spi/spi-img-spfi.txt | 1 +
drivers/spi/spi-img-spfi.c
Although the SPFI BITCLK divider supports a value of up to 255, only
values up to 128 are usable. This results in a maximum possible bit
clock rate of 1/4th the input clock rate.
Signed-off-by: Andrew Bresticker
---
drivers/spi/spi-img-spfi.c | 10 +-
1 file changed, 5 insertions(+), 5
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