uot;sw %0, 1(%1)" : : "r"(val), "r"(buf) : "memory");
+}
+
+int main(int argc, char **argv)
+{
+ int ret, val;
+
+ ret = prctl(PR_GET_UNALIGN, &val);
+ if (ret == -1 && errno == EINVAL)
+ ksft_exit_skip("SKIP GET_UNALIGN_CTL not supported\n");
+
+ exit(test_harness_run(argc, argv));
+}
Tested-by: Alexandre Ghiti
Thanks,
Alex
On 6/24/25 14:34, Clément Léger wrote:
Gentle ping.
I put it back again on my for-next branch.
Thanks,
Alex
Thanks,
Clément
On 22/05/2025 14:51, Clément Léger wrote:
This selftest tests all the currently emulated instructions (except for
the RV32 compressed ones which are left as a fu
amp;& errno == EINVAL)
+ ksft_exit_skip("SKIP GET_UNALIGN_CTL not supported\n");
+
+ exit(test_harness_run(argc, argv));
+}
Tested-by: Alexandre Ghiti
Thanks,
Alex
Hi Clément,
On 12/05/2025 10:46, Clément Léger wrote:
This selftest tests all the currently emulated instruction (except for
the RV32 compressed ones which are left as a future exercise for a RV32
user). For the FPU instructions, all the FPU registers are tested.
This commit can be tested using
Hi ignacio,
On 30/03/2025 13:12, Ignacio Encinas Rubio wrote:
Gentle ping :)
No worries, it's either being merged in 6.15-rc1 or rc2!
Thanks,
Alex
On 6/3/25 20:49, Ignacio Encinas wrote:
Vector registers are zero initialized by the kernel. Stop accepting
"all ones" as a clean value.
N
Hi Celeste,
On 03/12/2024 10:30, Celeste Liu wrote:
The orig_a0 is missing in struct user_regs_struct of riscv, and there is
no way to add it without breaking UAPI. (See Link tag below)
Like NT_ARM_SYSTEM_CALL do, we add a new regset name NT_RISCV_ORIG_A0 to
access original a0 register from use
Hi Drew,
On 05/12/2024 09:04, Andrew Jones wrote:
On Wed, Dec 04, 2024 at 06:57:10PM -0800, Charlie Jenkins wrote:
When compiling the pointer masking tests with -Wall this warning
is present:
pointer_masking.c: In function ‘test_tagged_addr_abi_sysctl’:
pointer_masking.c:203:9: warning: ignori
Hi Charlie,
On 05/12/2024 03:57, Charlie Jenkins wrote:
When compiling the pointer masking tests with -Wall this warning
is present:
pointer_masking.c: In function ‘test_tagged_addr_abi_sysctl’:
pointer_masking.c:203:9: warning: ignoring return value of ‘pwrite’
declared with attribute ‘warn_un
altmap);
if (pgtable_l4_enabled)
- free_pmd_table(pmd_base, pudp);
+ free_pmd_table(pmd_base, pudp, is_vmemmap);
}
}
base-commit: 57f7c7dc78cd09622b12920d92b40c1ce11b234e
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
H)/include
export prefix libdir src obj
base-commit: db5ca265e3334b48c4e3fa07eef79e8bc578c430
You can add:
Tested-by: Alexandre Ghiti
Thanks,
Alex
Hi Geert,
On Tue, Jul 9, 2024 at 10:13 AM Geert Uytterhoeven wrote:
>
> Hi Alexandre,
>
> On Mon, Jun 24, 2024 at 10:23 AM Alexandre Ghiti
> wrote:
> > We cannot delay the icache flush after patching some functions as we may
> > have patched a function that will g
64BIT
> select ARCH_WANT_LD_ORPHAN_WARN if !XIP_KERNEL
> + select ARCH_WANT_OPTIMIZE_DAX_VMEMMAP
> select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP
> select ARCH_WANTS_NO_INSTR
> select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
> --
> 2.43.0
>
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
FSET);
> + mhp_range.end = __pa(PAGE_END - 1);
> + return mhp_range;
> +}
> +
> +int __ref arch_add_memory(int nid, u64 start, u64 size, struct mhp_params
> *params)
> +{
> + int ret = 0;
> +
> + create_linear_mapping_range(start, start + size, 0, ¶ms->pgprot);
> + ret = __add_pages(nid, start >> PAGE_SHIFT, size >> PAGE_SHIFT,
> params);
> + if (ret) {
> + remove_linear_mapping(start, size);
> + goto out;
> + }
> +
> + max_pfn = PFN_UP(start + size);
> + max_low_pfn = max_pfn;
> +
> + out:
> + flush_tlb_all();
> + return ret;
> +}
> +
> +void __ref arch_remove_memory(u64 start, u64 size, struct vmem_altmap
> *altmap)
> +{
> + __remove_pages(start >> PAGE_SHIFT, size >> PAGE_SHIFT, altmap);
> + remove_linear_mapping(start, size);
> + flush_tlb_all();
> +}
> +
> +void __ref vmemmap_free(unsigned long start, unsigned long end, struct
> vmem_altmap *altmap)
> +{
> + remove_pgd_mapping(start, end, true, altmap);
> +}
> +#endif /* CONFIG_MEMORY_HOTPLUG */
> --
> 2.43.0
>
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
_va(pfn << PAGE_SHIFT);
> +}
> +
> #endif /* __ASSEMBLY__ */
>
> #define virt_addr_valid(vaddr) ({
> \
> --
> 2.43.0
>
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
batch the icache maintenance anymore.
Fixes: 6ca445d8af0e ("riscv: Fix early ftrace nop patching")
Reported-by: Conor Dooley
Closes:
https://lore.kernel.org/linux-riscv/20240613-lubricant-breath-061192a9489a@wendy/
Signed-off-by: Alexandre Ghiti
---
arch/riscv/kernel/ftrace.c | 7 ++--
On 20/06/2024 19:03, Alexandre Ghiti wrote:
On 19/06/2024 05:40, Andy Chiu wrote:
On Tue, Jun 18, 2024 at 9:40 PM Alexandre Ghiti
wrote:
Hi Andy,
On Tue, Jun 18, 2024 at 2:48 PM Andy Chiu wrote:
On Tue, Jun 18, 2024 at 8:02 PM Alexandre Ghiti wrote:
Hi Conor,
On 17/06/2024 15:23
On 19/06/2024 05:40, Andy Chiu wrote:
On Tue, Jun 18, 2024 at 9:40 PM Alexandre Ghiti wrote:
Hi Andy,
On Tue, Jun 18, 2024 at 2:48 PM Andy Chiu wrote:
On Tue, Jun 18, 2024 at 8:02 PM Alexandre Ghiti wrote:
Hi Conor,
On 17/06/2024 15:23, Alexandre Ghiti wrote:
Hi Conor,
Sorry for the
Hi Andy,
On Tue, Jun 18, 2024 at 2:48 PM Andy Chiu wrote:
>
> On Tue, Jun 18, 2024 at 8:02 PM Alexandre Ghiti wrote:
> >
> > Hi Conor,
> >
> > On 17/06/2024 15:23, Alexandre Ghiti wrote:
> > > Hi Conor,
> > >
> > > Sorry for the delay
Hi Conor,
On 17/06/2024 15:23, Alexandre Ghiti wrote:
Hi Conor,
Sorry for the delay here.
On 13/06/2024 09:48, Conor Dooley wrote:
On Thu, May 23, 2024 at 01:51:34PM +0200, Alexandre Ghiti wrote:
Commit c97bf629963e ("riscv: Fix text patching when IPI are used")
converted ftrac
void arch_stack_walk(stack_trace_consume_fn consume_entry,
void *cookie,
struct task_struct *task, struct pt_regs *regs)
{
walk_stackframe(task, regs, consume_entry, cookie);
Reviewed-by: Alexandre Ghiti
I'll try to make this go into -fixes, this is in my fixes branch at least.
Thanks,
Alex
Hi Conor,
Sorry for the delay here.
On 13/06/2024 09:48, Conor Dooley wrote:
On Thu, May 23, 2024 at 01:51:34PM +0200, Alexandre Ghiti wrote:
Commit c97bf629963e ("riscv: Fix text patching when IPI are used")
converted ftrace_make_nop() to use patch_insn_write() which does not
emit
: fix this by emitting a
local flush icache when early patching nops.
Fixes: c97bf629963e ("riscv: Fix text patching when IPI are used")
Signed-off-by: Alexandre Ghiti
---
arch/riscv/include/asm/cacheflush.h | 6 ++
arch/riscv/kernel/ftrace.c | 3 +++
2 files changed, 9
| _PAGE_DEVMAP);
> +}
> +
> static inline pte_t pte_mkhuge(pte_t pte)
> {
> return pte;
> @@ -711,6 +723,11 @@ static inline pmd_t pmd_mkdirty(pmd_t pmd)
> return pte_pmd(pte_mkdirty(pmd_pte(pmd)));
> }
>
> +static inline pmd_t pmd_mkdevmap(pmd_t pmd)
> +{
> + return pte_pmd(pte_mkdevmap(pmd_pte(pmd)));
> +}
> +
> static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
> pmd_t *pmdp, pmd_t pmd)
> {
> --
> 2.40.1
>
Otherwise, you can add:
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
M_VMEMMAP_ENABLE is only enabled on 64BIT.
> + select ARCH_ENABLE_MEMORY_HOTREMOVE if MEMORY_HOTPLUG
> select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
> select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
> select ARCH_HAS_BINFMT_FLAT
> --
&
On Tue, May 21, 2024 at 1:49 PM Björn Töpel wrote:
>
> From: Björn Töpel
>
> For an architecture to support memory hotplugging, a couple of
> callbacks needs to be implemented:
>
> arch_add_memory()
> This callback is responsible for adding the physical memory into the
> direct map, and call
nit pgprot_t pgprot_from_va(uintptr_t va)
> {
> if (IS_ENABLED(CONFIG_64BIT) && !is_kernel_mapping(va))
> return PAGE_KERNEL;
> @@ -1231,9 +1226,8 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa)
> pt_ops_set_fixmap();
> }
>
> -static void __init create_linear_mapping_range(phys_addr_t start,
> - phys_addr_t end,
> - uintptr_t fixed_map_size)
> +static void __meminit create_linear_mapping_range(phys_addr_t start,
> phys_addr_t end,
> + uintptr_t fixed_map_size)
> {
> phys_addr_t pa;
> uintptr_t va, map_size;
> --
> 2.40.1
>
You can add:
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
tmap);
> }
> #endif
>
> --
> 2.40.1
>
You can add:
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
On Tue, May 14, 2024 at 8:17 PM Björn Töpel wrote:
>
> Alexandre Ghiti writes:
>
> > On Tue, May 14, 2024 at 4:05 PM Björn Töpel wrote:
> >>
> >> From: Björn Töpel
> >>
> >> Enable ARCH_ENABLE_MEMORY_HOTPLUG and ARCH_ENABLE_MEMORY_HOTREMOVE fo
On Tue, May 14, 2024 at 4:05 PM Björn Töpel wrote:
>
> From: Björn Töpel
>
> Enable ARCH_ENABLE_MEMORY_HOTPLUG and ARCH_ENABLE_MEMORY_HOTREMOVE for
> RISC-V.
>
> Signed-off-by: Björn Töpel
> ---
> arch/riscv/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/riscv/Kconfig b
On Tue, May 14, 2024 at 4:05 PM Björn Töpel wrote:
>
> From: Björn Töpel
>
> For an architecture to support memory hotplugging, a couple of
> callbacks needs to be implemented:
>
> arch_add_memory()
> This callback is responsible for adding the physical memory into the
> direct map, and call
krodata_size);
> #endif
>
> #ifdef CONFIG_KFENCE
> - create_linear_mapping_range(kfence_pool,
> - kfence_pool + KFENCE_POOL_SIZE,
> - PAGE_SIZE);
> + create_linear_mapping_range(kfence_pool, kfence_pool +
> KFENCE_POOL_SIZE, PAGE_SIZE, NULL);
>
> memblock_clear_nomap(kfence_pool, KFENCE_POOL_SIZE);
> #endif
> --
> 2.40.1
>
You can add:
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
On Tue, May 14, 2024 at 4:05 PM Björn Töpel wrote:
>
> From: Björn Töpel
>
> Prepare for memory hotplugging support by changing from __init to
> __meminit for the page table functions that are used by the upcoming
> architecture specific callbacks.
>
> Changing the __init attribute to __meminit,
END,
> "bpf/modules");
> + if (IS_ENABLED(CONFIG_MEMORY_HOTPLUG)) {
> + preallocate_pgd_pages_range(VMEMMAP_START, VMEMMAP_END,
> "vmemmap");
> + preallocate_pgd_pages_range(PAGE_OFFSET, PAGE_END, "direct
> map");
> + }
> }
> #endif
> --
> 2.40.1
>
As you asked, with
https://lore.kernel.org/linux-riscv/20240514133614.87813-1-alexgh...@rivosinc.com/T/#u,
you will be able to remove the usage of KASAN_SHADOW_START.
But anyhow, you can add:
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
On 26/03/2024 17:49, Jarkko Sakkinen wrote:
On Tue Mar 26, 2024 at 3:57 PM EET, Alexandre Ghiti wrote:
Hi Jarkko,
On 25/03/2024 22:55, Jarkko Sakkinen wrote:
Tacing with kprobes while running a monolithic kernel is currently
impossible due the kernel module allocator dependency.
Address the
Hi Jarkko,
On 25/03/2024 22:55, Jarkko Sakkinen wrote:
Tacing with kprobes while running a monolithic kernel is currently
impossible due the kernel module allocator dependency.
Address the issue by implementing textmem API for RISC-V.
Link: https://www.sochub.fi # for power on testing new SoC'
+cc Andy and Evgenii
On 06/03/2024 21:35, Alexandre Ghiti wrote:
Hi Puranjay,
On 06/03/2024 17:59, Puranjay Mohan wrote:
This patch enables support for DYNAMIC_FTRACE_WITH_CALL_OPS on RISC-V.
This allows each ftrace callsite to provide an ftrace_ops to the common
ftrace trampoline, allowing
Hi Puranjay,
On 06/03/2024 17:59, Puranjay Mohan wrote:
This patch enables support for DYNAMIC_FTRACE_WITH_CALL_OPS on RISC-V.
This allows each ftrace callsite to provide an ftrace_ops to the common
ftrace trampoline, allowing each callsite to invoke distinct tracer
functions without the need to
Töpel
Signed-off-by: Björn Töpel
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrea Parri
---
arch/riscv/include/asm/patch.h | 1 +
arch/riscv/kernel/ftrace.c | 44 ++
arch/riscv/kernel/patch.c | 16 +
3 files changed, 53 insertions(+), 8
This memory barrier is not needed and not documented so simply remove
it.
Suggested-by: Andrea Parri
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrea Parri
---
arch/riscv/kernel/patch.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/riscv/kernel/patch.c b/arch/riscv/kernel/patch.c
then remove the memory barrier from patch 2 as
suggested by Andrea
- Convert atomic_inc into an atomic_inc with release semantics as
suggested by Andrea
Alexandre Ghiti (2):
riscv: Remove superfluous smp_mb()
riscv: Fix text patching when IPI are used
arch/riscv/include/asm/patch.h | 1
On Wed, Feb 28, 2024 at 7:21 PM Samuel Holland
wrote:
>
> Hi Alex,
>
> On 2024-02-28 11:51 AM, Alexandre Ghiti wrote:
> > For now, we use stop_machine() to patch the text and when we use IPIs for
> > remote icache flushes (which is emitted in patch_text_nosync()), the syst
Töpel
Signed-off-by: Björn Töpel
Signed-off-by: Alexandre Ghiti
---
arch/riscv/include/asm/patch.h | 1 +
arch/riscv/kernel/ftrace.c | 42 ++
arch/riscv/kernel/patch.c | 18 +--
3 files changed, 50 insertions(+), 11 deletions(-)
diff --git a
This memory barrier is not needed and not documented so simply remove
it.
Suggested-by: Andrea Parri
Signed-off-by: Alexandre Ghiti
---
arch/riscv/kernel/patch.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/riscv/kernel/patch.c b/arch/riscv/kernel/patch.c
index 37e87fdcf6a0
Andrea
Alexandre Ghiti (2):
riscv: Remove superfluous smp_mb()
riscv: Fix text patching when IPI are used
arch/riscv/include/asm/patch.h | 1 +
arch/riscv/kernel/ftrace.c | 42 ++
arch/riscv/kernel/patch.c | 19 ---
3 files changed, 50
Hi Andrea,
On Thu, Feb 8, 2024 at 12:42 PM Andrea Parri wrote:
>
> > +static int __ftrace_modify_code(void *data)
> > +{
> > + struct ftrace_modify_param *param = data;
> > +
> > + if (atomic_inc_return(¶m->cpu_count) == num_online_cpus()) {
> > + ftrace_modify_all_code(param-
.
Co-developed-by: Björn Töpel
Signed-off-by: Björn Töpel
Signed-off-by: Alexandre Ghiti
---
arch/riscv/include/asm/patch.h | 1 +
arch/riscv/kernel/ftrace.c | 38 ++
arch/riscv/kernel/patch.c | 11 +-
3 files changed, 40 insertions(+), 10
@Conor Dooley This fails checkpatch but the documentation here states
that this is how to do:
https://elixir.bootlin.com/linux/latest/source/Documentation/trace/ftrace-design.rst#L246
On Tue, Oct 3, 2023 at 8:24 PM Alexandre Ghiti wrote:
>
> ftrace creates entries for each syscall in the t
lso ignore compat syscalls like x86/arm64 by implementing
arch_trace_is_compat_syscall().
Fixes: 08d0ce30e0e4 ("riscv: Implement syscall wrappers")
Signed-off-by: Alexandre Ghiti
---
arch/riscv/include/asm/ftrace.h | 21 +
1 file changed, 21 insertions(+)
diff --git
ERNEL, 0, NUMA_NO_NODE,
- __builtin_return_address(0));
-}
-
-void bpf_jit_free_exec(void *addr)
-{
- return vfree(addr);
-}
-
void *bpf_arch_text_copy(void *dst, void *src, size_t len)
{
int ret;
Otherwise, you can add:
Reviewed-by: Alexandre Ghiti
Thanks,
Alex
esses")
Signed-off-by: Alexandre Ghiti
---
arch/riscv/mm/ptdump.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
index 0aba4421115c..a4ed4bdbbfde 100644
--- a/arch/riscv/mm/ptdump.c
+++ b/arch/riscv/mm/ptdump.c
@@ -
Fix multiple leftovers when moving the kernel mapping outside the linear
mapping for 64b kernel that left the 32b kernel unusable.
Fixes: 4b67f48da707 ("riscv: Move kernel mapping outside of linear mapping")
Signed-off-by: Alexandre Ghiti
---
arch/riscv/include/asm/page
If CONFIG_STRICT_KERNEL_RWX is not set, we cannot set different permissions
to the kernel data and text sections, so make sure it is defined before
trying to protect the kernel linear mapping.
Signed-off-by: Alexandre Ghiti
---
arch/riscv/kernel/setup.c | 8
1 file changed, 4
.
XIP on RISC-V will for the time being only work on MMU-enabled
kernels.
Signed-off-by: Alexandre Ghiti [ Rebase on top of "Move
kernel mapping outside the linear mapping" ]
Signed-off-by: Vitaly Wool
---
arch/riscv/Kconfig | 55 +++-
arch/risc
y the
different zones of the vm layout.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Anup Patel
---
arch/riscv/mm/ptdump.c | 73 +++---
1 file changed, 61 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
index ace74de
This new document presents the RISC-V virtual memory layout and is based
one the x86 one: it describes the different limits of the different regions
of the virtual address space.
Signed-off-by: Alexandre Ghiti
---
Documentation/riscv/index.rst | 1 +
Documentation/riscv/vm-layout.rst | 63
space, both
sv39 and sv48 kernels will be exactly the same without needing to be
relocated at runtime.
Suggested-by: Arnd Bergmann
Signed-off-by: Alexandre Ghiti
---
arch/riscv/boot/loader.lds.S| 3 +-
arch/riscv/include/asm/page.h | 17 +-
arch/riscv/include/asm/pgtable.h
missing header in documentation.
- Fix another checkpatch warning about EXPORT_SYMBOL which was not
directly below variable declaration.
Alexandre Ghiti (3):
riscv: Move kernel mapping outside of linear mapping
Documentation: riscv: Add documentation that describes the VM layout
riscv
.
XIP on RISC-V will for the time being only work on MMU-enabled
kernels.
Signed-off-by: Alexandre Ghiti [ Rebase on top of "Move
kernel mapping outside the linear mapping ]
Signed-off-by: Vitaly Wool
---
Changes in v2:
- dedicated macro for XIP address fixup when MMU is not enabled yet
o
y the
different zones of the vm layout.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Anup Patel
---
arch/riscv/mm/ptdump.c | 67 ++
1 file changed, 55 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
index ace74de
This new document presents the RISC-V virtual memory layout and is based
one the x86 one: it describes the different limits of the different regions
of the virtual address space.
Signed-off-by: Alexandre Ghiti
---
Documentation/riscv/index.rst | 1 +
Documentation/riscv/vm-layout.rst | 63
space, both
sv39 and sv48 kernels will be exactly the same without needing to be
relocated at runtime.
Suggested-by: Arnd Bergmann
Signed-off-by: Alexandre Ghiti
---
arch/riscv/boot/loader.lds.S| 3 +-
arch/riscv/include/asm/page.h | 17 +-
arch/riscv/include/asm/pgtable.h
initialized in nommu config.
Changes in v2:
- Fix documentation about direct mapping size which is 124GB instead
of 126GB.
- Fix SPDX missing header in documentation.
- Fix another checkpatch warning about EXPORT_SYMBOL which was not
directly below variable declaration.
Alexandre Ghiti (3
In case the command line given by the user is too long, warn about it
and truncate it to the last full argument.
This is what efi already does in commit 80b1bfe1cb2f ("efi/libstub:
Don't parse overlong command lines").
Reported-by: Dmitry Vyukov
Signed-off-by: Alexandre Ghiti
Increase COMMAND_LINE_SIZE as the current default value is too low
for syzbot kernel command line.
Reported-by: Dmitry Vyukov
Signed-off-by: Alexandre Ghiti
---
arch/riscv/include/uapi/asm/setup.h | 8
1 file changed, 8 insertions(+)
create mode 100644 arch/riscv/include/uapi/asm
y the
different zones of the vm layout.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Anup Patel
---
arch/riscv/mm/ptdump.c | 67 ++
1 file changed, 55 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
index ace74de
This new document presents the RISC-V virtual memory layout and is based
one the x86 one: it describes the different limits of the different regions
of the virtual address space.
Signed-off-by: Alexandre Ghiti
---
Documentation/riscv/index.rst | 1 +
Documentation/riscv/vm-layout.rst | 63
space, both
sv39 and sv48 kernels will be exactly the same without needing to be
relocated at runtime.
Suggested-by: Arnd Bergmann
Signed-off-by: Alexandre Ghiti
---
arch/riscv/boot/loader.lds.S| 3 +-
arch/riscv/include/asm/page.h | 17 ++-
arch/riscv/include/asm/pgtable.h
config.
Changes in v2:
- Fix documentation about direct mapping size which is 124GB instead
of 126GB.
- Fix SPDX missing header in documentation.
- Fix another checkpatch warning about EXPORT_SYMBOL which was not
directly below variable declaration.
Alexandre Ghiti (3):
riscv: Move kernel
y the
different zones of the vm layout.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Anup Patel
---
arch/riscv/mm/ptdump.c | 67 ++
1 file changed, 55 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
index ace74de
This new document presents the RISC-V virtual memory layout and is based
one the x86 one: it describes the different limits of the different regions
of the virtual address space.
Signed-off-by: Alexandre Ghiti
---
Documentation/riscv/index.rst | 1 +
Documentation/riscv/vm-layout.rst | 63
space, both
sv39 and sv48 kernels will be exactly the same without needing to be
relocated at runtime.
Suggested-by: Arnd Bergmann
Signed-off-by: Alexandre Ghiti
---
arch/riscv/boot/loader.lds.S| 3 +-
arch/riscv/include/asm/page.h | 18 ++-
arch/riscv/include/asm/pgtable.h
deserves a second look.
Changes in v2:
- Fix documentation about direct mapping size which is 124GB instead
of 126GB.
- Fix SPDX missing header in documentation.
- Fix another checkpatch warning about EXPORT_SYMBOL which was not
directly below variable declaration.
Alexandre Ghiti (3):
riscv
warnings about missing prototypes by declaring
the introduced functions as static.
Alexandre Ghiti (2):
riscv: Ensure page table writes are flushed when initializing KASAN
vmalloc
riscv: Cleanup KASAN_VMALLOC support
arch/riscv/mm/kasan_init.c | 61
of set_pgd that goes through all unused page table
levels, contrary to p*d_populate functions, which makes this function work
whatever the number of page table levels.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Palmer Dabbelt
---
arch/riscv/mm/kasan_init.c | 59
Make sure that writes to kernel page table during KASAN vmalloc
initialization are made visible by adding a sfence.vma.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Palmer Dabbelt
---
arch/riscv/mm/kasan_init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/riscv/mm/kasan_init.c b
of set_pgd that goes through all unused page table
levels, contrary to p*d_populate functions, which makes this function work
whatever the number of page table levels.
And finally, make sure the writes to swapper_pg_dir are visible using
an sfence.vma.
Signed-off-by: Alexandre Ghiti
---
Changes
of set_pgd that goes through all unused page table
levels, contrary to p*d_populate functions, which makes this function work
whatever the number of page table levels.
And finally, make sure the writes to swapper_pg_dir are visible using
an sfence.vma.
Signed-off-by: Alexandre Ghiti
---
arch
This new document presents the RISC-V virtual memory layout and is based
one the x86 one: it describes the different limits of the different regions
of the virtual address space.
Signed-off-by: Alexandre Ghiti
---
Documentation/riscv/index.rst | 1 +
Documentation/riscv/vm-layout.rst | 61
y the
different zones of the vm layout.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Anup Patel
---
arch/riscv/mm/ptdump.c | 67 ++
1 file changed, 55 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
index ace74de
space, both
sv39 and sv48 kernels will be exactly the same without needing to be
relocated at runtime.
Suggested-by: Arnd Bergmann
Signed-off-by: Alexandre Ghiti
---
arch/riscv/boot/loader.lds.S| 3 +-
arch/riscv/include/asm/page.h | 18 ++-
arch/riscv/include/asm/pgtable.h
deserves a second look.
Alexandre Ghiti (3):
riscv: Move kernel mapping outside of linear mapping
Documentation: riscv: Add documentation that describes the VM layout
riscv: Prepare ptdump for vm layout dynamic addresses
Documentation/riscv/index.rst | 1 +
Documentation/riscv/vm
Populate the top-level of the kernel page table to implement KASAN_VMALLOC,
lower levels are filled dynamically upon memory allocation at runtime.
Co-developed-by: Nylon Chen
Signed-off-by: Nylon Chen
Co-developed-by: Nick Hu
Signed-off-by: Nick Hu
Signed-off-by: Alexandre Ghiti
---
arch
with
for_each_mem_range()")
Signed-off-by: Alexandre Ghiti
---
arch/riscv/mm/kasan_init.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/mm/kasan_init.c b/arch/riscv/mm/kasan_init.c
index 4b9149f963d3..6d3b88f2c566 100644
--- a/arch/riscv/mm/kasan_init.c
/lkml/20200603153608.30056-1-a...@ghiti.fr/
Reported-by: Dmitry Vyukov
Signed-off-by: Alexandre Ghiti
---
arch/riscv/mm/init.c | 21 +
1 file changed, 5 insertions(+), 16 deletions(-)
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index f9f9568d689e..f81f813b9603 100644
PTE
. A . . . . R V
---[ Kasan shadow end ]---
Signed-off-by: Alexandre Ghiti
---
arch/riscv/mm/kasan_init.c | 24
1 file changed, 24 insertions(+)
diff --git a/arch/riscv/mm/kasan_init.c b/arch/riscv/mm/kasan_init.c
index b7d4d9abd144..2b196f512f07 100644
--- a
when
the kernel will get pushed to the end of the address space.
Address those problems by rewriting the kasan population function,
splitting it into subfunctions for each different page table level.
Signed-off-by: Alexandre Ghiti
---
arch/riscv/mm/kasan_init.c
Instead of hardcoding memory initialization to 0, use KASAN_SHADOW_INIT.
Signed-off-by: Alexandre Ghiti
---
arch/riscv/mm/kasan_init.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/mm/kasan_init.c b/arch/riscv/mm/kasan_init.c
index a8a2ffd9114a..7bbe09416a2e
There is no functional change here, only improvement in code readability
by adding comments to explain where the kasan constants come from and by
replacing hardcoded numerical constant by the corresponding define.
Note that the comments come from arm64.
Signed-off-by: Alexandre Ghiti
---
arch
hugepages when possible
(patch 4)
Alexandre Ghiti (4):
riscv: Improve kasan definitions
riscv: Use KASAN_SHADOW_INIT define for kasan memory initialization
riscv: Improve kasan population function
riscv: Improve kasan population by using hugepages when possible
arch/riscv/include/asm/kasan.h
. A . . . . R V
---[ Kasan shadow end ]---
Signed-off-by: Alexandre Ghiti
---
arch/riscv/mm/kasan_init.c | 101 +++--
1 file changed, 73 insertions(+), 28 deletions(-)
diff --git a/arch/riscv/mm/kasan_init.c b/arch/riscv/mm/kasan_init.c
index a8a2ffd9114a
CONFIG_DEBUG_VIRTUAL enabled, raises a WARN that is interpreted as a
kernel bug by syzbot.
Signed-off-by: Alexandre Ghiti
---
arch/riscv/include/asm/page.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
index
The kernel is now mapped at the end of the address space and it should
be accessed through this mapping only: so map the whole kernel in the
linear mapping as read only.
Signed-off-by: Alexandre Ghiti
---
arch/riscv/include/asm/page.h | 9 -
arch/riscv/mm/init.c | 29
With the arrival of sv48 and its large address space, it would be
cumbersome to statically define the unit size to use to print the different
portions of the virtual memory layout: instead, determine it dynamically.
Signed-off-by: Alexandre Ghiti
---
arch/riscv/mm/init.c | 46
Define precisely the size of the user accessible virtual space size
for sv32/39/48 mmu types and explain why the whole virtual address
space is split into 2 equal chunks between kernel and user space.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Anup Patel
Reviewed-by: Palmer Dabbelt
---
arch
Now that the mmu type is determined at runtime using SATP
characteristic, use the global variable pgtable_l4_enabled to output
mmu type of the processor through /proc/cpuinfo instead of relying on
device tree infos.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Anup Patel
Reviewed-by: Palmer
less memory
accesses in case of a TLB miss.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Anup Patel
---
arch/riscv/mm/init.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index cb23a30d9af3..f9a99cb1870b
automatically
fallback to a standard 3-level page table by folding the new PUD level into
PGDIR level. In order to detect HW capabilities at runtime, we
use SATP feature that ignores writes with an unsupported mode.
Signed-off-by: Alexandre Ghiti
---
arch/riscv/Kconfig | 6
functions into other functions that riscv
can use without duplicating code.
Signed-off-by: Alexandre Ghiti
---
include/asm-generic/pgalloc.h | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/include/asm-generic/pgalloc.h b/include/asm-generic/pgalloc.h
index
y the
different zones of the vm layout.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Anup Patel
---
arch/riscv/mm/ptdump.c | 56 ++
1 file changed, 46 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/mm/ptdump.c b/arch/riscv/mm/ptdump.c
index ace74de
Either the user specifies maximum physical memory size of 2GB or the
user lives with the system constraint which is 1/4th of maximum
addressable memory in Sv39 MMU mode (i.e. 128GB) for now.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Anup Patel
---
arch/riscv/Kconfig | 20
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