On Wed, 2020-10-14 at 08:47 +0200, Lukas Bulwahn wrote:
>
> On Tue, 13 Oct 2020, Joe Perches wrote:
>
> > On Wed, 2020-10-14 at 08:36 +0200, Lukas Bulwahn wrote:
> > > On Tue, 13 Oct 2020, Joe Perches wrote:
> > >
> > > > On Wed, 2020-10-14 at 08:21 +0200, Lukas Bulwahn wrote:
> > > > > What doe
From: lizhe
Set rp_size to zero will be ignore during remounting.
The method to identify whether we input a remounting option of
rp_size is to check if the rp_size input is zero. It can not work
well if we pass "rp_size=0".
This patch add a bool variable "set_rp_size" to fix this problem.
By t
From: lizhe
The jffs2 mount options will be ignored when remounting jffs2.
It can be easily reproduced with the steps listed below.
1. mount -t jffs2 -o compr=none /dev/mtdblockx /mnt
2. mount -o remount compr=zlib /mnt
Since ec10a24f10c8, the option parsing happens before fill_super and
then pa
On Tue, Oct 13, 2020 at 05:55:31PM +0200, Roland Scheidegger wrote:
> Hi,
>
> this commit should NOT be applied to 5.8.
> It fixes a regression introduced by
> 58e4d686d456c3e356439ae160ff4a0728940b8e (drm/ttm: cleanup
> ttm_mem_type_manager_func.get_node interface v3) which is part of 5.9
> but n
On Tue, Oct 13, 2020 at 04:42:59PM -0700, si-wei liu wrote:
>
> On 10/9/2020 7:27 PM, Jason Wang wrote:
> >
> > On 2020/10/3 下午1:02, Si-Wei Liu wrote:
> > > Pinned pages are not properly accounted particularly when
> > > mapping error occurs on IOTLB update. Clean up dangling
> > > pinned pages f
On Wed, 2020-10-14 at 08:36 +0200, Lukas Bulwahn wrote:
>
> On Tue, 13 Oct 2020, Joe Perches wrote:
>
> > On Wed, 2020-10-14 at 08:21 +0200, Lukas Bulwahn wrote:
> > > What does checkpatch.pl warn about and what does clang-format still warn
> > > about, which is generally accepted okay as style
On Wed, 14 Oct 2020 at 07:07, Anshuman Khandual
wrote:
>
>
>
> On 10/12/2020 12:59 PM, Ard Biesheuvel wrote:
> > On Tue, 6 Oct 2020 at 08:36, Anshuman Khandual
> > wrote:
> >>
> >>
> >>
> >> On 09/30/2020 01:32 PM, Anshuman Khandual wrote:
> >>> But if __is_lm_address() checks against the effecti
On Wed, 2020-10-14 at 08:21 +0200, Lukas Bulwahn wrote:
> What does checkpatch.pl warn about and what does clang-format still warn
> about, which is generally accepted okay as style in the kernel?
clang-format doesn't warn at all, it just reformats.
checkpatch using the --in-place can reformat a
The sun8i codec has three clock/sample rate domains:
- The AIF1 domain, with a sample rate equal to AIF1 LRCK
- The AIF2 domain, with a sample rate equal to AIF2 LRCK
- The SYSCLK domain, containing the ADC, DAC, and effects (AGC/DRC),
with a sample rate given by a divisor from SYSCLK. The di
Now that we guarantee that SYSCLK is running at the optimal rate when
hw_params succeeds, and that it will continue running at that rate,
SYSCLK will always be an integer multiple of BCLK. So we can always
pick the exact divider, not just the closest divider.
Acked-by: Maxime Ripard
Signed-off-by
Now that the DAI clock setup is correct for all hardware-supported PCM
formats, we can enable them in the driver. With the appropriate support
in the CPU DAI driver, this allows userspace to access the additional
formats.
Since this codec is connected to the CPU via a DAI, not directly, we do
not
On 2020/10/13 11:07, jaeg...@kernel.org wrote:
First problem is we hit BUG_ON() in f2fs_get_sum_page given EIO on
f2fs_get_meta_page_nofail().
Quick fix was not to give any error with infinite loop, but syzbot caught
a case where it goes to that loop from fuzzed image. In turned out we abused
f2
The codec's clock input is shared among all AIFs, and shared with other
audio-related hardware in the SoC, including I2S and SPDIF controllers.
To ensure sample rates selected by userspace or by codec2codec DAI links
are maintained, the clock rate must be protected while it is in use.
Signed-off-b
This introduces the pureLiFi LiFi driver for LiFi-X, LiFi-XC
and LiFi-XL USB devices.
This driver implementation has been based on the zd1211rw driver.
Driver is based on 802.11 softMAC Architecture and uses
native 802.11 for configuration and management
The driver is compiled and tested in ARM,
While another stream is active, only allow userspace to use sample rates
that are compatible with the current SYSCLK frequency. This ensures the
actual sample rate will always match what is given in hw_params.
Acked-by: Maxime Ripard
Signed-off-by: Samuel Holland
---
sound/soc/sunxi/sun8i-codec
The LRCK inversion bit has a different meaning in DSP mode: it selects
between the DSP A and DSP B formats. To support this, we need to know if
the selected format is a DSP format. One easy way to do this is to set
the format field before the clock inversion fields.
Acked-by: Maxime Ripard
Signed
The system sample rate programmed into the hardware is really a clock
divider from SYSCLK to the ADC and DAC. Since we support two SYSCLK
frequencies, we can use all sample rates corresponding to one of those
frequencies divided by any available divisor.
This commit enables support for those sampl
The AIF clock control register has the same layout for all three AIFs.
The only difference between them is that AIF3 is missing some fields. We
can reuse the same register field definitions for all three registers,
and use the DAI ID to select the correct register address.
Signed-off-by: Samuel Ho
AIF3 has some differences from AIF1 and AIF2:
- It supports one channel only
- It supports master mode only
- It is not directly connected to any of the mixers; instead all audio
goes through a mux with AIF2.
- It does not have its own clock dividers; instead it reuses AIF2 BCLK
and LRCK.
This adds support for AIF2, which is stereo and has fullly independent
clocking capability, making it very similar to AIF1.
Acked-by: Maxime Ripard
Signed-off-by: Samuel Holland
---
sound/soc/sunxi/sun8i-codec.c | 215 ++
1 file changed, 215 insertions(+)
diff -
The codec supports only power-of-two BCLK/LRCK divisors. If either the
slot width or the number of slots is not a power of two, the LRCK
divisor must be rounded up to provide enough space. To do that, use
order_base_2 (instead of ilog2, which rounds down).
Since the rounded divisor is also needed
When using the I2S, LEFT_J, or RIGHT_J format, the hardware supports
independent BCLK and LRCK inversion control. When using DSP_A or DSP_B,
LRCK inversion is not supported. The register bit is repurposed to
select between DSP_A and DSP_B. Extend the driver to support this.
Signed-off-by: Samuel H
The AIFs have a single register controlling DAI parameters in both
directions, including BCLK/LRCK divisor and word size. The DAIs produce
only noise or silence if any of these parameters is wrong. Therefore, we
need to enforce symmetry for these parameters, so starting a new
substream will not bre
The hardware supports 8 to 24-bit word sizes on all three of its DAIs,
only one of which is connected to the CPU DAI. Program the word size
based on the actual selected format, instead of assuming limitations
from another driver (which, incedentally, has patches pending to remove
that limitation).
In preparation for adding additional DAIs to this component, convert the
DAI driver definition to an array. Since this changes all of the lines
in the definition anyway, let's move it closer to the ops function
definitions, instead of on the far side of the DAPM arrays. And while
moving the DAI dri
Now that BCLK and LRCK rate calculations in the driver can handle any
hardware-supported slot width and number of slots, allow overriding
those parameters from the device tree.
Acked-by: Maxime Ripard
Signed-off-by: Samuel Holland
---
sound/soc/sunxi/sun8i-codec.c | 28 +
This series adds support the other two AIFs present in the sun8i codec,
which can be used for codec2codec DAI links.
This series first fills out the DAI driver, removing assumptions that
were made for AIF1 (16 bits, 2 channels, certain clock inversions). Some
new logic is required to handle 3 DAIs
Previously, the BCLK divisor calculation assumed zero padding and
exactly two slots. In order to support the TDM slot binding and
20/24-bit word sizes, those assumptions must be removed.
Due to hardware limitations, the BCLK/LRCK ratio is not as simple as
"slot_width * slots". However, the correct
On Tue, Oct 13, 2020 at 07:43:40PM -0700, Stephen Boyd wrote:
> Quoting Krzysztof Kozlowski (2020-10-01 09:56:46)
> > diff --git a/drivers/clk/samsung/clk-exynos-clkout.c
> > b/drivers/clk/samsung/clk-exynos-clkout.c
> > index 34ccb1d23bc3..68af082d4716 100644
> > --- a/drivers/clk/samsung/clk-exy
The new HW arbitration feature on Aspeed ast2600 will cause MAC TX to
hang when handling scatter-gather DMA. Disable the problematic feature
by setting MAC register 0x58 bit28 and bit27.
Signed-off-by: Dylan Hung
---
drivers/net/ethernet/faraday/ftgmac100.c | 5 +
drivers/net/ethernet/farad
This patch fixes the TX hang issue on Aspeed AST2600.
Two HW arbitration features are added onto ast2600, but these features will
cause MAC TX to hang when handling scatter-gather DMA. These two
problematic features can be disabled by setting MAC register 0x58 bit28
and bit27.
Dylan Hung (1):
n
allyesconfig
powerpc allmodconfig
powerpc allnoconfig
x86_64 randconfig-a004-20201013
x86_64 randconfig-a002-20201013
x86_64 randconfig-a006-20201013
x86_64 randconfig-a001-20201013
x86_64
On 10/13/20 6:11 PM, Andy Lutomirski wrote:
> I have no problem with vmalloc(), but I do have a problem with
> vfree() due to the IPIs that result. We need a cache or something.
This sounds like the kind of thing we should just build into vmalloc()
instead of having a bunch of callers implement th
On Wed, 2020-10-14 at 07:46 +0200, Lukas Bulwahn wrote:
> Just one bigger project example: Comparing clang-format suggestions on
> patches against checkpatch.pl suggestions are fine-tuning both of them to fit
> to
> the actual kernel style.
Eek no.
Mindless use of either tool isn't a great thi
On 10/13/20 10:44 PM, Ethan Zhao wrote:
This patch only reverts the commit bdb5ac85777d ?
or you'd better separate the revert and code you added.
We cannot revert the commit as it is. pcie_do_recovery()
function and Documentation/* folder changed a lot since
fatal and non-fatal error recover
When an I2C slave works, sometimes both IC_INTR_RX_FULL and
IC_INTR_STOP_DET are rising during an IRQ handle, especially when system
is busy or too late to handle interrupts.
If IC_INTR_RX_FULL is rising and the system doesn't handle immediately,
IC_INTR_STOP_DET may be rising and the system has t
lmodconfig
powerpc allnoconfig
x86_64 randconfig-a004-20201013
x86_64 randconfig-a002-20201013
x86_64 randconfig-a006-20201013
x86_64 randconfig-a001-20201013
x86_64 randconfig-a003-20201
> -Original Message-
> From: Joel Stanley
> Sent: Wednesday, October 14, 2020 1:28 PM
> To: Stephen Boyd
> Cc: Andrew Jeffery ; Michael Turquette
> ; Ryan Chen ;
> BMC-SW ; Linux ARM
> ; linux-aspeed
> ; linux-...@vger.kernel.org; Linux Kernel
> Mailing List
> Subject: Re: [PATCH 1/1] cl
Linus,
Please git pull the following tag:
git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git
for-linus-5.10b-rc1-tag
xen: branch for v5.10-rc1
It contains:
- 2 small cleanup patches
- A fix for avoiding error messages when initializing MCA banks in a
Xen dom0
- A small series for
On Tue, Oct 13, 2020 at 08:21:13AM -0700, Randy Dunlap wrote:
> On 10/13/20 8:12 AM, Mike Rapoport wrote:
> > On Tue, Oct 13, 2020 at 07:43:59AM -0700, Randy Dunlap wrote:
> >> On 10/13/20 1:09 AM, Mike Rapoport wrote:
> >>> On Mon, Oct 12, 2020 at 05:53:01PM +0800, Muchun Song wrote:
> On Mon
gcc 10 optimizes the scheduler code differently than its predecessors.
When DEBUG_SECTION_MISMATCH config is enabled, Makefile forces gcc not
to inline some functions (-fno-inline-functions-called-once). Before gcc
10, "no-inlined" __schedule starts with the usual prologue (push %bp; mov
%sp,%bp).
On 14-10-2020 07:07, Randy Dunlap wrote:
> On 10/13/20 9:56 PM, Udo van den Heuvel wrote:
>> I.e.: it looks like I will lose some funcionality when I disable
>> SND_HDA_CODEC_REALTEK.
>
> OK. At present you can't have it both ways, i.e., SND_HDA_CODEC_REALTEK
> with no LEDS. That driver apparentl
On 07. 10. 20, 16:54, Josh Poimboeuf wrote:
-ENOPARSE on $SUBJECT.
Also please address it to x...@kernel.org, I think the tip maintainers
can pick up the fix directly.
Hmm, weird, I must have sent an older version as my current patch in the
tree has:
Cc: Miroslav Benes
Cc: Josh Poimboeuf
C
On 10/12/2020 12:59 PM, Ard Biesheuvel wrote:
> On Tue, 6 Oct 2020 at 08:36, Anshuman Khandual
> wrote:
>>
>>
>>
>> On 09/30/2020 01:32 PM, Anshuman Khandual wrote:
>>> But if __is_lm_address() checks against the effective linear range instead
>>> i.e [_PAGE_OFFSET(vabits_actual)..(PAGE_END - 1
The Marvell 88E6393X device is a single-chip integration of a 11-port
Ethernet switch with eight integrated Gigabit Ethernet (GbE) transceivers
and three 10-Gigabit interfaces.
This patch adds functionalities specific to mv88e6393x family (88E6393X,
88E6193X and 88E6191X)
Signed-off-by: Pavana Sh
On 14-10-2020 06:49, Randy Dunlap wrote:
> If you disable SND_HDA_CODEC_REALTEK, then the rest of the
> LED kconfig symbols can be disabled.
Sure,
but:
# dmesg|grep audi
(...)
[ 19.971537] snd_hda_codec_generic hdaudioC0D0: ignore pin 0x7, too
many assigned pins
[ 19.973547] snd_hda_codec_g
Hi, Chunfeng:
On Tue, 2020-10-13 at 16:52 +0800, Chunfeng Yun wrote:
> Convert HDMI PHY binding to YAML schema mediatek,ufs-phy.yaml
>
> Signed-off-by: Chunfeng Yun
> ---
> v2: fix binding check warning of reg in example
> ---
> .../display/mediatek/mediatek,hdmi.txt| 17 +---
> .../bin
On 13-10-20, 17:17, Surendran K wrote:
> _setup_req(..) never returns negative value.
> Hence the condition ret < 0 is never met
The subsystem is "dmaengine", git log would tell you the tags to use
>
> Signed-off-by: Surendran K
> ---
> drivers/dma/pl330.c | 2 --
> 1 file changed, 2 deletion
On 13-10-2020 18:03, Randy Dunlap wrote:
> On 10/13/20 8:53 AM, Randy Dunlap wrote:
>> [adding LED people + list]
>>
>> On 10/13/20 6:24 AM, Udo van den Heuvel wrote:
(...)
So how do I disable this stuff?
>
> I was able to disable LEDS_CLASS and NEW_LEDS after I disabled the following
Dear Beloved Friend,
Sorry if this email came to you as a surprise,I am Dr.Dawuda Usman and
we are looking for a company or individual from your region to help us
receive investment fund .I will send you full details As soon As I hear
from you thanks.
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Thanks Mark Brown for your time !!!
On 10/13/2020 8:45 PM, Mark Brown wrote:
On Tue, Oct 13, 2020 at 07:09:46PM +0530, Srinivasa Rao Mandadapu wrote:
From: V Sujith Kumar Reddy
Disable MI2S bit clock from PAUSE/STOP/SUSPEND usecase
instead of shutdown time. Acheive this by invoking
clk_disab
I will add a dt-bindings commit for this change.
Thanks for review.
JC
On 9/28/20 9:18 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:35PM +0800, JC Kuo wrote:
>> PMC driver provides USB sleepwalk registers access to XUSB PADCTL
>> driver. This commit adds a "nvidia,pmc" property which
I will amend commit accordingly and submit a new patch.
Thanks for review.
JC
On 9/28/20 9:17 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:34PM +0800, JC Kuo wrote:
>> This commit implements a register map which grants USB (UTMI and HSIC)
>> sleepwalk registers access to USB PHY driv
commit 64fa3aff89785b5a924ce3934f6595c35b4dffee
Author: Sharon Dvir
Date: Wed Aug 17 15:35:09 2016 +0300
iwlwifi: pcie: give a meaningful name to interrupt request
perhaps unintentionally for file:
drivers/net/wireless/intel/iwlwifi/pcie/internal.h
in function static inline const char *qu
Document the higher level --insn-trace etc. perf script options.
Include the howto how to build xed into the manpage
Cc: adrian.hun...@intel.com
Signed-off-by: Andi Kleen
---
tools/perf/Documentation/perf-intel-pt.txt | 30 ++
1 file changed, 30 insertions(+)
diff --git a/t
Peter suggested that using the exclusive mode in perf could
avoid some problems with bad scheduling of groups. Exclusive
is implemented in the kernel, but wasn't exposed by the perf tool,
so hard to use without custom low level API users.
Add support for marking groups or events with :e for exclus
Hi,
Looks good to me. I add some comment. Please check them.
On 10/12/20 11:47 PM, Michael Auchter wrote:
> This patch adds an extcon driver for the TI TUSB320 USB Type-C device.
> This can be used to detect whether the port is configured as a
> downstream or upstream facing port.
>
> Signed-off
On Tue, 13 Oct 2020 15:48:52 -0400
Steven Rostedt wrote:
> From: "Steven Rostedt (VMware)"
>
> After having a typo for writing a histogram trigger.
>
> Wrote:
> echo 'hist:key=pid:ts=common_timestamp.usec' >
> events/sched/sched_waking/trigger
>
> Instead of:
> echo 'hist:key=pid:ts=comm
Asserting reset to a PLL when it's managed by hardware power sequencer would
break sequencer's state machine. Putting PLL in reset doesn't save some extra
power.
Thanks for review.
JC
On 9/28/20 9:06 PM, Thierry Reding wrote:
> On Wed, Sep 09, 2020 at 04:10:30PM +0800, JC Kuo wrote:
>> Once UPHY
On 10/13/20 3:45 PM, Michael Ellerman wrote:
Christophe Leroy writes:
Le 13/10/2020 à 09:23, Aneesh Kumar K.V a écrit :
Christophe Leroy writes:
CPU_FTR_NODSISRALIGN has not been used since
commit 31bfdb036f12 ("powerpc: Use instruction emulation
infrastructure to handle alignment faults")
On Sun, 11 Oct 2020 23:52:53 +0530, Rayagonda Kokatanur wrote:
> --- a/drivers/i2c/busses/i2c-bcm-iproc.c
> +++ b/drivers/i2c/busses/i2c-bcm-iproc.c
>
> - } else if (status & BIT(IS_S_RD_EVENT_SHIFT)) {
> - /* Start of SMBUS for Master Read */
> +
MT8192 msdc is an independent sub system, we need control more bus
clocks for it.
Add support for the additional subsys clocks to allow it to be
configured appropriately.
Signed-off-by: Wenbin Mei
Reviewed-by: Nicolas Boichat
---
drivers/mmc/host/mtk-sd.c | 74 +-
This commit adds mmc device node for mt8192
Signed-off-by: Wenbin Mei
---
arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 89 +
arch/arm64/boot/dts/mediatek/mt8192.dtsi| 34
2 files changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dt
Convert the mtk-sd binding to DT schema format using json-schema.
Signed-off-by: Wenbin Mei
Reviewed-by: Rob Herring
---
.../devicetree/bindings/mmc/mtk-sd.txt| 75
.../devicetree/bindings/mmc/mtk-sd.yaml | 165 ++
2 files changed, 165 insertions(+), 75 d
MT8192 mmc host ip is compatible with MT8183.
Add support for this.
Signed-off-by: Wenbin Mei
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
b/Documentat
Change in v7:
1)add "unevaluatedProperties" in mtk-sd.yaml
2)add Reviewed-by tag
Change in v6:
1)use devm_clk_get function for required clocks
Change in v5:
1)remove Reviewed-by tag
2)use devm_clk_bulk_get_optional instead of devm_clk_get_optional
for bulk clks
Change in v4:
1)drop "vmmc" and
Quoting Paul Cercueil (2020-09-02 18:50:44)
> The to_clk_info() previously had a BUG_ON() to check that it was only
> called for PLL clocks. Yet, all the other clocks were doing the exact
> same thing the macro does, in-line.
>
> Move the to_clk_info() macro to the top of the file, remove the
> ha
Quoting Paul Cercueil (2020-09-02 18:50:45)
> Use the readl_poll_timeout() function instead of rolling our own
> busy-wait loops. This makes the code simpler.
>
> Signed-off-by: Paul Cercueil
> ---
Applied to clk-next
Quoting Paul Cercueil (2020-09-02 18:50:47)
> The custom clocks have custom functions to round, get or set their rate.
> Therefore, we can't assume that they need the CLK_SET_RATE_PARENT flag.
>
> Signed-off-by: Paul Cercueil
> ---
Applied to clk-next
Quoting Paul Cercueil (2020-09-02 18:50:46)
> CLK_SET_RATE_GATE means that the clock must be gated when being
> reclocked. This is not the case for the PLLs in Ingenic SoCs.
>
> Signed-off-by: Paul Cercueil
> ---
Applied to clk-next
Quoting Paul Cercueil (2020-09-02 18:50:48)
> Clocks that don't have a divider are in our case all marked with the
> CLK_SET_RATE_PARENT flag. In this case, the .round_rate implementation
> should modify the value pointed to by parent_rate, in order to propagate
> the rate change to the parent, as
Quoting Navid Emamdoost (2020-08-09 16:11:58)
> In the implementation of bcm2835_register_pll(), the allocated pll is
> leaked if devm_clk_hw_register() fails to register hw. Release pll if
> devm_clk_hw_register() fails.
>
> Signed-off-by: Navid Emamdoost
> ---
Applied to clk-next
Quoting Claudiu Beznea (2020-08-24 23:59:11)
> Fix variable set but not used compilation warning.
>
> Fixes: 43b1bb4a9b3e ("clk: at91: clk-sam9x60-pll: re-factor to support plls
> with multiple outputs")
> Reported-by: kernel test robot
> Signed-off-by: Claudiu Beznea
> ---
Applied to clk-next
Quoting Claudiu Beznea (2020-08-24 23:59:09)
> There is no need to check parent_name variable while assigning it to
> init.parent_names. parent_name variable is already checked at
> the beginning of at91_clk_register_peripheral() function.
>
> Fixes: 6114067e437eb ("clk: at91: add PMC peripheral c
Quoting Claudiu Beznea (2020-08-24 23:59:10)
> SAMA5D2 datasheet specifies on chapter 33.22.8 (PMC Clock Generator
> Main Oscillator Register) that writing any value other than
> 0x37 on KEY field aborts the write operation. Use the key when
> selecting main clock parent.
>
> Fixes: 27cb1c2083373
Quoting Xu Wang (2020-09-20 20:45:22)
> In case of error, the function clk_register() returns ERR_PTR()
> and never returns NULL. The NULL test in the return value check
> should be replaced with IS_ERR().
>
> Signed-off-by: Xu Wang
> ---
Applied to clk-next
Quoting Lubomir Rintel (2020-09-25 16:39:14)
> The LCD clock dividers are apparently based on one. No datasheet,
> determined empirically, but seems to be confirmed by line 19 of lcd.fth in
> OLPC laptop's Open Firmware [1]:
>
>h# 0700 value pmua-disp-clk-sel \ PLL1 / 7 -> 113.86 MHz
>
>
Quoting Ryan Chen (2020-09-28 00:01:08)
> In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are
> default for Host SuperIO UART device, eSPI clk for Host eSPI bus access
> eSPI slave channel, those clks can't be disable should keep default,
> otherwise will affect Host side access
Quoting Qiang Zhao (2020-09-15 20:03:10)
> From: Zhao Qiang
>
> On LS2088A, Watchdog need clk divided by 32,
> so modify MAX_PLL_DIV to 32
>
> Signed-off-by: Zhao Qiang
> ---
Applied to clk-next
Quoting Serge Semin (2020-09-20 04:03:35)
> We've discovered that disabling the so called Ethernet PLL causes reset of
> the devices consuming its outgoing clock. The resets happen automatically
> even if each underlying clock gate is turned off. Due to that we can't
> disable the Ethernet PLL unti
Patch 1 is a preparatory patch to reduce conflicts. Patch 2 fixes
balance failure due to ENOSPC in btrfs/156 on arm64 systems with
pagesize=64k. Minor conflicts in fs/btrfs/block-group.c are resolved.
Thanks.
Josef Bacik (2):
btrfs: don't pass system_chunk into can_overcommit
btrfs: take overc
Quoting Alexandru Ardelean (2020-10-01 01:59:47)
> From: Lars-Peter Clausen
>
> The axi-clkgen has (optional) fractional dividers on the output clock
> divider and feedback clock divider path. Utilizing the fractional dividers
> allows for a better resolution of the output clock, being able to
>
Quoting Alexandru Ardelean (2020-10-01 01:59:48)
> From: Lars-Peter Clausen
>
> Using the fractional dividers requires some additional power bits to be
> set.
>
> The fractional power bits are not documented and the current heuristic
> for setting them seems be insufficient for some cases. Just
From: Josef Bacik
commit 9f246926b4d5db4c5e8c78e4897757de26c95be6 upstream
We have the space_info, we can just check its flags to see if it's the
system chunk space info.
Reviewed-by: Nikolay Borisov
Reviewed-by: Qu Wenruo
Reviewed-by: Johannes Thumshirn
Signed-off-by: Josef Bacik
Reviewed-
From: Josef Bacik
commit a30a3d2067536cbcce26c055e70cc3a6ae4fd45c upstream
inc_block_group_ro does a calculation to see if we have enough room left
over if we mark this block group as read only in order to see if it's ok
to mark the block group as read only.
The problem is this calculation _onl
Quoting Krzysztof Kozlowski (2020-10-01 09:56:45)
> The Exynos clock output (clkout) driver uses same register address space
> (Power Management Unit address space) as Exynos PMU driver and same set
> of compatibles. It was modeled as clock provider instantiated with
> CLK_OF_DECLARE_DRIVE().
>
>
Quoting Krzysztof Kozlowski (2020-10-01 09:56:46)
> diff --git a/drivers/clk/samsung/clk-exynos-clkout.c
> b/drivers/clk/samsung/clk-exynos-clkout.c
> index 34ccb1d23bc3..68af082d4716 100644
> --- a/drivers/clk/samsung/clk-exynos-clkout.c
> +++ b/drivers/clk/samsung/clk-exynos-clkout.c
> @@ -28,41
1. Support for some new features
2. fix up some error
Chang in V4:
[PATCH v3 1/5] : Update the commit message.
[PATCH v3 2/5] : Update the commit message.
Chang in V3:
[PATCH v2 3/6] : It's been merged
So rebased and resubmit.
Chang in V2:
[PATCH v2 5/6] : fix up the Register error, and add dela
support fractional divider with one level and two level parent clock
.i.e:
normal fractional divider is:
|--\
---[GPLL]---| \ |--\
---[CPLL]---|mux|--[GATE]--[DIV]---| \
---[NPLL]---| /|
If setting freq is not support in rockchip_pll_rate_table,
It can calculate and set pll params by auto.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk-pll.c | 215 ++---
1 file changed, 200 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/rockchip/cl
Can you check your get_maintainers script invocation? Not sure why arm64
maintainers are Cced on a clk patch.
Quoting Varadarajan Narayanan (2020-09-27 22:15:34)
> Add programming sequence support for managing the Stromer
> PLLs.
>
> Signed-off-by: Varadarajan Narayanan
> ---
> drivers/clk/qcom
Rockchip socs often have some tiny number of muxes not controlled from
the core clock controller but through bits set in the pmugrf.
Use MUXPMUGRF() to cover this special clock-type.
Signed-off-by: Elaine Zhang
---
drivers/clk/rockchip/clk.c | 9 +
drivers/clk/rockchip/clk.h | 17 ++
set pll sequence:
->set pll to slow mode or other plls
->set pll down
->set pll params
->set pll up
->wait pll lock status
->set pll to normal mode
To slove the system error:
wait_pll_lock: timeout waiting for pll to lock
pll_set_params: pll update u
>From Rockchips fractional divider usage, some clocks can be generated
by fractional divider, but the input clock frequency of fractional
divider should be less than a specified value.
.i.e:
|--\
---[GPLL]---| \ |--\
---[CPLL]---|mux|--[GATE]--[DIV
Reviewed-by: Alex Shi
在 2020/10/14 上午10:20, Bailu Lin 写道:
> This is a Chinese translated version of
> Documentation/arm64/hugetlbpage.rst
>
> Signed-off-by: Bailu Lin
> ---
> Changes in v3:
> - Modify a translation as Alex sugguested.
> Changes in v2:
> - Fix Sphinx 2.4.4's waring by increa
On Tue, 2020-10-13 at 17:10 +0200, Matthias Brugger wrote:
>
> On 12/10/2020 14:45, Wenbin Mei wrote:
> > MT8192 msdc is an independent sub system, we need control more bus
> > clocks for it.
> > Add support for the additional subsys clocks to allow it to be
> > configured appropriately.
> >
> >
Quoting Varadarajan Narayanan (2020-09-27 22:15:36)
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 0583273..d1a2504 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -155,6 +155,14 @@ config IPQ_GCC_8074
> i2c, USB, SD/eMMC, etc. Sel
Yes, it's safe to apply "clk: tegra: Don't enable PLLE HW sequencer at init"
before the others have applied. Disabling PLLE hardware power sequencer will not
cause any functionality problem to XUSB/PCIE/SATA. The only thing changed is
PLLE won't be powered off by hardware when all clients are in lo
> On Sun, Oct 11, 2020 at 08:54:38AM -0700, t...@redhat.com wrote:
> > From: Tom Rix
> >
> > The clang build reports this warning
> >
> > fw.c:1485:21: warning: address of array 'rtwdev->chip->fw_fifo_addr'
> > will always evaluate to 'true'
> > if (!rtwdev->chip->fw_fifo_addr) {
> >
>
This is a Chinese translated version of
Documentation/arm64/hugetlbpage.rst
Signed-off-by: Bailu Lin
---
Changes in v3:
- Modify a translation as Alex sugguested.
Changes in v2:
- Fix Sphinx 2.4.4's waring by increasing underline' size.
---
Documentation/arm64/hugetlbpage.rst | 2 +
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