Quoting Ryan Chen (2020-09-28 00:01:08) > In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are > default for Host SuperIO UART device, eSPI clk for Host eSPI bus access > eSPI slave channel, those clks can't be disable should keep default, > otherwise will affect Host side access SuperIO and SPI slave device. > > Signed-off-by: Ryan Chen <ryan_c...@aspeedtech.com> > ---
Is there resolution on this thread?
