On 27/09/20 03:51, Qi, Yadong wrote:
>> Subject: RE: [PATCH] KVM: x86: emulate wait-for-SIPI and SIPI-VMExit
>>
>>> Again, this looks good but it needs testcases.
>>
>> Yes, the unit test development is WIP.
>>
>
> Hi, Paolo
>
> I have sent out the unit test patch.
> https://patchwork.kernel.org/
On 26/09/20 16:26, Joseph Salisbury wrote:
> From: Joseph Salisbury
>
> In the architecture independent version of hyperv-tlfs.h, commit
> c55a844f46f958b
> removed the "X64" in the symbol names so they would make sense for both x86
> and
> ARM64. That commit added aliases with the "X64" in th
The iommu-dma constrains IOVA allocation based on the domain geometry
that the driver reports. Update domain geometry everytime a domain is
attached to or detached from a device.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel/iommu.c | 16 ++--
1 file changed, 14 insertions(+), 2 de
From: Tom Murphy
Allow the dma-iommu api to use bounce buffers for untrusted devices.
This is a copy of the intel bounce buffer code.
Signed-off-by: Tom Murphy
Co-developed-by: Lu Baolu
Signed-off-by: Lu Baolu
---
drivers/iommu/dma-iommu.c | 163 +++---
1 file
Yep, I am think the same question, is there any other files better to put this
function ?
How about pci.c ?
Thanks,
Ethan
-Original Message-
From: Christoph Hellwig
Sent: Sunday, September 27, 2020 2:24 PM
To: Zhao, Haifeng
Cc: bhelg...@google.com; ooh...@gmail.com; rus...@russell.cc
On 2020/9/25 23:54, Marc Zyngier wrote:
> On Thu, 24 Sep 2020 15:17:48 +0800, Zhen Lei wrote:
>> v5 --> v6:
>> 1. add Reviewed-by: Rob Herring for Patch 4.
>> 2. Some modifications are made to Patch 5:
>>1) add " |" for each "description:" property if its content exceeds one
>> line,
>>
From: Tvrtko Ursulin
A couple small tweaks are needed to make the test build and run
on current kernels.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Maor Gottlieb
Signed-off-by: Leon Romanovsky
---
tools/testing/scatterlist/Makefile | 3 ++-
tools/testing/scatterlist/linux/mm.h | 35
From: Maor Gottlieb
Extend __sg_alloc_table_from_pages to support dynamic allocation of
SG table from pages. It should be used by drivers that can't supply
all the pages at one time.
This function returns the last populated SGE in the table. Users should
pass it as an argument to the function fr
From: Tvrtko Ursulin
Instead of just asserting dump some more useful info about what the test
saw versus what it expected to see.
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Maor Gottlieb
Signed-off-by: Leon Romanovsky
---
tools/testing/scatterlist/main.c | 44 --
From: Leon Romanovsky
Changelog:
v4:
* Fixed formatting in first patch.
* Added fix (clear tmp_netnts) in first patch to fix i915 failure.
* Added test patches
v3: https://lore.kernel.org/linux-rdma/20200922083958.2150803-1-l...@kernel.org/
* Squashed Christopher's suggestion to avoid introd
From: Maor Gottlieb
Remove the implementation of ib_umem_add_sg_table and instead
call to __sg_alloc_table_from_pages which already has the logic to
merge contiguous pages.
Besides that it removes duplicated functionality, it reduces the
memory consumption of the SG table significantly. Prior to
Combining the sg segments exposes a bug in the Intel i915 driver which
causes visual artifacts and the screen to freeze. This is most likely
because of how the i915 handles the returned list. It probably doesn't
respect the returned value specifying the number of elements in the list
and instead de
Hi,
The previous post of this series could be found here.
https://lore.kernel.org/linux-iommu/20200912032200.11489-1-baolu...@linux.intel.com/
This version introduce a new patch [4/7] to fix an issue reported here.
https://lore.kernel.org/linux-iommu/51a1baec-48d1-c0ac-181b-1fba92aa4...@linux.i
On 25/09/2020 10:50, Pali Rohár wrote:
eMMC definitions in files armada-3720-espressobin-emmc.dts and
armada-3720-espressobin-v7-emmc.dts is same. So move it into common
armada-3720-espressobin.dtsi file with status "disabled".
This change simplifies eMMC variants of DTS files for Espressobin.
Signed-off-by: Ryan Kosta
---
drivers/staging/nvec/nvec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c
index 360ec040774..a80996b2f5c 100644
--- a/drivers/staging/nvec/nvec.c
+++ b/drivers/staging/nvec/nvec.c
@@ -289
Lock(&iommu->lock) without disabling irq causes lockdep warnings.
[ 12.703950]
[ 12.703962] WARNING: possible irq lock inversion dependency detected
[ 12.703975] 5.9.0-rc6+ #659 Not tainted
[ 12.703983] --
Convert the Hisilicon Hi6220 Power Always ON domain controller binding to
DT schema format using json-schema.
Signed-off-by: Zhen Lei
---
.../controller/hi3620/hisilicon,hi6220-aoctrl.txt | 18 --
.../controller/hi3620/hisilicon,hi6220-aoctrl.yaml | 42 ++
2 files ch
Convert the Hisilicon Hi3798CV200 Peripheral Controller binding to DT
schema format using json-schema.
Signed-off-by: Zhen Lei
---
.../controller/hisilicon,hi3798cv200-perictrl.txt | 21 --
.../controller/hisilicon,hi3798cv200-perictrl.yaml | 45 ++
2 files changed,
Convert the Hisilicon HiP05/HiP06 PCIe-SAS subsystem controller binding
to DT schema format using json-schema.
Signed-off-by: Zhen Lei
---
.../controller/hisilicon,pcie-sas-subctrl.txt | 15 -
.../controller/hisilicon,pcie-sas-subctrl.yaml | 37 ++
2 files ch
Convert the Hisilicon peripheral misc control register binding to DT
schema format using json-schema.
Signed-off-by: Zhen Lei
---
.../arm/hisilicon/controller/hisilicon,pctrl.txt | 13 -
.../arm/hisilicon/controller/hisilicon,pctrl.yaml | 34 ++
2 files changed, 34
Convert the Hisilicon Bootwrapper boot method binding to DT schema format
using json-schema.
The property boot-method contains two groups of physical address range
information: bootwrapper and relocation. The "uint32-array" type is not
suitable for it, because the field "address" and "size" may oc
Convert the Hisilicon Hi6220 Media domain controller binding to DT schema
format using json-schema.
Signed-off-by: Zhen Lei
---
.../hi3620/hisilicon,hi6220-mediactrl.txt | 18 --
.../hi3620/hisilicon,hi6220-mediactrl.yaml | 42 ++
2 files changed, 42
Convert the Hisilicon HiP05/HiP06 DSA subsystem controller binding to DT
schema format using json-schema.
Signed-off-by: Zhen Lei
---
.../hisilicon/controller/hisilicon,dsa-subctrl.txt | 15 -
.../controller/hisilicon,dsa-subctrl.yaml | 37 ++
2 files changed
The field of 'q_usage_counter' is always fetched in fast path of every
block driver, and move it into front of 'request_queue', so it can be
fetched into 1st cacheline of 'request_queue' instance.
Tested-by: Veronika Kabatova
Reviewed-by: Christoph Hellwig
Cc: Sagi Grimberg
Cc: Tejun Heo
Cc: C
From: Kefeng Wang
Add sd5203.dts for Hisilicon SD5203 SoC platform.
Signed-off-by: Kefeng Wang
Signed-off-by: Zhen Lei
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sd5203.dts | 96
2 files changed, 98 insertions(+)
create mode 100644
From: Kefeng Wang
Enable support for the Hisilicon SD5203 SoC. The core is ARM926EJ-S.
Signed-off-by: Kefeng Wang
Signed-off-by: Zhen Lei
---
arch/arm/mach-hisi/Kconfig | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/
Convert Hisilicon SoC bindings to DT schema format using json-schema.
Signed-off-by: Zhen Lei
---
.../bindings/arm/hisilicon/hisilicon.txt | 57
.../bindings/arm/hisilicon/hisilicon.yaml | 77 ++
2 files changed, 77 insertions(+), 57 deleti
Convert the Hisilicon Hi6220 SRAM controller binding to DT schema format
using json-schema.
Signed-off-by: Zhen Lei
---
.../hi3620/hisilicon,hi6220-sramctrl.txt | 16 -
.../hi3620/hisilicon,hi6220-sramctrl.yaml | 38 ++
2 files changed, 38 insertion
Split the devicetree bindings of each Hisilicon controller from
hisilicon.txt into a separate file, the file name is the compatible name
attach the .txt file name extension.
All Hi6220 dedicated controllers are grouped into subdirectory "hi3620".
All HiPxx dedicated controllers are grouped into s
Convert the Hisilicon CPU controller binding to DT schema format using
json-schema.
Signed-off-by: Zhen Lei
---
.../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 ---
.../hisilicon/controller/hisilicon,cpuctrl.yaml| 28 ++
2 files changed, 28 insertions(+), 8 de
Convert the Hisilicon system controller and its variants binding to DT
schema format using json-schema. All of them are grouped into one yaml
file, to help users understand differences and avoid repeated
descriptions.
Signed-off-by: Zhen Lei
---
.../controller/hi3620/hisilicon,hi6220-sysctrl.txt
Convert the Hisilicon Hip06 SoCs implement a Low Pin Count (LPC)
controller binding to DT schema format using json-schema.
Signed-off-by: Zhen Lei
---
.../arm/hisilicon/hisilicon-low-pin-count.txt | 33
.../arm/hisilicon/hisilicon-low-pin-count.yaml | 63 +++
The compatible name "hisilicon,hip01" does not exist in any C file, and
it is not mentioned in the description file "hisilicon.txt". Delete it.
Fixes: 56a9c909d88a ("ARM: dts: Add hip01-ca9x2 dts file")
Signed-off-by: Zhen Lei
---
arch/arm/boot/dts/hip01-ca9x2.dts | 2 +-
1 file changed, 1 inser
Convert the Hisilicon Fabric controller binding to DT schema format using
json-schema.
Signed-off-by: Zhen Lei
---
.../controller/hipxx/hisilicon,hip04-fabric.txt| 5 -
.../controller/hipxx/hisilicon,hip04-fabric.yaml | 26 ++
2 files changed, 26 insertions(+), 5 d
Convert the Hisilicon Hi6220 Power Management domain controller binding
to DT schema format using json-schema.
Signed-off-by: Zhen Lei
---
.../controller/hi3620/hisilicon,hi6220-pmctrl.txt | 18 --
.../controller/hi3620/hisilicon,hi6220-pmctrl.yaml | 42 ++
2 files c
'struct percpu_ref' is often embedded into one user structure, and the
instance is usually referenced in fast path, however actually only
'percpu_count_ptr' is needed in fast path.
So move other fields into one new structure of 'percpu_ref_data', and
allocate it dynamically via kzalloc(), then mem
Convert the Hisilicon HiP05/HiP06 PERI subsystem controller binding to DT
schema format using json-schema.
Signed-off-by: Zhen Lei
---
.../controller/hisilicon,peri-subctrl.txt | 16 --
.../controller/hisilicon,peri-subctrl.yaml | 34 ++
2 files chang
Add devicetree binding for Hisilicon SD5203 SoC.
Signed-off-by: Zhen Lei
---
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hisilicon.yaml
b/Documentation/devicetree/bindings/
MD code uses perpcu-refcount internal to check if this percpu-refcount
variable is initialized, this way is a hack.
Add percpu_ref_is_initialized for MD so that the hack can be avoided.
Acked-by: Song Liu
Suggested-by: Jens Axboe
Tested-by: Veronika Kabatova
Cc: Song Liu
Cc: linux-r...@vger.k
From: Kefeng Wang
Add support of early console for SD5203.
Signed-off-by: Kefeng Wang
Signed-off-by: Zhen Lei
---
arch/arm/Kconfig.debug | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 8a66a4e3549..d27a7
Hi,
The 1st patch removes memory footprint of percpu_ref in fast path
from 7 words to 2 words, since it is often used in fast path and
embedded in user struct.
The 2nd patch moves .q_usage_counter to 1st cacheline of
'request_queue'.
Simple test on null_blk shows ~2% IOPS boost on one 16cores(tw
v2 --> v3:
1. Convert hisilicon.txt to hisilicon.yaml. Because there are many kinds
of Hisilicon controllers in it, so split each of them into a separate
file first. Then I convert all of them to DT schema format, and also
convert the other files in directory "../bindings/arm/hisilicon/".
On Sat, Sep 26, 2020 at 03:28:32PM -0700, Linus Torvalds wrote:
> On Fri, Sep 25, 2020 at 6:15 PM Linus Torvalds
> wrote:
> >
> > I think that over the weekend I'll do Peter's version but with the
> > "page_mapcount() == 1" check, because I'm starting to like that
> > better than the mm->has_pinn
> +#ifdef CONFIG_PCIE_DPC
> +static inline bool pci_wait_port_outdpc(struct pci_dev *pdev)
> +{
> + u16 cap = pdev->dpc_cap, status;
> + u16 loop = 0;
> +
> + if (!cap) {
> + pci_WARN_ONCE(pdev, !cap, "No DPC capability initiated\n");
> + return false;
> + }
Add i.MX8MQ dev/sys addr map and configuration data structure
i.MX8MM share i.MX8MQ settings.
Reviewed-by: Richard Zhu
Signed-off-by: Peng Fan
---
drivers/remoteproc/imx_rproc.c | 40 ++
1 file changed, 40 insertions(+)
diff --git a/drivers/remoteproc/imx_rproc.
We might need to map an region multiple times, becaue the region might
be shared between remote processors, such i.MX8QM with dual M4 cores.
So use devm_ioremap, not devm_ioremap_resource.
Reviewed-by: Oleksij Rempel
Reviewed-by: Richard Zhu
Signed-off-by: Peng Fan
---
drivers/remoteproc/imx_r
The hook is used to parse memory-regions and load resource table
from the address the remote processor published.
Reviewed-by: Richard Zhu
Signed-off-by: Peng Fan
---
drivers/remoteproc/imx_rproc.c | 97 ++
1 file changed, 97 insertions(+)
diff --git a/drivers/r
To arm64, "dc zva, dst" is used in memset.
Per ARM DDI 0487A.j, chapter C5.3.8 DC ZVA, Data Cache Zero by VA,
"If the memory region being zeroed is any type of Device memory,
this instruction can give an alignment fault which is prioritized
in the same way as other alignment faults that are d
It is using devm_ioremap, so not devm_ioremap_resource. Correct
the error message and print out sa/size.
Acked-by: Richard Zhu
Reviewed-by: Mathieu Poirier
Signed-off-by: Peng Fan
---
drivers/remoteproc/imx_rproc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/rem
Add elf memory hooks according to elf_mem_hook setting in the platform
configuration dcfg.
Acked-by: Richard Zhu
Signed-off-by: Peng Fan
---
drivers/remoteproc/imx_rproc.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/
Use virtio/mailbox to build connection between Remote Proccessors
and Linux. Add delayed work to handle incoming messages.
Reviewed-by: Richard Zhu
Signed-off-by: Peng Fan
---
drivers/remoteproc/imx_rproc.c | 112 -
1 file changed, 109 insertions(+), 3 deletions(
V2:
Rebased on linux-next
Dropped early boot feature to make patchset simple.
Drop rsc-da
V1:
https://patchwork.kernel.org/cover/11682461/
This patchset is to support i.MX8MQ/M coproc.
The early boot feature was dropped to make the patchset small in V2.
Since i.MX specific TCM memory require
Hi Jonathan,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: a1bffa48745afbb54cb4f873bba783b2ae8be042
commit: 7a3a7671fa6c7e90aff5f4242add2a40587b85ef ASoC: samsung: Add driver for
Aries boards
date: 3 months ago
From: Zqiang
There is a small race window when a delayed work is being canceled and
the work still might be queued from the timer_fn:
CPU0CPU1
kthread_cancel_delayed_work_sync()
__kthread_cancel_work_sync()
__kthread_cancel_work()
On Sun, Sep 27, 2020 at 07:45:20AM +0200, Greg Kroah-Hartman wrote:
> On Sun, Sep 27, 2020 at 02:57:56AM +0900, Vincent Mailhol wrote:
> > The ES58X devices are incorrectly recognized as USB Modem (CDC ACM),
> > preventing the etas-es58x module to load.
> >
> > Thus, these have been added
> > to t
On Sun, 2020-09-27 at 11:09 +0530, Anup Patel wrote:
> The NoMMU kernel is broken for QEMU virt machine from Linux-5.9-rc6
> because clint_time_val is used even before CLINT driver is probed
> at following places:
> 1. rand_initialize() calls get_cycles() which in-turn uses
>clint_time_val
> 2.
On Sat, 2020-09-26 at 22:46 -0700, Palmer Dabbelt wrote:
> On Sat, 26 Sep 2020 22:39:16 PDT (-0700), Anup Patel wrote:
> > The NoMMU kernel is broken for QEMU virt machine from Linux-5.9-rc6
> > because clint_time_val is used even before CLINT driver is probed
> > at following places:
> > 1. rand_i
On Sat, Sep 26, 2020 at 12:22:19PM -0700, Moritz Fischer wrote:
> Hi Greg,
>
> On Sat, Sep 26, 2020 at 08:09:13AM +0200, Greg KH wrote:
> > On Sat, Sep 26, 2020 at 10:23:46AM +0800, Xu Yilun wrote:
> > > Hi greg,
> > >
> > > About the bus naming, I summarized some questions we've discussed to che
Hi Marcel,
> On 26 September 2020 at 1:34, Marcel Holtmann wrote:
>
> Hi Alex,
>
> >>> When someone attacks the service provider, it creates connection,
> >>> authenticates. Then it requests key size of one byte and it identifies
> >>> the key with brute force methods.
> >>>
> >>> After l2cap in
On Sat, 26 Sep 2020 22:39:16 PDT (-0700), Anup Patel wrote:
The NoMMU kernel is broken for QEMU virt machine from Linux-5.9-rc6
because clint_time_val is used even before CLINT driver is probed
at following places:
1. rand_initialize() calls get_cycles() which in-turn uses
clint_time_val
2. bo
At 2020-09-24T10:06:23+0200, Michael Kerrisk (man-pages) wrote:
> Thanks for the interesting history, Branden!
Hi, Michael. And you're welcome! I often wonder if I test people's
patience with my info dumps but I try to show my work when making
claims.
> From time toi time I wonder if the functi
On Sun, Sep 27, 2020 at 02:57:56AM +0900, Vincent Mailhol wrote:
> The ES58X devices are incorrectly recognized as USB Modem (CDC ACM),
> preventing the etas-es58x module to load.
>
> Thus, these have been added
> to the ignore list in drivers/usb/class/cdc-acm.c
>
> Signed-off-by: Vincent Mailho
On Sun, Sep 27, 2020 at 08:24:39AM +0800, Liu, Shuo A wrote:
> Ping...
It's been less than a week since you sent this. Please relax and if you
really need reviews, get them from within Intel, where you can impose a
deadline on those developers. Otherwise, your patch is in good company:
The NoMMU kernel is broken for QEMU virt machine from Linux-5.9-rc6
because clint_time_val is used even before CLINT driver is probed
at following places:
1. rand_initialize() calls get_cycles() which in-turn uses
clint_time_val
2. boot_init_stack_canary() calls get_cycles() which in-turn
use
On Sat, 26 Sep 2020 22:38:17 PDT (-0700), a...@brainfault.org wrote:
On Sun, Sep 27, 2020 at 5:50 AM Palmer Dabbelt wrote:
On Sat, 26 Sep 2020 03:31:29 PDT (-0700), Damien Le Moal wrote:
> On Sat, 2020-09-26 at 15:51 +0530, Anup Patel wrote:
>> The NoMMU kernel is broken for QEMU virt machine
On Sat, 26 Sep 2020 22:35:39 PDT (-0700), a...@brainfault.org wrote:
On Sun, Sep 27, 2020 at 5:50 AM Palmer Dabbelt wrote:
On Sat, 26 Sep 2020 03:31:29 PDT (-0700), Damien Le Moal wrote:
> On Sat, 2020-09-26 at 15:51 +0530, Anup Patel wrote:
>> The NoMMU kernel is broken for QEMU virt machine
On Sun, Sep 27, 2020 at 5:50 AM Palmer Dabbelt wrote:
>
> On Sat, 26 Sep 2020 03:31:29 PDT (-0700), Damien Le Moal wrote:
> > On Sat, 2020-09-26 at 15:51 +0530, Anup Patel wrote:
> >> The NoMMU kernel is broken for QEMU virt machine from Linux-5.9-rc6
> >> because the get_cycles() and friends are
On Sun, Sep 27, 2020 at 5:50 AM Palmer Dabbelt wrote:
>
> On Sat, 26 Sep 2020 03:31:29 PDT (-0700), Damien Le Moal wrote:
> > On Sat, 2020-09-26 at 15:51 +0530, Anup Patel wrote:
> >> The NoMMU kernel is broken for QEMU virt machine from Linux-5.9-rc6
> >> because the get_cycles() and friends are
Rafael Aquini writes:
> On Fri, Sep 25, 2020 at 11:21:58AM +0800, Huang, Ying wrote:
>> Rafael Aquini writes:
>> >> Or, can you help to run the test with a debug kernel based on upstream
>> >> kernel. I can provide some debug patch.
>> >>
>> >
>> > Sure, I can set your patches to run with the
When we see 'can't recover (no error_detected callback)' on console,
Maybe the reason is io state is not changed by calling
pci_dev_set_io_state(), that is confused. fix it.
Signed-off-by: Ethan Zhao
Tested-by: Wen Jin
Tested-by: Shanshan Zhang
---
Chagnes:
V2: no change.
V3: no change.
dri
During DPC error injection test we found there is race condition between
pciehp and DPC driver, NULL pointer reference caused panic as following
# setpci -s 64:02.0 0x196.w=000a
// 64:02.0 is rootport has DPC capability
# setpci -s 65:00.0 0x04.w=0544
// 65:00.0 is NVMe SSD populated in abov
When uncorrectable error happens, AER driver and DPC driver interrupt
handlers likely call
pcie_do_recovery()
->pci_walk_bus()
->report_frozen_detected()
with pci_channel_io_frozen the same time.
If pci_dev_set_io_state() return true even if the original state is
pci_channel_io_froz
This simple patch set fixed some serious security issues found when DPC
error injection and NVMe SSD hotplug brute force test were doing -- race
condition between DPC handler and pciehp, AER interrupt handlers, caused
system hang and system with DPC feature couldn't recover to normal
working state
When root port has DPC capability and it is enabled, then triggered by
errors, DPC DLLSC and PDC interrupts will be sent to DPC driver, pciehp
driver at the same time.
That will cause following result:
1. Link and device are recovered by hardware DPC and software DPC driver,
device
isn't re
Once root port DPC capability is enabled and triggered, at the beginning
of DPC is triggered, the DPC status bits are set by hardware and then
sends DPC/DLLSC/PDC interrupts to OS DPC and pciehp drivers, it will
take the port and software DPC interrupt handler 10ms to 50ms (test data
on ICS(Ice Lak
😊 definitely simpler !
-Original Message-
From: Joe Perches
Sent: Sunday, September 27, 2020 12:17 PM
To: Zhao, Haifeng ; bhelg...@google.com;
ooh...@gmail.com; rus...@russell.cc; lu...@wunner.de;
andriy.shevche...@linux.intel.com; stuart.w.ha...@gmail.com;
mr.nuke...@gmail.com; mika
Hi Arnd,
> Subject: Re: [PATCH 0/5] Add noncoherent platform support for vop driver
>
> On Fri, Sep 25, 2020 at 9:27 AM Sherry Sun wrote:
> >
> > Change the way of allocating vring to support noncoherent platform for
> > vop driver, and add some related dma changes to make sure noncoherent
> > p
When root port has DPC capability and it is enabled, then triggered by
errors, DPC DLLSC and PDC interrupts will be sent to DPC driver, pciehp
driver at the same time.
That will cause following result:
1. Link and device are recovered by hardware DPC and software DPC driver,
device
isn't re
On Sat, 2020-09-26 at 23:19 +0200, Arnd Bergmann wrote:
> On Sat, Sep 19, 2020 at 7:26 AM Christoph Hellwig wrote:
> > On Fri, Sep 18, 2020 at 02:15:43PM +0200, Arnd Bergmann wrote:
[]
>
> > > + return ioc;
> > > +out:
> > > + kfree(ioc);
> > > +
> > > + return ERR_PTR(err);
> >
> >
Hi Leonard,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: a1bffa48745afbb54cb4f873bba783b2ae8be042
commit: 5173a9756c8df9c387e04e49da0c4061951bbfec PM / devfreq: Add generic imx
bus scaling driver
date: 4 months
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: a1bffa48745afbb54cb4f873bba783b2ae8be042
commit: 7a3a7671fa6c7e90aff5f4242add2a40587b85ef ASoC: samsung: Add driver for
Aries boards
date: 3 months ago
config: x86_64-randconfig-a001-20200927 (attached as
On Sat, 2020-09-26 at 23:28 -0400, Ethan Zhao wrote:
> simplify the pci_dev_set_io_state() function to only return true
> when dev->error_state is changed.
[]
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
[]
> @@ -362,35 +362,11 @@ static inline bool pci_dev_set_io_state(struct pci_dev
> *d
The existing macro uses duplicate the index value so
move the index into the macro to reduce any possible
copy/paste and typo defects.
Miscellanea:
o Neaten macro
Signed-off-by: Joe Perches
---
sound/soc/qcom/qdsp6/q6afe-clocks.c | 191 ++---
---
1 file changed, 93
During DPC error injection test we found there is race condition between
pciehp and DPC driver, NULL pointer reference caused panic as following
# setpci -s 64:02.0 0x196.w=000a
// 64:02.0 is rootport has DPC capability
# setpci -s 65:00.0 0x04.w=0544
// 65:00.0 is NVMe SSD populated in abov
Hi Greg,
This is the second set of MHI patches for v5.10. The summary is below:
* Fixed the format specifier used in debugfs interface. The issue was
identified by building for ARM32 machine.
NOTE: I've sent this patch separately for review.
* Removed the auto-start option for MHI channels. T
From: Loic Poulain
Start MHI device channels so that transfers can be performed.
The MHI stack does not auto-start channels anymore.
Signed-off-by: Loic Poulain
Reviewed-by: Manivannan Sadhasivam
Acked-by: David S. Miller
Signed-off-by: Manivannan Sadhasivam
---
net/qrtr/mhi.c | 5 +
1
From: Loic Poulain
There is really no point having an auto-start for channels.
This is confusing for the device drivers, some have to enable the
channels, others don't have... and waste resources (e.g. pre allocated
buffers) that may never be used.
This is really up to the MHI device(channel) dr
From: Hemant Kumar
Currently this macro is defined in internal MHI header as
a TRE length mask. Moving it to external header allows MHI
client drivers to set this upper bound for the transmit
buffer size.
Signed-off-by: Hemant Kumar
Reviewed-by: Manivannan Sadhasivam
Signed-off-by: Manivannan
From: Loic Poulain
This value was missing in the channel debugfs output.
Signed-off-by: Loic Poulain
Reviewed-by: Manivannan Sadhasivam
Signed-off-by: Manivannan Sadhasivam
---
drivers/bus/mhi/core/debugfs.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/bus
For exposing the addresses of read/write pointers and doorbell register,
let's use the correct format specifiers. This fixes the following issues
generated using W=1 build in ARM32 and reported by Kbuild bot:
All warnings (new ones prefixed by >>):
>> drivers/bus/mhi/core/debugfs.c:75:7: warning:
Hi Andre,
On Tue, Sep 22, 2020 at 11:12:25AM +0100, Andre Przywara wrote:
> The Scalable Vector Extension (SVE) is an ARMv8 architecture extension
> that introduces very long vector operations (up to 2048 bits).
> The SPE profiling feature can tag SVE instructions with additional
> properties like
When we see 'can't recover (no error_detected callback)' on console,
Maybe the reason is io state is not changed by calling
pci_dev_set_io_state(), that is confused. fix it.
Signed-off-by: Ethan Zhao
Tested-by: Wen Jin
Tested-by: Shanshan Zhang
---
Chagnes:
V2: no change.
drivers/pci/pcie/err
When uncorrectable error happens, AER driver and DPC driver interrupt
handlers likely call
pcie_do_recovery()
->pci_walk_bus()
->report_frozen_detected()
with pci_channel_io_frozen the same time.
If pci_dev_set_io_state() return true even if the original state is
pci_channel_io_froz
Once root port DPC capability is enabled and triggered, at the beginning
of DPC is triggered, the DPC status bits are set by hardware and then
sends DPC/DLLSC/PDC interrupts to OS DPC and pciehp drivers, it will
take the port and software DPC interrupt handler 10ms to 50ms (test data
on ICS(Ice Lak
This simple patch set fixed some serious security issues found when DPC
error injection and NVMe SSD hotplug brute force test were doing -- race
condition between DPC handler and pciehp, AER interrupt handlers, caused
system hang and system with DPC feature couldn't recover to normal
working state
Dear Friend,
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On Tue, Sep 22, 2020 at 11:12:24AM +0100, Andre Przywara wrote:
> When SPE records a physical address, it can additionally tag the event
> with information from the Memory Tagging architecture extension.
>
> Decode the two additional fields in the SPE event payload.
>
> Signed-off-by: Andre Przyw
randconfig-a004-20200927
i386 randconfig-a005-20200927
i386 randconfig-a001-20200927
i386 randconfig-a002-20200926
i386 randconfig-a006-20200926
i386 randconfig-a003-20200926
i386 randconfig-a004-202
Hi Boris,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: a1bffa48745afbb54cb4f873bba783b2ae8be042
commit: cd33c830448baf7b1e94da72eca069e3e1d050c9 media: rkvdec: Add the rkvdec
driver
date: 5 months ago
config: x
On Wed, Sep 16, 2020 at 12:56:05PM -0700, Hemant Kumar wrote:
> Currently this macro is defined in internal MHI header as
> a TRE length mask. Moving it to external header allows MHI
> client drivers to set this upper bound for the transmit
> buffer size.
>
> Signed-off-by: Hemant Kumar
Reviewed
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