On Tue, Apr 23, 2019 at 04:38:35PM -0700, Linus Torvalds wrote:
> So anybody who builds the kernel as root is doing something seriously
> wrong, in my opinion.
Some of my test boxes don't have a user account... if they fall over,
I'll just re-image them.
So I've been doing it wrong?
Hi Nick & Yamada,
Nick Desaulniers 於 2019年4月24日 週三 上午5:19寫道：
>
> Towards the goal of removing cc-ldoption, it seems that --hash-style=
> was added to binutils 2.17.50.0.2 in 2006. The minimal required version
> of binutils for the kernel according to
> Documentation/process/changes.rst is 2.20.
>
Christoph Hellwig 於 2019年4月24日 週三 下午2:14寫道：
>
> ping?
>
> On Tue, Apr 09, 2019 at 12:26:54PM +0200, Christoph Hellwig wrote:
> > These macros are not used anywhere.
> >
> > Signed-off-by: Christoph Hellwig
> > ---
> > arch/nds32/include/asm/memory.h | 8
> > 1 file changed, 8 deletions(
On 17.04.19 15:56, Oscar Salvador wrote:
> On Tue, 2019-04-09 at 12:01 +0200, David Hildenbrand wrote:
>> Let's just warn in case a section is not valid instead of failing to
>> remove somewhere in the middle of the process, returning an error
>> that
>> will be mostly ignored by callers.
>>
>> Cc:
Hi Jiada,
I think this series looks good. Unfortunately I'm out of office for the
next week and are thus unable to test it. Please don't let this block
this series but if it's still on the ML when I'm back I will do a proper
review and test of it.
On 2019-04-24 14:11:43 +0900, Jiada Wang wrote
Add devres wrapper for thermal_add_hwmon_sysfs() to simplify driver
code.
Signed-off-by: Andrey Smirnov
Reviewed-by: Daniel Lezcano
Tested-by: Lucas Stach
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo Valentin
Cc: Daniel Lezcano
Cc: Angus Ainslie (Purism)
Cc: linux-...@nxp.com
Cc: linux...@v
On 24-04-19, 12:16, Rajendra Nayak wrote:
>
>
> On 4/23/2019 6:58 PM, Georgi Djakov wrote:
> > In addition to frequency and voltage, some devices may have bandwidth
> > requirements for their interconnect throughput - for example a CPU
> > or GPU may also need to increase or decrease their bandwi
Convert driver to use regmap API, drop custom LE/BE IO helpers and
simplify bit manipulation using regmap_update_bits(). This also allows
us to convert some register initialization to use loops and adds
convenient debug access to TMU registers via debugfs.
Signed-off-by: Andrey Smirnov
Reviewed-b
Expose thermal readings as a HWMON device, so that it could be
accessed using lm-sensors.
Signed-off-by: Andrey Smirnov
Reviewed-by: Daniel Lezcano
Tested-by: Lucas Stach
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo Valentin
Cc: Daniel Lezcano
Cc: Angus Ainslie (Purism)
Cc: linux-...@nxp.co
Convert driver to use devm_ioremap() to simplify memory deallocation
and error handling code. No functional change intended.
Signed-off-by: Andrey Smirnov
Reviewed-by: Daniel Lezcano
Tested-by: Lucas Stach
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo Valentin
Cc: Daniel Lezcano
Cc: Angus Ain
We can simplify error cleanup code if instead of passing a "struct
platform_device *" to qoriq_tmu_calibration() and deriving a bunch of
pointers from it, we pass those pointers directly. This way we won't
be force to call platform_set_drvdata() as early in qoriq_tmu_probe()
and consequently would
Before returning measured temperature data to upper layer we need to
make sure that the reading was marked as "valid" to avoid reporting
bogus data.
Signed-off-by: Andrey Smirnov
Reviewed-by: Daniel Lezcano
Tested-by: Lucas Stach
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo Valentin
Cc: Danie
Tmu_get_temp will get called as a part of sensor registration via
devm_thermal_zone_of_sensor_register(). To prevent it from retruning
bogus data we need to enable sensor monitoring before that. Looking at
the datasheet (i.MX8MQ RM) there doesn't seem to be any harm in
enabling them all, so, for th
It's impossible to use this driver outside of Device Tree, so if the
probe function is called, the dev.of_node is guaranteed to not be NULL
and guarding against that is pointless. Drop it.
Signed-off-by: Andrey Smirnov
Acked-by: Daniel Lezcano
Tested-by: Lucas Stach
Cc: Chris Healy
Cc: Lucas S
Struct thermal_zone_device reference stored as sensor's private data
isn't really used anywhere in the code. Drop it.
Signed-off-by: Andrey Smirnov
Acked-by: Daniel Lezcano
Tested-by: Lucas Stach
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo Valentin
Cc: Daniel Lezcano
Cc: Angus Ainslie (Puri
Pass all necessary data to qoriq_tmu_register_tmu_zone() directly
instead of passing a paltform device and then deriving it. This is
done as a first step to simplify resource deallocation code.
Signed-off-by: Andrey Smirnov
Acked-by: Daniel Lezcano
Tested-by: Lucas Stach
Cc: Chris Healy
Cc: Lu
Now that driver is converted to use get_temp_id() instead of
get_temp() we no longer need per sensor data. Drop all of the code
related to it.
Signed-off-by: Andrey Smirnov
Tested-by: Lucas Stach
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo Valentin
Cc: Daniel Lezcano
Cc: Angus Ainslie (Puris
Use a local "struct device *dev" for brevity. No functional change
intended.
Signed-off-by: Andrey Smirnov
Acked-by: Daniel Lezcano
Tested-by: Lucas Stach
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo Valentin
Cc: Daniel Lezcano
Cc: Angus Ainslie (Purism)
Cc: linux-...@nxp.com
Cc: linux...@v
Everyone:
This series contains patches adding support for HWMON integration, bug
fixes and general improvements (hopefully) for TMU driver I made while
working on it on i.MX8MQ.
Feedback is welcome!
Thanks,
Andrey Smirnov
Changes since [v4]
- Collected Tested-by from Lucas
- Colle
On 22-03-19, 11:49, Viresh Kumar wrote:
> On 21-03-19, 12:45, Peter Zijlstra wrote:
> > On Wed, Mar 20, 2019 at 10:22:23AM +0530, Viresh Kumar wrote:
> > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> > > index 65e4559eef2f..1ac8c710 100644
> > > --- a/arch/x86/kvm/x86.c
> > > +++ b/
On 4/23/2019 6:58 PM, Georgi Djakov wrote:
In addition to frequency and voltage, some devices may have bandwidth
requirements for their interconnect throughput - for example a CPU
or GPU may also need to increase or decrease their bandwidth to DDR
memory based on the current operating performa
Hi Joao Paulo,
> This commit makes the kernel not send the next queued HCI command until
> a command complete arrives for the last HCI command sent to the
> controller. This change avoids a problem with some buggy controllers
> (seen on two SKUs of QCA9377) that send an extra command complete even
On Wed, Apr 24, 2019 at 11:59 AM Christoph Hellwig wrote:
>
> On Mon, Apr 15, 2019 at 09:37:23AM +, Anup Patel wrote:
> > This patch adds SCAUSE interrupt flag and SCAUSE interrupt related
> > defines to asm/csr.h. We also use these defines in kernel/irq.c and
> > express SIE/SIP flags in-term
On Wed, Apr 24, 2019 at 3:37 PM Masahiro Yamada
wrote:
>
> On Wed, Apr 24, 2019 at 3:29 PM Geert Uytterhoeven
> wrote:
> >
> > Hi Nick,
> >
> > On Tue, Apr 23, 2019 at 10:31 PM Nick Desaulniers
> > wrote:
> > > Towards the goal of removing cc-ldoption, prefer ld-option, or better
> > > yet, req
On Wed, Apr 24, 2019 at 3:29 PM Geert Uytterhoeven wrote:
>
> Hi Nick,
>
> On Tue, Apr 23, 2019 at 10:31 PM Nick Desaulniers
> wrote:
> > Towards the goal of removing cc-ldoption, prefer ld-option, or better
> > yet, require --Wl,--hash-style=sysv since the selftest for vdso's
> > requires DT_HAS
On Tue, Apr 23, 2019 at 01:51:45PM +, Robin Gong wrote:
> Correct ecspi/sdma compatible since ecspi errata ERR009165
> not fixed on i.mx6sll chip.
>
> Signed-off-by: Robin Gong
> ---
> arch/arm/boot/dts/imx6sll.dtsi | 10 +-
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff
On Tue, Apr 23, 2019 at 01:51:10PM +, Robin Gong wrote:
>ERR009165 fix on i.mx6ul and next chip, such as i.mx6ull/i.mx8mq/i.mx8mm.
> Remove workaround on those chips. Add new i.mx6ul type for that.
>
> Signed-off-by: Robin Gong
> ---
> drivers/spi/spi-imx.c | 39 +
On Mon, Apr 15, 2019 at 09:37:27AM +, Anup Patel wrote:
> We should prefer accessing CSRs using their CSR numbers because:
> 1. It compiles fine with older toolchains.
> 2. We can use latest CSR names in #define macro names of CSR numbers
>as-per RISC-V spec.
> 3. We can access newly added
On Mon, Apr 15, 2019 at 09:37:23AM +, Anup Patel wrote:
> This patch adds SCAUSE interrupt flag and SCAUSE interrupt related
> defines to asm/csr.h. We also use these defines in kernel/irq.c and
> express SIE/SIP flags in-terms of SCAUSE interrupt causes.
I'm not a fan of this. For one this p
On Mon, Apr 15, 2019 at 09:37:17AM +, Anup Patel wrote:
> The spacing between macro name and value is not consistent in
> asm/csr.h. This patch beautifies asm/csr.h by using tabs to align
> macro values instead of spaces.
>
> Signed-off-by: Anup Patel
Looks good,
Reviewed-by: Christoph Hell
Hi Nick,
On Tue, Apr 23, 2019 at 10:31 PM Nick Desaulniers
wrote:
> Towards the goal of removing cc-ldoption, prefer ld-option, or better
> yet, require --Wl,--hash-style=sysv since the selftest for vdso's
> requires DT_HASH.
>
> Cc: Andy Lutomirsky
> Cc: clang-built-li...@googlegroups.com
> Sug
Sorry, please ignore this patchset. I will send V2 to fix something else.
On 2019/4/24 11:21, Huazhong Tan wrote:
This patch-set includes code optimizations and bugfixes for the HNS3
ethernet controller driver.
[patch 1/12 - 3/12] fixes some bugs about the IO path
[patch 4/12 - 6/12] includes
The current proposed __vdso_sgx_enter_enclave() requires enclaves to preserve
%rsp, which prohibits enclaves from allocating space on the untrusted stack.
However, there are existing enclaves (e.g. those built with current Intel SGX
SDK libraries) relying on the untrusted stack for passing paramete
The previous __vdso_sgx_enter_enclave() requires enclaves to preserve %rsp,
which prohibits enclaves from allocating and passing parameters for
untrusted function calls (aka. o-calls).
This patch addresses the problem above by introducing a new ABI that preserves
%rbp instead of %rsp. Then __vdso_
The original x86/sgx/Makefile doesn't work when 'x86/sgx' is specified as the
test target. This patch fixes that problem, along with minor changes to the
dependencies between 'x86' and 'x86/sgx' in selftests/x86/Makefile.
Signed-off-by: Cedric Xing
---
tools/testing/selftests/x86/Makefile |
This patch augments SGX selftest with two new tests.
The first test exercises the newly added callback interface, by marking the
whole enclave range as PROT_READ, then calling mprotect() upon #PFs to add
necessary PTE permissions per PFEC (#PF Error Code) until the enclave finishes.
This test also
On Tue, Apr 23, 2019 at 05:02:27PM -0700, Atish Patra wrote:
> If nr_cpus command line option is set, maximum possible cpu should be
> set to that value.
>
> Signed-off-by: Atish Patra
Looks good,
Reviewed-by: Christoph Hellwig
On Apr 23, 2019, at 11:13 PM, Khazhismel Kumykov wrote:
>
> These functions may take a long time looping over many groups, which
> may cause issues for non-preempt kernels.
> ext4_mb_init_backend()
> ext4_setup_system_zone()
> ext4_mb_release()
>
> Signed-off-by: Khazhismel Kumykov
Reviewed-by
> }
> +
> +bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
> +{
> + return phys_id == cpuid_to_hartid_map(cpu);
> +}
> /* Unsupported */
Please keep an empty line after function bodys.
Otherwise looks good:
Reviewed-by: Christoph Hellwig
Looks good,
Reviewed-by: Christoph Hellwig
On Tue, Apr 23, 2019 at 02:22:53PM -0700, Nick Desaulniers wrote:
> Towards the goal of removing cc-ldoption, it seems that --hash-style=
> was added to binutils 2.17.50.0.2 in 2006. The minimal required version
> of binutils for the kernel according to
> Documentation/process/changes.rst is 2.20.
Steven Rostedt writes:
> On Tue, 23 Apr 2019 20:15:49 +0200
> Nicolai Stange wrote:
>> Steven Rostedt writes:
>> > For 32 bit, we could add 4 variables on the thread_info and make 4
>> > trampolines, one for each context (normal, softirq, irq and NMI), and
>> > have them use the variable stored
On Wed, Apr 24, 2019 at 01:47:48AM +0300, Serge Semin wrote:
> Since memblock-patchset was introduced the reserved-memory nodes are
> supported being declared in dt-files. So these nodes are actually parsed
> during the arch setup procedure when the early_init_fdt_scan_reserved_mem()
> method is ca
On 04/24/19 at 01:41pm, Baoquan He wrote:
> On 04/24/19 at 02:47am, Junichi Nomura wrote:
> > On 4/24/19 2:15 AM, Kairui Song wrote:
> > > On Mon, Apr 22, 2019 at 11:21 PM Junichi Nomura
> > > wrote:
> > >> Is the mapping of ACPI tables just by luck, too?
> > >
> > > Good question, they should h
ping?
On Tue, Apr 09, 2019 at 12:26:54PM +0200, Christoph Hellwig wrote:
> These macros are not used anywhere.
>
> Signed-off-by: Christoph Hellwig
> ---
> arch/nds32/include/asm/memory.h | 8
> 1 file changed, 8 deletions(-)
>
> diff --git a/arch/nds32/include/asm/memory.h b/arch/nds
On 4/24/2019 8:20 AM, YueHaibing wrote:
Remove duplicated include.
Signed-off-by: YueHaibing
Reviewed-by: Mukesh Ojha
Cheers,
-Mukesh
---
drivers/staging/kpc2000/kpc2000/kp2000_module.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/staging/kpc2000/kpc2000/kp2000_module.c
On Tue, Apr 23, 2019 at 5:08 PM Peter Zijlstra wrote:
> Well, SKX isn't exactly 'missing'; it would be very good if we can
> confirm the new code is still correct under the below mentioned
> conditions.
>
> commit b511203093489eb1829cb4de86e8214752205ac6
> Author: Len Brown
> Date: Fri Dec 22 0
On 23-04-19, 16:28, Georgi Djakov wrote:
> The OPP bindings now support bandwidth values, so add support to parse it
> from device tree and store it into the new dev_pm_opp_icc_bw struct, which
> is part of the dev_pm_opp.
>
> Also add and export the dev_pm_opp_set_paths() and dev_pm_opp_put_paths
Hi Gary,
On Wed, Apr 24, 2019 at 03:21:14AM +, Gary Guo wrote:
> > Look:
> > linux-next git:(riscv_asid_allocator_v2)$ grep GLOBAL arch/riscv -r
> > arch/riscv/include/asm/pgtable-bits.h:#define _PAGE_GLOBAL(1 << 5)/*
> > Global */
> > arch/riscv/include/asm/pgtable-bits.h:
On 04/23/2019 09:35 PM, Mark Rutland wrote:
> On Tue, Apr 23, 2019 at 01:01:58PM +0530, Anshuman Khandual wrote:
>> Generic usage for init_mm.pagetable_lock
>>
>> Unless I have missed something else these are the generic init_mm kernel
>> page table
>> modifiers at runtime (at least which uses ini
On 23-04-19, 16:28, Georgi Djakov wrote:
> If the OPP bandwidth values are populated, we want to switch also the
> interconnect bandwidth in addition to frequency and voltage.
>
> Signed-off-by: Georgi Djakov
> ---
> drivers/opp/core.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion
On Tue, Apr 23, 2019 at 9:22 PM Eduardo Valentin wrote:
>
> Hello,
>
> On Tue, Apr 02, 2019 at 06:12:44PM +0200, Daniel Lezcano wrote:
> > The module support for the thermal subsystem makes little sense:
> > - some subsystems relying on it are not modules, thus forcing the
> >framework to be
On (04/23/19 09:48), Steven Rostedt wrote:
> > RFC
> >
> > Normally, we grab console_sem lock before we iterate consoles
> > list, which is necessary if we want to be race free. The only exception
> > to this rule is console_flush_on_panic(). However, it seems that we are
> > not fully rac
Is anyone going to pick this patch up?
Add support for Synopsys DesignWare core IP based PCIe host controller
present in Tegra194 SoC.
Signed-off-by: Vidya Sagar
---
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Changed 'nvidia,init-speed' to 'nvidia,init-link-speed'
* Changed 'nvidia,pex-wake' to 'nvid
ZQ,
On Fri, Apr 12, 2019 at 3:22 PM Z.q. Hou wrote:
>
> From: Hou Zhiqiang
>
> Refactor the Mobiveil PCIe Host Bridge IP driver to make
> it easier to add support for both RC and EP mode driver.
> This patch moved the Mobiveil driver to an new directory
> 'drivers/pci/controller/mobiveil' and re
On Tue, 23 Apr 2019 at 11:56, Enric Balletbo i Serra
wrote:
>
> Hi Tomeu,
>
> On 23/4/19 10:11, Tomeu Vizoso wrote:
> > Callers don't expect it to return NULL, but an error code.
> >
> > Fixes Oops such as the one below, when one tries to set a governor that
> > isn't available:
> >
> > Unable to
On Tue, Apr 23, 2019 at 05:25:00PM +0200, Sebastian Andrzej Siewior wrote:
> On 2019-04-15 13:04:03 [+0200], To Paul E. McKenney wrote:
> >
> > good so nothing important so far. I hope the box gets to TREE08 soon.
>
> test completed. Nothing new.
That took some time! Thank you for running it!
On 23-04-19, 16:28, Georgi Djakov wrote:
> In addition to frequency and voltage, some devices may have bandwidth
> requirements for their interconnect throughput - for example a CPU
> or GPU may also need to increase or decrease their bandwidth to DDR
> memory based on the current operating perform
Add PCIe host controller driver for DesignWare core based
PCIe controller IP present in Tegra194.
Signed-off-by: Vidya Sagar
---
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* None
Changes since [v1]:
* Changed CONFIG_PCIE_TEGRA194 from 'y' to 'm'
arch/arm64/conf
Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
The Tegra194 SoC contains six PCIe controllers and twenty P2U instances
grouped into two different PHY bricks namely High-Speed IO (HSIO-12 P2Us)
and NVIDIA High Speed (NVHS-8 P2Us) respectively.
Signed-off-by: Vidya Sagar
---
Chang
Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface
with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module.
For each PCIe lane of a controller, there is a P2U unit instantiated at
hardware level. This driver provides support for the programming required
for each P2
Enable PCIe controller nodes to enable respective PCIe slots on
P2972- board. Following is the ownership of slots by different
PCIe controllers.
Controller-0 : M.2 Key-M slot
Controller-1 : On-board Marvell eSATA controller
Controller-3 : M.2 Key-E slot
Signed-off-by: Vidya Sagar
---
Changes
Add support for Tegra194 P2U (PIPE to UPHY) module block which is a glue
module instantiated one for each PCIe lane between Synopsys Designware core
based PCIe IP and Universal PHY block.
---
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Changed node label to reflect
Add support for Tegra194 PCIe controllers. These controllers are based
on Synopsys DesignWare core IP.
Signed-off-by: Vidya Sagar
---
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Using only 'Cx' (x-being controller number) format to represent a controller
* Change
Add support to enable CDM (Configuration Dependent Module) register check
for any data corruption based on the device-tree flag 'enable-cdm-check'.
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
---
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* Changed code
Add support to enable CDM (Configuration Dependent Module) registers check
for any data corruption. CDM registers include standard PCIe configuration
space registers, Port Logic registers and iATU and DMA registers.
Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook
Vers
Some host controllers need to know the existence of clkreq signal routing to
downstream devices to be able to advertise low power features like ASPM L1
substates. Without clkreq signal routing being present, enabling ASPM L1 sub
states might lead to downstream devices falling off the bus. Hence a n
Export pcie_bus_config to enable host controller drivers setting it to a
specific configuration be able to build as loadable modules
Signed-off-by: Vidya Sagar
---
Changes since [v4]:
* None
Changes since [v3]:
* None
Changes since [v2]:
* None
Changes since [v1]:
* This is a new patch in v2 s
Remove multiple write enable and disable sequences of dbi registers as
Tegra194 implements writes to BAR-0 register (offset: 0x10) controlled by
DBI write-lock enable bit thereby not allowing any further writes to BAR-0
register in config space to take place. Hence disabling write permission
only t
Move PCIe config space capability search API to common DesignWare file
as this can be used by both host and ep mode codes.
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
---
Changes from [v4]:
* Removed redundant APIs in pcie-designware-ep.c file after moving them
to pcie-designware.c f
Add extended configuration space capability search API using struct dw_pcie *
pointer
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
---
Changes from [v4]:
* None
Changes from [v3]:
* None
Changes from [v2]:
* None
Changes from [v1]:
* This is a new patch in v2 series
drivers/pci/con
Export pcie_pme_disable_msi() & pcie_pme_no_msi() APIs to enable drivers
using this API be able to build as loadable modules.
Signed-off-by: Vidya Sagar
---
Changes from [v4]:
* None
Changes from [v3]:
* None
Changes from [v2]:
* Exported pcie_pme_no_msi() API after making pcie_pme_msi_disabled
Hi ,
Sorry for spam,
when is the plan to merge this patch.
Regards
Gaurav
On 4/16/2019 4:45 PM, Gaurav Kohli wrote:
Hi ,
I have reviewed and tested for both enabled and disabled and working as
expected.
Please feel free to add:
Reviewed-by: Gaurav Kohli
Tested-by: Gaurav Kohli
Regards
Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
features.
Signed-off-by: Vidya Sagar
Reviewed-by: Thierry Reding
---
Changes from [v4]:
* None
Changes from [v3]:
* None
Changes from [v2]:
* Updated commit message and description to explicitly mention that defines are
Tegra194 has six PCIe controllers based on Synopsys DesignWare core.
There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO:
Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively.
Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses
UPHY lanes from NVH
Currently IRQ remains enabled after .remove, later if device is probed,
IRQ is requested before .thermal_init, this may cause IRQ function be
called before device is initialized.
this patch disables interrupt in .remove, to ensure irq function
only be called after device is fully initialized.
Sig
Currently IRQF_SHARED type interrupt line is allocated, but it
is not appropriate, as the interrupt line isn't shared between
different devices, instead IRQF_ONESHOT is the proper type.
By changing interrupt type to IRQF_ONESHOT, now irq handler is
no longer needed, as clear of interrupt status ca
There are issues with interrupt handling in rcar_gen3_thermal driver.
Currently IRQ is remain enabled after .remove, later if device is probed,
IRQ is requested before .thermal_init, this may cause IRQ function be
triggered but not able to clear IRQ status, thus cause system to hang.
Since the ir
Hi all,
Today's linux-next merge of the tip tree got a conflict in:
arch/arm64/include/asm/Kbuild
between commit:
c67fdc1f00cb ("arch: mostly remove ")
from the asm-generic tree and commit:
46ad0840b158 ("locking/rwsem: Remove arch specific rwsem files")
from the tip tree.
I fixed it
Let's reparent memcg slab memory on memcg offlining. This allows us
to release the memory cgroup without waiting for the last outstanding
kernel object (e.g. dentry used by another application).
So instead of reparenting all accounted slab pages, let's do reparent
a relatively small amount of kmem
Hi Helmut,
> -Original Message-
> From: Helmut Grohne
> Sent: Tuesday, April 23, 2019 6:15 PM
> To: Naga Sureshkumar Relli
> Cc: bbrezil...@kernel.org; miquel.ray...@bootlin.com; rich...@nod.at;
> dw...@infradead.org; computersforpe...@gmail.com; marek.va...@gmail.com;
> linux-
> m...@l
Altera MSI IP is a soft IP and is only available after
FPGA image is programmed.
Make driver modulable to support use case FPGA image is programmed
after kernel is booted. User proram FPGA image in kernel then only load
MSI driver module.
Signed-off-by: Ley Foon Tan
---
drivers/pci/controller/K
Altera PCIe Rootport IP is a soft IP and is only available after
FPGA image is programmed.
Make driver modulable to support use case FPGA image is programmed
after kernel is booted. User proram FPGA image in kernel then only load
PCIe driver module.
Signed-off-by: Ley Foon Tan
---
drivers/pci/c
# Why do we need this?
We've noticed that the number of dying cgroups is steadily growing on most
of our hosts in production. The following investigation revealed an issue
in userspace memory reclaim code [1], accounting of kernel stacks [2],
and also the mainreason: slab objects.
The underlying
Initialize kmem_cache->memcg_params.memcg pointer in
memcg_link_cache() rather than in init_memcg_params().
Once kmem_cache will hold a reference to the memory cgroup,
it will simplify the refcounting.
For non-root kmem_caches memcg_link_cache() is always called
before the kmem_cache becomes visi
Let's separate the page counter modification code out of
__memcg_kmem_uncharge() in a way similar to what
__memcg_kmem_charge() and __memcg_kmem_charge_memcg() work.
This will allow to reuse this code later using a new
memcg_kmem_uncharge_memcg() wrapper, which calls
__memcg_kmem_unchare_memcg() i
Currently the page accounting code is duplicated in SLAB and SLUB
internals. Let's move it into new (un)charge_slab_page helpers
in the slab_common.c file. These helpers will be responsible
for statistics (global and memcg-aware) and memcg charging.
So they are replacing direct memcg_(un)charge_sla
On 04/18/2019 06:14 AM, Quentin Perret wrote:
> On Tuesday 16 Apr 2019 at 15:38:39 (-0400), Thara Gopinath wrote:
>> +/**
>> + * Function to update thermal pressure from cooling device
>> + * or any framework responsible for capping cpu maximum
>> + * capacity.
>> + */
>> +void sched_update_thermal
On Tue, Apr 23, 2019 at 02:31:18PM +0530, Bharath Vedartham wrote:
> This patch fixes the sparse warning:
> warning: restricted __fs16 degrades to integer
>
> inode->ui_u1.oldids.ui_suid is of type __fs16, a restricted integer.
> 0X is a 16 bit unsigned integer. Use __force to fix the sparse
>
On Wed, Apr 24, 2019 at 4:49 AM Kees Cook wrote:
>
> This refactors the stack memory initialization configs in order to
> keep things together when adding Clang stack initialization, and in
> preparation for future heap memory initialization configs.
>
> I intend to carry this in the gcc-plugins t
On Tue, Apr 23, 2019 at 4:57 PM Andy Lutomirski wrote:
>
> To clarify, this is “fail if you can’t find the files to install, but don’t
> even try to check whether those files are up to date”, right?
Ack. Exactly because the whole "check whether the files are
up-to-date" is generally part of the
On Wed, Apr 24, 2019 at 4:36 AM Kees Cook wrote:
>
> On Thu, Apr 11, 2019 at 6:39 PM Masahiro Yamada
> wrote:
> >
> > On Fri, Apr 12, 2019 at 3:01 AM Kees Cook wrote:
> > >
> > > Right now kernel hardening options are scattered around various Kconfig
> > > files. This can be a central place to c
Friendly ping...
> From: Zhiqiang Liu
>
> In proc_dointvec_jiffies func, the write value is only checked
> whether it is larger than INT_MAX. If the write value is less
> than zero, it can also be successfully writen in the data.
>
> However, in some scenarios, users would adopt the data to
>
On 24-04-19, 10:32, andy.t...@nxp.com wrote:
> From: Yuantian Tang
>
> Enable cpufreq feature on ls1028a chip by adding its compatible
> string.
>
> Signed-off-by: Yuantian Tang
> ---
> drivers/cpufreq/qoriq-cpufreq.c |1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git
On Wed, Apr 24, 2019 at 1:12 PM Vidya Sagar wrote:
>
> On 4/24/2019 2:02 AM, Bjorn Helgaas wrote:
> > On Tue, Apr 23, 2019 at 01:57:19PM +0530, Vidya Sagar wrote:
> >> Move PCIe config space capability search API to common DesignWare file
> >> as this can be used by both host and ep mode codes.
>
On Wed, Apr 24, 2019 at 8:40 AM Linus Torvalds
wrote:
>
> On Tue, Apr 23, 2019 at 11:47 AM Andy Lutomirski wrote:
> >
> > Hmm. I suppose an alternative would be for vdso_install to fail if
> > the vdso isn't built?
>
> I absolutely abhor even the concept of building the kernel as root,
> and I t
Enable CONFIG_THERMAL_STATISTICS to extend the sysfs interface
for thermal cooling devices and expose some useful statistics.
Signed-off-by: Anson Huang
---
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig
b/arch/arm/c
> -Original Message-
> From: Guo Ren
> Sent: Wednesday, April 24, 2019 03:08
> To: Gary Guo
> Cc: Christoph Hellwig ; linux-a...@vger.kernel.org; Palmer
> Dabbelt ; Andrew Waterman ; Arnd
> Bergmann ; Anup Patel ; Xiang
> Xiaoyan ; linux-kernel@vger.kernel.org; Mike
> Rapoport ; Vincen
On 4/24/2019 2:05 AM, Bjorn Helgaas wrote:
On Tue, Apr 23, 2019 at 01:57:20PM +0530, Vidya Sagar wrote:
Add extended configuration space capability search API using struct dw_pcie *
pointer
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
---
Changes from [v3]:
* None
Changes from [v2]:
1 - 100 of 873 matches
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