Re: [PATCH v3 04/13] dt-bindings: x86: Add CPU bindings for x86

2025-05-03 Thread Rob Herring (Arm)
On Sat, 03 May 2025 12:15:06 -0700, Ricardo Neri wrote: > Add bindings for CPUs in x86 architecture. Start by defining the `reg` and > `enable-method` properties and their relationship to x86 APIC ID and the > available mechanisms to boot secondary CPUs. > > Start defining bindings for Intel pro

[PATCH v3 10/13] x86/hyperv/vtl: Setup the 64-bit trampoline for TDX guests

2025-05-03 Thread Ricardo Neri
From: Yunhong Jiang The hypervisor is an untrusted entity for TDX guests. It cannot be used to boot secondary CPUs - neither via hypercalls not the INIT assert, de-assert plus Start-Up IPI messages. Instead, the platform virtual firmware boots the secondary CPUs and puts them in a state to trans

[PATCH v3 02/13] x86/acpi: Add a helper function to get a pointer to the wakeup mailbox

2025-05-03 Thread Ricardo Neri
In preparation to move the functionality to wake secondary CPUs up out of the ACPI code, add a helper function to get a pointer to the mailbox. Use this helper function only in the portions of the code for which the variable acpi_mp_wake_mailbox will be out of scope once it is relocated out of the

[PATCH v3 06/13] dt-bindings: reserved-memory: Wakeup Mailbox for Intel processors

2025-05-03 Thread Ricardo Neri
Add DeviceTree bindings for the wakeup mailbox used on Intel processors. x86 platforms commonly boot secondary CPUs using an INIT assert, de-assert followed by Start-Up IPI messages. The wakeup mailbox can be used when this mechanism unavailable. The wakeup mailbox offers more control to the oper

[PATCH v3 07/13] x86/dt: Parse the Wakeup Mailbox for Intel processors

2025-05-03 Thread Ricardo Neri
The Wakeup Mailbox is a mechanism to boot secondary CPUs used on systems that do not want or cannot use the INIT + StartUp IPI messages. Add `intel,wakeup-mailbox` to the set of supported enable methods. Also add functionality to find and parse the parameters of the mailbox from the DeviceTree fro

[PATCH v3 08/13] x86/hyperv/vtl: Set real_mode_header in hv_vtl_init_platform()

2025-05-03 Thread Ricardo Neri
From: Yunhong Jiang Hyper-V VTL clears x86_platform.realmode_{init(), reserve()} in hv_vtl_platform_init() whereas it sets real_mode_header later in hv_vtl_early_init(). There is no need to deal with the real mode memory in two places: x86_platform.realmode_init() is invoked much later via an ear

[PATCH v3 13/13] x86/hyperv/vtl: Use the wakeup mailbox to boot secondary CPUs

2025-05-03 Thread Ricardo Neri
The hypervisor is an untrusted entity for TDX guests. It cannot be used to boot secondary CPUs. The function hv_vtl_wakeup_secondary_cpu() cannot be used. Instead, the virtual firmware boots the secondary CPUs and places them in a state to transfer control to the kernel using the wakeup mailbox.

[PATCH v3 00/13] x86/hyperv/hv_vtl: Use a wakeup mailbox to boot secondary CPUs

2025-05-03 Thread Ricardo Neri
Hi, I have taken over this work from Yunhong Jiang [1]. I have implemented all the feedback received in his last submission. I think that the acpi, smpboot, and hyperv portions are in good shape and ready for review by the x86 maintainers. I did major rework on the DeviceTree bindings and in my op

[PATCH v3 01/13] x86/acpi: Add a helper function to setup the wakeup mailbox

2025-05-03 Thread Ricardo Neri
In preparation to move the functionality to wake secondary CPUs up out of the ACPI code, add a helper function that stores the physical address of the mailbox and updates the wakeup_secondary_cpu_64() APIC callback. There is a slight change in behavior: now the APIC callback is updated before conf

[PATCH v3 04/13] dt-bindings: x86: Add CPU bindings for x86

2025-05-03 Thread Ricardo Neri
Add bindings for CPUs in x86 architecture. Start by defining the `reg` and `enable-method` properties and their relationship to x86 APIC ID and the available mechanisms to boot secondary CPUs. Start defining bindings for Intel processors. Bindings for other vendors can be added later as needed. S

[PATCH v3 11/13] x86/smpboot: Add a helper get the address of the wakeup mailbox

2025-05-03 Thread Ricardo Neri
A Hyper-V VTL level 2 guest on a TDX environment needs to map the physical page of the ACPI Multiprocessor Wakeup Structure as private (encrypted). It needs to know the physical address of this structure. Add a helper function. Suggested-by: Michael Kelley Signed-off-by: Ricardo Neri --- Changes

[PATCH v3 12/13] x86/hyperv/vtl: Mark the wakeup mailbox page as private

2025-05-03 Thread Ricardo Neri
From: Yunhong Jiang The current code maps MMIO devices as shared (decrypted) by default in a confidential computing VM. In a TDX environment, secondary CPUs are booted using the Multiprocessor Wakeup Structure defined in the ACPI specification. The virtual firmware and the operating system funct

[PATCH v3 09/13] x86/realmode: Make the location of the trampoline configurable

2025-05-03 Thread Ricardo Neri
From: Yunhong Jiang x86 CPUs boot in real mode. This mode uses 20-bit memory addresses (16-bit registers plus 4-bit segment selectors). This implies that the trampoline must reside under the 1MB memory boundary. There are platforms in which the firmware boots the secondary CPUs, switches them to

[PATCH v3 05/13] x86/dt: Parse the `enable-method` property of CPU nodes

2025-05-03 Thread Ricardo Neri
Add functionality to parse and validate the `enable-method` property for platforms that use alternative methods to wakeup secondary CPUs (e.g., a wakeup mailbox). Most x86 platforms boot secondary CPUs using INIT assert, de-assert followed by a Start-Up IPI messages. These systems do no need to sp

[PATCH v3 03/13] x86/acpi: Move acpi_wakeup_cpu() and helpers to smpboot.c

2025-05-03 Thread Ricardo Neri
The bootstrap processor uses acpi_wakeup_cpu() to indicate to firmware that it wants to boot a secondary CPU using a mailbox as described in the Multiprocessor Wakeup Structure of the ACPI specification. The wakeup mailbox does not strictly require support from ACPI. The platform firmware can impl