On Sat, 03 May 2025 12:15:06 -0700, Ricardo Neri wrote:
> Add bindings for CPUs in x86 architecture. Start by defining the `reg` and
> `enable-method` properties and their relationship to x86 APIC ID and the
> available mechanisms to boot secondary CPUs.
>
> Start defining bindings for Intel processors. Bindings for other vendors
> can be added later as needed.
>
> Signed-off-by: Ricardo Neri <ricardo.neri-calde...@linux.intel.com>
> ---
> .../devicetree/bindings/x86/cpus.yaml | 80 +++++++++++++++++++
> 1 file changed, 80 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/x86/cpus.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/x86/cpus.example.dtb:
cpus: cpu@0: 'cache-level' is a required property
from schema $id: http://devicetree.org/schemas/cpus.yaml#
doc reference errors (make refcheckdocs):
See
https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250503191515.24041-5-ricardo.neri-calde...@linux.intel.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
