Re: [PATCH 04/12] mm: Allow compound zone device pages

: 6f1833b8208c3b9e59eff10792667b6639365146 patch link: https://lore.kernel.org/r/c7026449473790e2844bb82012216c57047c7639.1725941415.git-series.apopple%40nvidia.com patch subject: [PATCH 04/12] mm: Allow compound zone device pages config: csky-defconfig (https://download.01.org/0day-ci/archive/20240912

Re: [PATCH 04/12] mm: Allow compound zone device pages

: 6f1833b8208c3b9e59eff10792667b6639365146 patch link: https://lore.kernel.org/r/c7026449473790e2844bb82012216c57047c7639.1725941415.git-series.apopple%40nvidia.com patch subject: [PATCH 04/12] mm: Allow compound zone device pages config: um-allnoconfig (https://download.01.org/0day-ci/archive/20240912

Re: [PATCH 12/12] mm: Remove devmap related functions and page table bits

-ci/archive/20240912/202409122016.5i2hnkru-...@intel.com/config) compiler: powerpc64-linux-gcc (GCC) 14.1.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240912/202409122016.5i2hnkru-...@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not

Re: [PATCH v2 07/25] KVM: VMX: Set intercept for FRED MSRs

On Thu, Sep 05, 2024, Xin Li wrote: > On 6/12/2024 2:32 PM, Sean Christopherson wrote: > > On Fri, Apr 19, 2024, Chao Gao wrote: > > > On Wed, Feb 07, 2024 at 09:26:27AM -0800, Xin Li wrote: > > > > Add FRED MSRs to the valid passthrough MSR list and set FRED MSRs > > > > intercept > > > > based o

[PATCH v4 00/30] riscv control-flow integrity for usermode

v4 for cpu assisted riscv user mode control flow integrity. zicfiss and zicfilp [1] are ratified riscv CPU extensions. v3 [2] was sent in April this year for riscv usermode control flow integrity enabling. To get more information on zicfilp and zicfiss riscv CPU extensions, patch series adds docu

[PATCH v4 01/30] mm: Introduce ARCH_HAS_USER_SHADOW_STACK

From: Mark Brown Since multiple architectures have support for shadow stacks and we need to select support for this feature in several places in the generic code provide a generic config option that the architectures can select. Suggested-by: David Hildenbrand Acked-by: David Hildenbrand Signe

[PATCH v4 02/30] mm: helper `is_shadow_stack_vma` to check shadow stack vma

VM_SHADOW_STACK (alias to VM_HIGH_ARCH_5) is used to encode shadow stack VMA on three architectures (x86 shadow stack, arm GCS and RISC-V shadow stack). In case architecture doesn't implement shadow stack, it's VM_NONE Introducing a helper `is_shadow_stack_vma` to determine shadow stack vma or not.

[PATCH v4 04/30] riscv: Add support for per-thread envcfg CSR values

From: Samuel Holland Some bits in the [ms]envcfg CSR, such as the CFI state and pointer masking mode, need to be controlled on a per-thread basis. Support this by keeping a copy of the CSR value in struct thread_struct and writing it during context switches. It is safe to discard the old CSR valu

[PATCH v4 06/30] riscv/Kconfig: enable HAVE_EXIT_THREAD for riscv

riscv will need an implementation for exit_thread to clean up shadow stack when thread exits. If current thread had shadow stack enabled, shadow stack is allocated by default for any new thread. Signed-off-by: Deepak Gupta Reviewed-by: Charlie Jenkins --- arch/riscv/Kconfig | 1 + arch

[PATCH v4 07/30] riscv: zicfilp / zicfiss in dt-bindings (extensions.yaml)

Make an entry for cfi extensions in extensions.yaml. Signed-off-by: Deepak Gupta --- .../devicetree/bindings/riscv/extensions.yaml| 12 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings

[PATCH v4 08/30] riscv: zicfiss / zicfilp enumeration

This patch adds support for detecting zicfiss and zicfilp. zicfiss and zicfilp stands for unprivleged integer spec extension for shadow stack and branch tracking on indirect branches, respectively. This patch looks for zicfiss and zicfilp in device tree and accordinlgy lights up bit in cpu feature

[PATCH v4 09/30] riscv: zicfiss / zicfilp extension csr and bit definitions

zicfiss and zicfilp extension gets enabled via b3 and b2 in *envcfg CSR. menvcfg controls enabling for S/HS mode. henvcfg control enabling for VS while senvcfg controls enabling for U/VU mode. zicfilp extension extends *status CSR to hold `expected landing pad` bit. A trap or interrupt can occur b

[PATCH v4 10/30] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit

Carves out space in arch specific thread struct for cfi status and shadow stack in usermode on riscv. This patch does following - defines a new structure cfi_status with status bit for cfi feature - defines shadow stack pointer, base and size in cfi_status structure - defines offsets to new member

[PATCH v4 11/30] riscv/mm : ensure PROT_WRITE leads to VM_READ | VM_WRITE

`arch_calc_vm_prot_bits` is implemented on risc-v to return VM_READ | VM_WRITE if PROT_WRITE is specified. Similarly `riscv_sys_mmap` is updated to convert all incoming PROT_WRITE to (PROT_WRITE | PROT_READ). This is to make sure that any existing apps using PROT_WRITE still work. Earlier `protect

[PATCH v4 12/30] riscv mm: manufacture shadow stack pte

This patch implements creating shadow stack pte (on riscv). Creating shadow stack PTE on riscv means that clearing RWX and then setting W=1. Signed-off-by: Deepak Gupta Reviewed-by: Alexandre Ghiti --- arch/riscv/include/asm/pgtable.h | 10 ++ 1 file changed, 10 insertions(+) diff --gi

[PATCH v4 13/30] riscv mmu: teach pte_mkwrite to manufacture shadow stack PTEs

pte_mkwrite creates PTEs with WRITE encodings for underlying arch. Underlying arch can have two types of writeable mappings. One that can be written using regular store instructions. Another one that can only be written using specialized store instructions (like shadow stack stores). pte_mkwrite ca

[PATCH v4 14/30] riscv mmu: write protect and shadow stack

`fork` implements copy on write (COW) by making pages readonly in child and parent both. ptep_set_wrprotect and pte_wrprotect clears _PAGE_WRITE in PTE. Assumption is that page is readable and on fault copy on write happens. To implement COW on shadow stack pages, clearing up W bit makes them XWR

[PATCH v4 15/30] riscv/mm: Implement map_shadow_stack() syscall

As discussed extensively in the changelog for the addition of this syscall on x86 ("x86/shstk: Introduce map_shadow_stack syscall") the existing mmap() and madvise() syscalls do not map entirely well onto the security requirements for shadow stack memory since they lead to windows where memory is a

[PATCH v4 16/30] riscv/shstk: If needed allocate a new shadow stack on clone

Userspace specifies CLONE_VM to share address space and spawn new thread. `clone` allow userspace to specify a new stack for new thread. However there is no way to specify new shadow stack base address without changing API. This patch allocates a new shadow stack whenever CLONE_VM is given. In cas

[PATCH v4 17/30] prctl: arch-agnostic prctl for shadow stack

From: Mark Brown Three architectures (x86, aarch64, riscv) have announced support for shadow stacks with fairly similar functionality. While x86 is using arch_prctl() to control the functionality neither arm64 nor riscv uses that interface so this patch adds arch-agnostic prctl() support to get

[PATCH v4 18/30] prctl: arch-agnostic prctl for indirect branch tracking

Three architectures (x86, aarch64, riscv) have support for indirect branch tracking feature in a very similar fashion. On a very high level, indirect branch tracking is a CPU feature where CPU tracks branches which uses memory operand to perform control transfer in program. As part of this tracking

[PATCH v4 03/30] riscv: Enable cbo.zero only when all harts support Zicboz

From: Samuel Holland Currently, we enable cbo.zero for usermode on each hart that supports the Zicboz extension. This means that the [ms]envcfg CSR value may differ between harts. Other features, such as pointer masking and CFI, require setting [ms]envcfg bits on a per-thread basis. The combinati

[PATCH v4 05/30] riscv: Call riscv_user_isa_enable() only on the boot hart

From: Samuel Holland Now that the [ms]envcfg CSR value is maintained per thread, not per hart, riscv_user_isa_enable() only needs to be called once during boot, to set the value for the init task. This also allows it to be marked as __init. Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley R

[PATCH v4 19/30] riscv: Implements arch agnostic shadow stack prctls

Implement architecture agnostic prctls() interface for setting and getting shadow stack status. prctls implemented are PR_GET_SHADOW_STACK_STATUS, PR_SET_SHADOW_STACK_STATUS and PR_LOCK_SHADOW_STACK_STATUS. As part of PR_SET_SHADOW_STACK_STATUS/PR_GET_SHADOW_STACK_STATUS, only PR_SHADOW_STACK_ENA

[PATCH v4 20/30] riscv: Implements arch agnostic indirect branch tracking prctls

prctls implemented are: PR_SET_INDIR_BR_LP_STATUS, PR_GET_INDIR_BR_LP_STATUS and PR_LOCK_INDIR_BR_LP_STATUS. Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/usercfi.h | 28 +++- arch/riscv/kernel/process.c | 5 +++ arch/riscv/kernel/usercfi.c | 76 ++

[PATCH v4 21/30] riscv/traps: Introduce software check exception

zicfiss / zicfilp introduces a new exception to priv isa `software check exception` with cause code = 18. This patch implements software check exception. Additionally it implements a cfi violation handler which checks for code in xtval. If xtval=2, it means that sw check exception happened because

[PATCH v4 22/30] riscv sigcontext: cfi state struct definition for sigcontext

Shadow stack needs to be saved and restored on signal delivery and signal return. sigcontext embedded in ucontext is extendible. Defining cfi state in there which can be used to save cfi state before signal delivery and restore cfi state on sigreturn Signed-off-by: Deepak Gupta --- arch/riscv/i

[PATCH v4 23/30] riscv signal: save and restore of shadow stack for signal

Save shadow stack pointer in sigcontext structure while delivering signal. Restore shadow stack pointer from sigcontext on sigreturn. As part of save operation, kernel uses `ssamoswap` to save snapshot of current shadow stack on shadow stack itself (can be called as a save token). During restore o

[PATCH v4 24/30] riscv/kernel: update __show_regs to print shadow stack register

Updating __show_regs to print captured shadow stack pointer as well. On tasks where shadow stack is disabled, it'll simply print 0. Signed-off-by: Deepak Gupta Reviewed-by: Alexandre Ghiti --- arch/riscv/kernel/process.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ar

[PATCH v4 25/30] riscv/ptrace: riscv cfi status and state via ptrace and in core files

Expose a new register type NT_RISCV_USER_CFI for risc-v cfi status and state. Intentionally both landing pad and shadow stack status and state are rolled into cfi state. Creating two different NT_RISCV_USER_XXX would not be useful and wastage of a note type. Enabling or disabling of feature is not

[PATCH v4 26/30] riscv/hwprobe: zicfilp / zicfiss enumeration in hwprobe

Adding enumeration of zicfilp and zicfiss extensions in hwprobe syscall. Signed-off-by: Deepak Gupta --- arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ arch/riscv/kernel/sys_hwprobe.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/

[PATCH v4 27/30] riscv: create a config for shadow stack and landing pad instr support

This patch creates a config for shadow stack support and landing pad instr support. Shadow stack support and landing instr support can be enabled by selecting `CONFIG_RISCV_USER_CFI`. Selecting `CONFIG_RISCV_USER_CFI` wires up path to enumerate CPU support and if cpu support exists, kernel will sup

[PATCH v4 28/30] riscv: Documentation for landing pad / indirect branch tracking

Adding documentation on landing pad aka indirect branch tracking on riscv and kernel interfaces exposed so that user tasks can enable it. Signed-off-by: Deepak Gupta --- Documentation/arch/riscv/zicfilp.rst | 104 +++ 1 file changed, 104 insertions(+) create mode 100644

[PATCH v4 29/30] riscv: Documentation for shadow stack on riscv

Adding documentation on shadow stack for user mode on riscv and kernel interfaces exposed so that user tasks can enable it. Signed-off-by: Deepak Gupta --- Documentation/arch/riscv/zicfiss.rst | 169 +++ 1 file changed, 169 insertions(+) create mode 100644 Documentation/

[PATCH v4 30/30] kselftest/riscv: kselftest for user mode cfi

Adds kselftest for RISC-V control flow integrity implementation for user mode. There is not a lot going on in kernel for enabling landing pad for user mode. cfi selftest are intended to be compiled with zicfilp and zicfiss enabled compiler. Thus kselftest simply checks if landing pad and shadow sta

Re: [PATCH v4 07/30] riscv: zicfilp / zicfiss in dt-bindings (extensions.yaml)

On Thu, 12 Sep 2024 16:16:26 -0700, Deepak Gupta wrote: > Make an entry for cfi extensions in extensions.yaml. > > Signed-off-by: Deepak Gupta > --- > .../devicetree/bindings/riscv/extensions.yaml| 12 > 1 file changed, 12 insertions(+) > My bot found errors running 'mak