[PATCH v4 05/30] riscv: Call riscv_user_isa_enable() only on the boot hart

[Deepak Gupta]

From: Samuel Holland <samuel.holl...@sifive.com>

Now that the [ms]envcfg CSR value is maintained per thread, not per
hart, riscv_user_isa_enable() only needs to be called once during boot,
to set the value for the init task. This also allows it to be marked as
__init.

Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.doo...@microchip.com>
Reviewed-by: Deepak Gupta <de...@rivosinc.com>
Signed-off-by: Samuel Holland <samuel.holl...@sifive.com>
Signed-off-by: Deepak Gupta <de...@rivosinc.com>
---
 arch/riscv/include/asm/cpufeature.h | 2 +-
 arch/riscv/kernel/cpufeature.c      | 4 ++--
 arch/riscv/kernel/smpboot.c         | 2 --
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/include/asm/cpufeature.h 
b/arch/riscv/include/asm/cpufeature.h
index 45f9c1171a48..ce9a995730c1 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -31,7 +31,7 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
 /* Per-cpu ISA extensions. */
 extern struct riscv_isainfo hart_isa[NR_CPUS];
 
-void riscv_user_isa_enable(void);
+void __init riscv_user_isa_enable(void);
 
 #define _RISCV_ISA_EXT_DATA(_name, _id, _subset_exts, _subset_exts_size, 
_validate) {  \
        .name = #_name,                                                         
        \
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index f7fcd23d55de..41fd0be25bd8 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -919,12 +919,12 @@ unsigned long riscv_get_elf_hwcap(void)
        return hwcap;
 }
 
-void riscv_user_isa_enable(void)
+void __init riscv_user_isa_enable(void)
 {
        if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOZ))
                current->thread_info.envcfg |= ENVCFG_CBZE;
        else if (any_cpu_has_zicboz)
-               pr_warn_once("Zicboz disabled as it is unavailable on some 
harts\n");
+               pr_warn("Zicboz disabled as it is unavailable on some harts\n");
 }
 
 #ifdef CONFIG_RISCV_ALTERNATIVE
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c
index 0f8f1c95ac38..e36d20205bd7 100644
--- a/arch/riscv/kernel/smpboot.c
+++ b/arch/riscv/kernel/smpboot.c
@@ -233,8 +233,6 @@ asmlinkage __visible void smp_callin(void)
        numa_add_cpu(curr_cpuid);
        set_cpu_online(curr_cpuid, true);
 
-       riscv_user_isa_enable();
-
        /*
         * Remote cache and TLB flushes are ignored while the CPU is offline,
         * so flush them both right now just in case.
-- 
2.45.0