RE: userspace access to cache geometry information

2010-10-18 Thread Catalin Marinas
On Sat, 2010-10-16 at 02:05 +0100, Woodruff, Richard wrote: > > From: linaro-dev-boun...@lists.linaro.org [mailto:linaro-dev- > > boun...@lists.linaro.org] On Behalf Of Peter Maydell > > > One of the Valgrind subtools is Cachegrind; this is a cache > > profiler. (It simulates the I1, D1 and L2 cac

RE: userspace access to cache geometry information

2010-10-15 Thread Woodruff, Richard
> From: linaro-dev-boun...@lists.linaro.org [mailto:linaro-dev- > boun...@lists.linaro.org] On Behalf Of Peter Maydell > One of the Valgrind subtools is Cachegrind; this is a cache > profiler. (It simulates the I1, D1 and L2 caches so it can > pinpoint the sources of cache misses in application co

Re: userspace access to cache geometry information

2010-10-15 Thread Dave Martin
On Fri, Oct 15, 2010 at 2:49 PM, Peter Maydell wrote: > One of the Valgrind subtools is Cachegrind; this is a cache > profiler. (It simulates the I1, D1 and L2 caches so it can > pinpoint the sources of cache misses in application code.) > > On x86 Cachegrind automatically queries the host CPU to

Re: userspace access to cache geometry information

2010-10-15 Thread Dave Martin
On Fri, Oct 15, 2010 at 2:49 PM, Peter Maydell wrote: > One of the Valgrind subtools is Cachegrind; this is a cache > profiler. (It simulates the I1, D1 and L2 caches so it can > pinpoint the sources of cache misses in application code.) > > On x86 Cachegrind automatically queries the host CPU to