On Sat, 2010-10-16 at 02:05 +0100, Woodruff, Richard wrote: > > From: linaro-dev-boun...@lists.linaro.org [mailto:linaro-dev- > > boun...@lists.linaro.org] On Behalf Of Peter Maydell > > > One of the Valgrind subtools is Cachegrind; this is a cache > > profiler. (It simulates the I1, D1 and L2 caches so it can > > pinpoint the sources of cache misses in application code.) > > Part of this info is exported to user space through /proc/cpuinfo > > Catalin did post a patch long back to fix up decode for v7. I recall > RMK not linking some aspect. The reasons are buried in mail archives. > IIRC it had to do with expectations around that interface and the > constant churn around he formatting that happened.
I recall the patch was originally implemented by Tony Thompson @ ARM but it wasn't accepted by RMK. But I think the patch wasn't giving enough information to be useful to cachegrind anyway. The cache configuration can be a lot more complex on ARMv7 onwards as you can have several levels of cache with different cache line sizes. We've had discussions in ARM in the past but I don't think we got to any clear conclusion. Maybe Linux could export a /sys filesystem with all the CPUID registers but care needs to be taken as simply checking for Neon features doesn't mean that the kernel supports them (or that the CPU doesn't have any associated errata). -- Catalin _______________________________________________ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
