ter we can have more detailed discussion.
Really great work, Nico. :-)
Thx,
Leo Yan
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Thx a lot, Lorenzo. It's much clear for me. :-)
On 03/11/2013 10:56 PM, Lorenzo Pieralisi wrote:
I'm curious if A15 use the MVA to invalidate icache, then will the DVM
contain the info of MVA and the range size? If it's ONLY include the
MVA, then A7 how to know it need invalidate 64 bytes' ran
ingle command.
Cache line size is just used as stride to for the cache function to be
optimized.
BTW, A15 TRM 6.3.6 explains what I tried to summarize above.
Thx for nicely reminding, i think i need read well A7/A15's TRM.
Thx,
Leo Yan
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cores still may have
valid icache lines, right?
Thx,
Leo Yan
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On 02/05/2013 04:17 PM, Jon Medhurst (Tixy) wrote:
On Tue, 2013-02-05 at 15:13 +0800, Leo Yan wrote:
On 01/29/2013 06:26 PM, Jon Medhurst (Tixy) wrote:
What I suspect is that the configuration in SITE1/HBI0249A/board.txt
isn't right, particularly the value for SCC 0x700. We are curr
C/DCC how to decide to wake up the core? it will ONLY
detect the pin assertion of WAKE_INT_STAT? If there have dvm on CCI,
then the core will be waken up as well?
Thx,
Leo Yan
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