On 01/29/2013 06:26 PM, Jon Medhurst (Tixy) wrote:
What I suspect is that the configuration in SITE1/HBI0249A/board.txt
isn't right, particularly the value for SCC 0x700. We are currently
putting the files and instructions together for the 13.01 release, but
if you use the attached board.txt file then I hope that will get the
system booting on all CPUs. (One quirk I found when swapping back and
forth between firmware versions is that it seemed to take two boots
before the changes firmware worked correctly, I don't know if that's
just something I'm doing different or if it is a general problem.)
Tixy, thx a lot for the board.txt.
Here i have some questions related with power management on TC2 board
with 13.01 release:
1. For core's C1 state:
From the latest kernel's code, now the C1 state means the core will be
powered off. so when the core wants to run into 'C1' state, then it need
set the BX_ADDR register; after the core run into the 'WFI' state then
the SPC/DCC will power off the core.
So we can if BX_ADDR != 0, that means the core will be powered off after
the core's STANDBYWFI pin has been asserted, right?
2. For core's wakeup:
We need wake up the core after the core run into low power mode, so in
the code now it will set the SPC's WAKE_INT_MASK register.
But now the code is a little confused me, for now the implementation
will set bits in the SPC's WAKE_INT_MASK register before the core run
into C1; from my understanding, if we set the bit in SPC's WAKE_INT_MASK
register, that means it will mask nIRQOUT/nFIQOUT from SPC to DCC, so
that DCC will NOT wake up the core anymore and the core cannot resume back.
Otherwise, if set the bit in WAKE_INT_MASK register it means we will
unmask the irq/fiq for the core; could someone can help confirm for this
question?
3. Sometimes after we placed the core in C1 state and don't want it to
be waken up anymore (for hotplug scenario or core's migration); but from
current code, i saw if i placed the big cluster's CA15_0 into C1, then
sometimes it will be waken up, at this point i checked the SPC's
WAKE_INT_RAW or WAKE_INT_STAT, the bit 0 (for IRQ) and bit 2 (for FIQ)
has not been set, so that means it's not caused by the interrupt which
it routes to the CA15_0.
So i just wander SPC/DCC how to decide to wake up the core? it will ONLY
detect the pin assertion of WAKE_INT_STAT? If there have dvm on CCI,
then the core will be waken up as well?
Thx,
Leo Yan
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