Hi Daniel,
- L1 D$ clean ( SCTLR C bit clear, DCCISW, clear SMP) is part of
the recommended sequence for Individual core power down .
- If a core is powered down having dirty lines in L1 then the
system should encounter an issue (abort) very easily. May be the first
On 14.10.13 19:03 +0100, Wookey wrote:
> +++ Antonio Terceiro [2013-10-14 11:19 -0300]:
> > On Fri, Oct 11, 2013 at 08:17:21AM +0100, Neil Williams wrote:
> > > If we could see the source code for google-talkplugin, it could be
> > > fixed
> >
> > Not going to happen ...
>
> Any word on whet
On 04/08/2014 01:07 PM, Amit Kucheria wrote:
Hi Daniel,
Have you noticed this on any platform yet with this test?
I have noticed a very very rare hang on the exynos4 board with this test
and the dual cpu support but it is not reproducible enough to check if
the cache flush fixes it or not (o
Hi Daniel,
Have you noticed this on any platform yet with this test?
Regards,
Amit
On Tue, Apr 8, 2014 at 4:05 PM, Daniel Lezcano wrote:
> As pointed by Lorenzo, when a cpu powers down, the L1 cache must be flushed
> before, otherwise:
>
> * data cachelines are not empty and the other cpu may
As pointed by Lorenzo, when a cpu powers down, the L1 cache must be flushed
before, otherwise:
* data cachelines are not empty and the other cpu may fetch data
* cpu will lost some data leading to a memory corruption
Note this bug is very difficult to reproduce and this test will not spot the
i
