Fix some issues reported by checkpatch.pl. Mostly whitespace, but also
includes min=>min_t, kzalloc=>kcalloc, and kmalloc=>kmalloc_array.
Signed-off-by: Mitchel Humpherys
---
drivers/iommu/arm-smmu.c | 59 ++--
1 file changed, 37 insertio
alone is:
arm-smmu.c:853: WARNING: line over 80 characters
#853: FILE: arm-smmu.c:853:
+ (MAIR_ATTR_WBRWA <<
MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
since it seems to be a case where "exceeding 80 columns significantly
increases readability and does not hide
#x27;t program the Stream Match Register
until after registering our interrupt handler so we shouldn't be missing
any interrupts.
Signed-off-by: Mitchel Humpherys
---
drivers/iommu/arm-smmu.c | 37 +
1 file changed, 17 insertions(+), 20 deletions(-)
diff --
#x27;t program the Stream Match Register
until after registering our interrupt handler so we shouldn't be missing
any interrupts.
Signed-off-by: Mitchel Humpherys
---
Changelog:
- v2: return error code from request_irq on failure
---
drivers/iommu/arm-smmu.c | 37 +-
On Mon, Jul 28 2014 at 12:03:27 PM, Will Deacon wrote:
> Hi Mitchel,
>
> Thanks for the quick v2, but now I spotted a problem :)
>
> On Mon, Jul 28, 2014 at 07:38:12PM +0100, Mitchel Humpherys wrote:
>> static void arm_smmu_destroy_domain_context(struct iommu_domain *d
#x27;t program the Stream Match Register
until after registering our interrupt handler so we shouldn't be missing
any interrupts.
Signed-off-by: Mitchel Humpherys
---
Changelog:
- v3: rework irq request code to avoid requesting the irq every
time a master is added to the domain
- v2:
On Wed, Jul 30 2014 at 08:31:14 AM, Will Deacon wrote:
> Hey Mitch,
>
> On Tue, Jul 29, 2014 at 07:11:15PM +0100, Mitchel Humpherys wrote:
>> request_irq shouldn't be called from atomic context since it might
>> sleep, but we're calling it wit
#x27;t program the Stream Match Register
until after registering our interrupt handler so we shouldn't be missing
any interrupts.
Signed-off-by: Mitchel Humpherys
---
Changelog:
- v4: some cleanup suggested by Will
- v3: rework irq request code to avoid requesting the irq every
time a
fifth and sixth handle some implementation-specific issues,
providing knobs in the device tree and a new domain attribute.
This series is based on on Will's iommu/pci branch.
Mitchel Humpherys (6):
iommu/arm-smmu: add support for specifying clocks
iommu/arm-smmu: add support for
Add a workaround for some buggy hardware that requires a TLB invalidate
operation to occur at map time. Activate the feature with the
qcom,smmu-invalidate-on-map boolean DT property.
Signed-off-by: Mitchel Humpherys
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 4
drivers
Generic IOMMU device tree bindings were recently added in
["devicetree: Add generic IOMMU device tree bindings"]. Implement the
bindings in the ARM SMMU driver.
See Documentation/devicetree/bindings/iommu/iommu.txt for the bindings
themselves.
Signed-off-by: Mitchel Humpherys
---
dri
for SMMU register access and turn them on and off as needed.
If no clocks are specified in the device tree things continue to work
the way they always have: we assume all necessary clocks are always
turned on.
Signed-off-by: Mitchel Humpherys
---
.../devicetree/bindings/iommu/arm,smmu.txt
On some power-constrained platforms it's useful to disable power when a
device is not in use. Add support for specifying regulators for SMMUs
and only leave power on as long as the SMMU is in use (attached).
Signed-off-by: Mitchel Humpherys
---
.../devicetree/bindings/iommu/arm,smm
useful for testing and hardware validation.
Since the address translation registers are optional on SMMUv2, only
enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1
and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec.
Signed-off-by: Mitchel Humpherys
---
drivers
Under certain conditions coherent hardware translation table walks can
result in degraded performance. Add a new domain attribute to
disable/enable this feature in generic code along with the domain
attribute setter and getter to handle it in the ARM SMMU driver.
Signed-off-by: Mitchel Humpherys
On Tue, Aug 12 2014 at 05:51:37 PM, Mitchel Humpherys
wrote:
> Generic IOMMU device tree bindings were recently added in
> ["devicetree: Add generic IOMMU device tree bindings"]. Implement the
> bindings in the ARM SMMU driver.
>
> See Documentation/devicetree/binding
On Tue, Aug 12 2014 at 05:51:33 PM, Mitchel Humpherys
wrote:
> This series is based on on Will's iommu/pci branch.
Incredibly, I also neglected to base this on top of Olav's recent patch
("iommu/arm-smmu: Do not access non-existing SMR registers")! I will do
that in v
Well hopefully this isn't too Nick Krouse-esque, but I have some
comments on my own patch below. I sat on these for a few days but have
noticed a few things after testing on another platform...
On Tue, Aug 12 2014 at 05:51:34 PM, Mitchel Humpherys
wrote:
> On some platforms with tig
On Tue, Aug 12 2014 at 05:51:35 PM, Mitchel Humpherys
wrote:
> On some power-constrained platforms it's useful to disable power when a
> device is not in use. Add support for specifying regulators for SMMUs
> and only leave power on as long as the SMMU is in use (attached).
>
On Tue, Aug 19 2014 at 05:44:32 AM, Will Deacon wrote:
> On Wed, Aug 13, 2014 at 01:51:36AM +0100, Mitchel Humpherys wrote:
>> Currently, we provide the iommu_ops.iova_to_phys service by doing a
>> table walk in software to translate IO virtual addresses to physical
>> add
On Tue, Aug 19 2014 at 05:48:07 AM, Will Deacon wrote:
> On Wed, Aug 13, 2014 at 01:51:39AM +0100, Mitchel Humpherys wrote:
>> Under certain conditions coherent hardware translation table walks can
>> result in degraded performance. Add a new domain attribute to
>> disable/e
On Tue, Aug 19 2014 at 05:58:34 AM, Will Deacon wrote:
> I also assume that the clk API ignores calls to clk_enable_prepare
> for a clk that's already enabled? I couldn't find that code...
That's clk_prepare_enable, not clk_enable_prepare. It's in
.
-Mitch
--
The Qualcomm Innovation Center, I
On Tue, Aug 26 2014 at 07:27:58 AM, Will Deacon wrote:
> [adding Mike]
>
> On Tue, Aug 19, 2014 at 08:03:09PM +0100, Olav Haugan wrote:
>> Hi Will,
>
> Hi Olav,
>
>> On 8/19/2014 5:58 AM, Will Deacon wrote:
>> > On Wed, Aug 13, 2014 at 01:51:34AM +0100,
On Wed, Sep 10 2014 at 11:27:39 AM, Will Deacon wrote:
> On Wed, Sep 10, 2014 at 02:29:42AM +0100, Mitchel Humpherys wrote:
>> On Tue, Aug 26 2014 at 07:27:58 AM, Will Deacon wrote:
>> > On Tue, Aug 19, 2014 at 08:03:09PM +0100, Olav Haugan wrote:
>> >> Clients of t
-off-by: Matt Wagantall
Signed-off-by: Mitchel Humpherys
---
include/linux/iopoll.h | 114 +
1 file changed, 114 insertions(+)
create mode 100644 include/linux/iopoll.h
diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h
new file mode
mp;m=140414727509158
Matt Wagantall (1):
iopoll: Introduce memory-mapped IO polling macros
Mitchel Humpherys (1):
iommu/arm-smmu: add support for iova_to_phys through ATS1PR
drivers/iommu/arm-smmu.c | 73 +-
include/linux/iopoll.h |
useful for testing and hardware validation.
Since the address translation registers are optional on SMMUv2, only
enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1
and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec.
Signed-off-by: Mitchel Humpherys
---
drivers
On Thu, Sep 11 2014 at 11:30:42 AM, Mitchel Humpherys
wrote:
> This series introduces support for performing iova-to-phys translations via
> the ARM SMMU hardware on supported implementations. We also make use of
> some new generic macros for polling hardware registers.
>
> Th
On Wed, Sep 10 2014 at 12:09:06 PM, Mitchel Humpherys
wrote:
> On Wed, Sep 10 2014 at 11:27:39 AM, Will Deacon wrote:
>> On Wed, Sep 10, 2014 at 02:29:42AM +0100, Mitchel Humpherys wrote:
>>> On Tue, Aug 26 2014 at 07:27:58 AM, Will Deacon wrote:
>>> > On Tue, Au
Some IOMMUs support access-protected mappings. Add a mapping flag to
indicate that the mapping should be created with access protection
configured.
Cc: Shubhraprakash Das
Signed-off-by: Mitchel Humpherys
---
include/linux/iommu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include
This series introduces a new mapping flag to indicate that the mapping
should be created with access protection applied. Support for this new flag
is then added to the ARM SMMU driver.
Mitchel Humpherys (2):
iommu: add IOMMU_PRIV flag for access-protected mappings
iommu/arm-smmu: add support
tency with nearby code.
Signed-off-by: Mitchel Humpherys
---
drivers/iommu/arm-smmu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index ca18d6d42a..93999ec22c 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers
so we only ever seem to
iterate this loop once. However, things might change in the future that
might cause us to hit this.
Signed-off-by: Mitchel Humpherys
---
Will, I was unable to come up with a test case to hit this bug based on
what I said in the commit message above. Not sure if my analys
On Fri, Sep 19 2014 at 03:05:36 PM, Will Deacon wrote:
> On Wed, Sep 17, 2014 at 09:16:09PM +0100, Mitchel Humpherys wrote:
>> ARM SMMUs support memory access control via some bits in the translation
>> table descriptor memory attributes. Currently we assume all translations
>&
On Mon, Sep 22 2014 at 08:26:14 AM, Will Deacon wrote:
> Hi Mitch,
>
> On Thu, Sep 11, 2014 at 07:30:44PM +0100, Mitchel Humpherys wrote:
>> Currently, we provide the iommu_ops.iova_to_phys service by doing a
>> table walk in software to translate IO virtual addresses to phys
On Wed, Sep 24 2014 at 09:37:12 AM, Will Deacon wrote:
> On Wed, Sep 24, 2014 at 02:12:00AM +0100, Mitchel Humpherys wrote:
>> On Mon, Sep 22 2014 at 08:26:14 AM, Will Deacon wrote:
>> > On Thu, Sep 11, 2014 at 07:30:44PM +0100, Mitchel Humpherys wrote:
>
On Fri, Sep 26 2014 at 03:24:30 AM, Will Deacon wrote:
> On Wed, Sep 24, 2014 at 09:34:26PM +0100, Mitchel Humpherys wrote:
>> On Wed, Sep 24 2014 at 09:37:12 AM, Will Deacon wrote:
>> > On Wed, Sep 24, 2014 at 02:12:00AM +0100, Mitchel Humpherys wrote:
>> >> On M
'
suffix
- Removed some convenience iopoll wrappers to encourage explicitness
Matt Wagantall (1):
iopoll: Introduce memory-mapped IO polling macros
Mitchel Humpherys (1):
iommu/arm-smmu: add support for iova_to_phys through ATS1PR
drivers/iommu/arm-smmu.c
-off-by: Matt Wagantall
Signed-off-by: Mitchel Humpherys
---
include/linux/iopoll.h | 77 ++
1 file changed, 77 insertions(+)
create mode 100644 include/linux/iopoll.h
diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h
new file mode 100644
useful for testing and hardware validation.
Since the address translation registers are optional on SMMUv2, only
enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1
and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec.
Signed-off-by: Mitchel Humpherys
---
drivers
On Sat, Sep 27 2014 at 02:31:51 PM, Mitchel Humpherys
wrote:
> This series introduces support for performing iova-to-phys translations via
> the ARM SMMU hardware on supported implementations. We also make use of
> some new generic macros for polling hardware registers.
>
> C
-off-by: Matt Wagantall
Signed-off-by: Mitchel Humpherys
---
include/linux/iopoll.h | 77 ++
1 file changed, 77 insertions(+)
create mode 100644 include/linux/iopoll.h
diff --git a/include/linux/iopoll.h b/include/linux/iopoll.h
new file mode 100644
uffix
- Removed some convenience iopoll wrappers to encourage explicitness
v2..v3:
- Remomved unnecessary `dev_name's
Matt Wagantall (1):
iopoll: Introduce memory-mapped IO polling macros
Mitchel Humpherys (1):
iommu/arm-smmu: add support for iova_to_phys through ATS1PR
drivers
useful for testing and hardware validation.
Since the address translation registers are optional on SMMUv2, only
enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1
and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec.
Signed-off-by: Mitchel Humpherys
---
drivers
On Mon, Sep 29 2014 at 01:31:37 AM, Thierry Reding
wrote:
> On Sat, Sep 27, 2014 at 08:27:28PM -0700, Mitchel Humpherys wrote:
>> From: Matt Wagantall
>>
>> It is sometimes necessary to poll a memory-mapped register until its
>> value satisfies some condition. Introd
gantall (1):
iopoll: Introduce memory-mapped IO polling macros
Mitchel Humpherys (1):
iommu/arm-smmu: add support for iova_to_phys through ATS1PR
drivers/iommu/arm-smmu.c | 79 +++-
include/linux/iopoll.h | 77 +++
useful for testing and hardware validation.
Since the address translation registers are optional on SMMUv2, only
enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1
and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec.
Signed-off-by: Mitchel Humpherys
---
Changes
Deacon
Signed-off-by: Matt Wagantall
Signed-off-by: Mitchel Humpherys
---
Changes since v3:
- Updated commit message to better reflect the patch content
---
include/linux/iopoll.h | 77 ++
1 file changed, 77 insertions(+)
create mode 100644 include
On Tue, Sep 30 2014 at 03:23:34 AM, Will Deacon wrote:
> Hi Mitch,
>
> On Sun, Sep 28, 2014 at 04:27:29AM +0100, Mitchel Humpherys wrote:
>> Currently, we provide the iommu_ops.iova_to_phys service by doing a
>> table walk in software to translate IO virtual addresses to phys
On Wed, Oct 01 2014 at 01:27:27 AM, Arnd Bergmann wrote:
> On Tuesday 30 September 2014 18:28:13 Mitchel Humpherys wrote:
>> + if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,
>> + !(tmp & ATSR_ACTIVE), 50, 100)) {
>>
On Mon, Oct 06 2014 at 03:28:16 AM, Varun Sethi
wrote:
> This flag is used for specifying access to device memory. SMMU would apply
> device memory attributes for a DMA transaction. This is required for setting
> access to GIC registers, for generating message interrupts. This would ensure
> tha
On Wed, Oct 01 2014 at 01:25:33 AM, Arnd Bergmann wrote:
> On Tuesday 30 September 2014 18:28:12 Mitchel Humpherys wrote:
>> + */
>> +#define readl_poll_timeout(addr, val, cond, sleep_us, timeout_us) \
>> +({ \
>> + ktime_t timeout = ktime_add
On Tue, Oct 07 2014 at 06:47:59 PM, Mitchel Humpherys
wrote:
>>> +#define readl_poll_timeout_atomic(addr, val, cond, max_reads,
>>> time_between_us) \
>>> +({ \
>>> + int count; \
>>> + for (count = (max_reads); count > 0; cou
ilure
v2..v3:
- Removed unnecessary `dev_name's
v1..v2:
- Renamed one of the iopoll macros to use the more standard `_atomic'
suffix
- Removed some convenience iopoll wrappers to encourage explicitness
Matt Wagantall (1):
iopoll: Introduce memory-mapped IO polling macros
Mi
useful for testing and hardware validation.
Since the address translation registers are optional on SMMUv2, only
enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1
and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec.
Signed-off-by: Mitchel Humpherys
---
Changes
Deacon
Signed-off-by: Matt Wagantall
Signed-off-by: Mitchel Humpherys
---
Changes since v4:
- Added support for other accessor functions
- Unified atomic and non-atomic interfaces
- Fixed erroneous `might_sleep' (we were might_sleep()'ing on the wrong
variable)
---
include/linu
On Wed, Oct 08 2014 at 06:40:46 AM, Arnd Bergmann wrote:
> On Tuesday 07 October 2014 18:47:59 Mitchel Humpherys wrote:
>> On Wed, Oct 01 2014 at 01:25:33 AM, Arnd Bergmann wrote:
>> > On Tuesday 30 September 2014 18:28:12 Mitchel Humpherys wrote:
>> >> + */
>
On Fri, Oct 10 2014 at 12:50:23 PM, Arnd Bergmann wrote:
> On Friday 10 October 2014 12:44:45 Mitchel Humpherys wrote:
>> >> Regarding the division, for the overwhelmingly common case where the
>> >> user of the API passes in a constant for sleep_us the compil
oll wrappers to encourage explicitness
Matt Wagantall (1):
iopoll: Introduce memory-mapped IO polling macros
Mitchel Humpherys (1):
iommu/arm-smmu: add support for iova_to_phys through ATS1PR
drivers/iommu/arm-smmu.c | 79 +-
include/linux/i
useful for testing and hardware validation.
Since the address translation registers are optional on SMMUv2, only
enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1
and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec.
Signed-off-by: Mitchel Humpherys
---
Changes
Deacon
Signed-off-by: Matt Wagantall
Signed-off-by: Mitchel Humpherys
---
Changes since v5:
- Use a shift instead of a divide in the poll loop.
---
include/linux/iopoll.h | 213 +
1 file changed, 213 insertions(+)
create mode 100644 include/linux
On Tue, Oct 14 2014 at 02:53:29 PM, Mitchel Humpherys
wrote:
> From: Matt Wagantall
>
> It is sometimes necessary to poll a memory-mapped register until its value
> satisfies some condition. Introduce a family of convenience macros that do
> this. Tight-looping, sleeping, and tim
useful for testing and hardware validation.
Since the address translation registers are optional on SMMUv2, only
enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1
and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec.
Signed-off-by: Mitchel Humpherys
---
Changes
Deacon
Signed-off-by: Matt Wagantall
Signed-off-by: Mitchel Humpherys
---
Changes since v6:
- No changes. Resending due to changes in the the next patch in the series.
---
include/linux/iopoll.h | 213 +
1 file changed, 213 insertions(+)
create mode
ame's
v1..v2:
- Renamed one of the iopoll macros to use the more standard `_atomic'
suffix
- Removed some convenience iopoll wrappers to encourage explicitness
Matt Wagantall (1):
iopoll: Introduce memory-mapped IO polling macros
Mitchel Humpherys (1):
iommu/arm-smmu:
On Thu, Oct 30 2014 at 05:00:23 AM, Arnd Bergmann wrote:
> On Thursday 30 October 2014 11:41:00 Will Deacon wrote:
>> > +
>> > +#define readl_poll_timeout(addr, val, cond, delay_us, timeout_us) \
>> > + readx_poll_timeout(readl, addr, val, cond, delay_us, timeout_us)
>> > +
>> > +#define readl_po
On Wed, Nov 12 2014 at 10:26:43 AM, Will Deacon wrote:
> Hi Mitch,
>
> On Wed, Aug 13, 2014 at 01:51:38AM +0100, Mitchel Humpherys wrote:
>> Add a workaround for some buggy hardware that requires a TLB invalidate
>> operation to occur at map time. Activate the feature
On Thu, Nov 13 2014 at 01:48:26 AM, Will Deacon wrote:
> Ha, damn, then I don't have a user of the shiny new quirks field I added!
> I don't think I'll go as far as removing it altogether though...
I'm sure we'll be making liberal use of that field soon enough ;)
-Mitch
--
Qualcomm Innovatio
Deacon
Cc: Arnd Bergmann
Signed-off-by: Matt Wagantall
Signed-off-by: Mitchel Humpherys
---
Sorry for any confusion regarding the genesis of this patch. Let me try to
clarify the history here. This patch was originally part of a series [1]
for adding support for IOMMU address translations through
On Fri, Nov 21 2014 at 03:48:33 AM, Stefano Stabellini
wrote:
> On Mon, 17 Nov 2014, Stefano Stabellini wrote:
>> Hi all,
>> I am writing this email to ask for your advice.
>>
>> On architectures where dma addresses are different from physical
>> addresses, it can be difficult to retrieve the ph
Deacon
Cc: Arnd Bergmann
Cc: Andrew Morton
Signed-off-by: Matt Wagantall
Signed-off-by: Mitchel Humpherys
---
This patch was originally part of a series [1] for adding support for IOMMU
address translations through an ARM SMMU hardware register. The other
patch in the series (the one that actually
On Mon, Nov 24 2014 at 04:53:19 PM, "Elliott, Robert (Server Storage)"
wrote:
>> -Original Message-
>> From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel-
>> ow...@vger.kernel.org] On Behalf Of Mitchel Humpherys
>> Sent: Monday, 24 November
On Thu, Nov 27 2014 at 03:51:16 AM, Will Deacon wrote:
> A number of IOMMUs found in ARM SoCs can walk architecture-compatible
> page tables.
>
> This patch adds a generic allocator for Stage-1 and Stage-2 v7/v8
> long-descriptor page tables. 4k, 16k and 64k pages are supported, with
> up to 4-lev
Deacon
Cc: Arnd Bergmann
Cc: Andrew Morton
Cc: Robert Elliott
Signed-off-by: Matt Wagantall
Signed-off-by: Mitchel Humpherys
---
v8..v9:
- Added note in comments about max sleep time (Rob Elliott)
v7..v8:
- sorted helper macros by size (b, w, l, q)
- removed some of the more esoteric (or
On Mon, Dec 15 2014 at 03:31:20 PM, Mitchel Humpherys
wrote:
> From: Matt Wagantall
>
> It is sometimes necessary to poll a memory-mapped register until its value
> satisfies some condition. Introduce a family of convenience macros that do
> this. Tight-looping, sleeping, and tim
Deacon
Cc: Arnd Bergmann
Cc: Andrew Morton
Cc: Robert Elliott
Signed-off-by: Matt Wagantall
Signed-off-by: Mitchel Humpherys
---
v9..10:
- Actually added the comments mentioned in v8..v9 (doh!)
v8..v9:
- Added note in comments about max sleep time (Rob Elliott)
v7..v8:
- sorted helper
Currently we do a STLBIALL when we initialize the SMMU. However, in
some configurations that register is not supposed to be touched and is
marked as "Secure only" in the spec. Rip it out.
Signed-off-by: Mitchel Humpherys
---
drivers/iommu/arm-smmu.c | 2 --
1 file changed, 2
On Tue, Jan 06 2015 at 06:15:07 AM, Will Deacon wrote:
>> /* Invalidate the TLB, just in case */
>> -writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
>> writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
>> writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
>
> I was
On Tue, Jan 06 2015 at 02:35:28 PM, Rob Herring wrote:
> On Tue, Jan 6, 2015 at 2:16 PM, Mitchel Humpherys
> wrote:
>> On Tue, Jan 06 2015 at 06:15:07 AM, Will Deacon wrote:
>>>> /* Invalidate the TLB, just in case */
>>>> -writel_relaxed
On Wed, Jan 07 2015 at 02:13:00 AM, Will Deacon wrote:
> On Tue, Jan 06, 2015 at 11:30:49PM +0000, Mitchel Humpherys wrote:
>> On Tue, Jan 06 2015 at 02:35:28 PM, Rob Herring
>> wrote:
>> > On Tue, Jan 6, 2015 at 2:16 PM, Mitchel Humpherys
>> > wrote:
>>
On Wed, Jan 07 2015 at 10:04:20 AM, Will Deacon wrote:
> On Wed, Jan 07, 2015 at 05:52:46PM +0000, Mitchel Humpherys wrote:
>> On Wed, Jan 07 2015 at 02:13:00 AM, Will Deacon wrote:
>> > On Tue, Jan 06, 2015 at 11:30:49PM +, Mitchel Humpherys wrote:
>> >> On T
On Tue, Dec 16 2014 at 01:45:27 AM, Will Deacon wrote:
> On Mon, Dec 15, 2014 at 11:47:23PM +0000, Mitchel Humpherys wrote:
>> From: Matt Wagantall
>>
>> It is sometimes necessary to poll a memory-mapped register until its value
>> satisfies some condition. Introd
On Tue, Jan 20 2015 at 06:16:43 AM, Will Deacon wrote:
> Hey Mitch,
>
> On Wed, Oct 29, 2014 at 09:13:40PM +, Mitchel Humpherys wrote:
>> Currently, we provide the iommu_ops.iova_to_phys service by doing a
>> table walk in software to translate IO virtual addresses to
way for doing things like enabling clocks within
our interrupt handler.
Signed-off-by: Mitchel Humpherys
---
drivers/iommu/arm-smmu.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 6cd47b75286f..81f6b54d94b1 100644
On Fri, Jan 23 2015 at 03:24:15 AM, Will Deacon wrote:
> Hi Mitch,
>
> On Thu, Jan 22, 2015 at 11:48:02PM +, Mitchel Humpherys wrote:
>> Context interrupts can call domain-specific handlers which might sleep.
>> Currently we register our handler with request_irq, so our
On Wed, Jan 28 2015 at 04:07:39 AM, Will Deacon wrote:
> On Fri, Jan 23, 2015 at 10:33:20PM +0000, Mitchel Humpherys wrote:
>> On Fri, Jan 23 2015 at 03:24:15 AM, Will Deacon wrote:
>> > On Thu, Jan 22, 2015 at 11:48:02PM +, Mitchel Humpherys wrote:
>> >> Cont
On Wed, Feb 04 2015 at 03:33:05 AM, Will Deacon wrote:
> On Mon, Feb 02, 2015 at 08:10:02PM +0000, Mitchel Humpherys wrote:
>> On Wed, Jan 28 2015 at 04:07:39 AM, Will Deacon wrote:
>> > With a shared handler (e.g. a bunch of context banks have the same IRQ)
>> > then
mmediately following the map.
Without this, eventually swiotlb runs out of memory and starts printing
things like:
[ 35.545076] arm-smmu d0.arm,smmu: swiotlb buffer is full (sz: 128
bytes)
Signed-off-by: Mitchel Humpherys
---
drivers/iommu/arm-smmu.c | 9 +++--
1 file changed, 7
On Thu, Mar 05 2015 at 02:38:45 AM, Robin Murphy wrote:
> Hi Mitch,
>
> On 05/03/15 00:18, Mitchel Humpherys wrote:
>> We're currently mapping a page in arm_smmu_flush_pgtable without ever
>> unmapping it. Fix this by calling dma_unmap_page on the returned dma
>>
buffers and flushing those instead, if said page tables
> happen to lie outside the default 32-bit mask.
>
> Signed-off-by: Robin Murphy
Tested-by: Mitchel Humpherys
Thanks Robin!
-Mitch
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the
On Fri, Mar 06 2015 at 02:48:17 AM, wrote:
> From: Yong Wu
>
> This patch adds support for mediatek m4u (MultiMedia Memory Management Unit).
> Currently this only supports m4u gen 2 with 2 levels of page table on mt8173.
[...]
> +static int mtk_iommu_invalidate_tlb(const struct mtk_iommu_info *
On Mon, Mar 09 2015 at 05:16:26 AM, Yong Wu wrote:
> Dear Mitchel,
> Thanks very much for your review.
>
> On Fri, 2015-03-06 at 09:15 -0800, Mitchel Humpherys wrote:
>> On Fri, Mar 06 2015 at 02:48:17 AM, wrote:
>> > From: Yong Wu
>> >
>>
.
Signed-off-by: Mitchel Humpherys
---
drivers/iommu/arm-smmu.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 2409e3bd3df2..a1b0f542d5ca 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu
to the iommu_ops which can optionally be
used by the driver to return a domain-specific pgsize_bitmap.
Signed-off-by: Mitchel Humpherys
---
drivers/iommu/iommu.c | 28 +++-
include/linux/iommu.h | 3 +++
2 files changed, 22 insertions(+), 9 deletions(-)
diff --git a
On Wed, Apr 06 2016 at 11:47:19 AM, Robin Murphy wrote:
> How would you handle said restriction of page sizes under this scheme?
I have a custom io-pgtable implementation that gets wired up based on an
IOMMU domain attribute, which is set by yet another custom DMA mapper.
My main goal is to give
On Thu, Apr 07 2016 at 12:29:59 PM, Mitchel Humpherys
wrote:
>> I'll clean up what I have and try to get it posted this afternoon so
>> we can compare.
>
> Cool, I have some comments that I'll leave over there.
Never mind, my comments weren't relevant. I&#x
Hey there,
We're experiencing an issue with IOMMU groups and PCI-e devices. The
system in question has a WLAN DMA master behind a PCI-e root complex
which is, in turn, behind an IOMMU. There are no there devices behind
the RC. This is on an ARM platform using the arm-smmu and pci-msm
drivers (p
On Thu, May 26 2016 at 11:58:53 AM, Robin Murphy wrote:
> Hey Mitch,
>
> On 26/05/16 01:26, Mitchel Humpherys wrote:
>> Hey there,
>>
>> We're experiencing an issue with IOMMU groups and PCI-e devices. The
>> system in question has a WLAN DMA master behin
On Wed, May 25 2016 at 08:45:58 PM, Alex Williamson
wrote:
>> Why do we do that? If the devices have different BDFs can't we safely
>> say that they're protected from peer-to-peer DMA (assuming no DMA
>> aliasing quirks)? Even as I write that out it seems wrong though since
>> the RC can probab
rm: add support for the IOMMU_PRIV flag
Mitchel Humpherys (2):
iommu: add IOMMU_PRIV attribute
Revert "iommu/arm-smmu: Treat all device transactions as unprivileged"
drivers/iommu/arm-smmu.c | 5 +
drivers/iommu/io-pgtable-arm.c | 16 +++-
include/linux
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