On Mon, Feb 18, 2019 at 05:01:59PM +, Robin Murphy wrote:
> On 18/02/2019 14:37, Stanislaw Gruszka wrote:
> [...]
> >Another issue is that dma_map_sg() & dma_map_page() may require some
> >constraints. I'm not sure about that and I want to clarify that with
> >CCed mm maintainers. I think DMA d
On Tue, Feb 19, 2019 at 12:57:18AM +0200, Meelis Roos wrote:
> I tried latest Linux on HP A180C (32-bit pa-risc). It works but the Zalon
> SCSI driver barfs warnings for GSC addon differential scsi board.
>
> The warnings seem to be DMA API related. Packaged 4.19 and self-compiled
> 5.0.0-rc7 exh
On Fri, 15 Feb 2019 17:33:34 +
Jean-Philippe Brucker wrote:
> Hi Jacob, Lu,
>
> On 30/01/2019 19:05, Jacob Pan wrote:
> > On Mon, 12 Nov 2018 14:44:57 +0800
> > Lu Baolu wrote:
> >
> >> This adds APIs for IOMMU drivers and device drivers to manage
> >> the PASIDs used for DMA transfer an
From: Kuppuswamy Sathyanarayanan
Intel IOMMU responds automatically when receiving page-requests from
a PCIe endpoint and the page-request queue is full and it cannot accept
any more page-requests. When it auto-responds to page-requests with a
success to the endpoint, it automatically responds wi
From: Kuppuswamy Sathyanarayanan
Return the PRG Response PASID Required bit in the Page Request
Status Register.
As per PCIe spec r4.0, sec 10.5.2.3, if this bit is Set, the device
expects a PASID TLP Prefix on PRG Response Messages when the
corresponding Page Requests had a PASID TLP Prefix. If
From: Kuppuswamy Sathyanarayanan
In Intel IOMMU, if the Page Request Queue (PRQ) is full, it will
automatically respond to the device with a success message as a keep
alive. And when sending the success message, IOMMU will include PASID in
the Response Message when the Page Request has a PASID in
From: Kuppuswamy Sathyanarayanan
As per Intel vt-d specification, Rev 3.0 (section 7.5.1.1, title
"Page Request Descriptor"), Intel IOMMU page request descriptor
only uses bits[63:12] of the Page Address. Hence its required to
enforce that the device will only send page request with
page-aligned
From: Kuppuswamy Sathyanarayanan
As per Intel vt-d specification, Rev 3.0 (section 7.5.1.1, title "Page
Request Descriptor"), Intel IOMMU page request descriptor only uses
bits[63:12] of the page address. Hence Intel IOMMU driver would only
permit devices that advertise they would only send Page
From: Kuppuswamy Sathyanarayanan
Return the Page Aligned Request bit in the ATS Capability Register.
As per PCIe spec r4.0, sec 10.5.1.2, if the Page Aligned Request bit is
set, it indicates the Untranslated Addresses generated by the device are
always aligned to a 4096 byte boundary.
An IOMMU
On Sun, Feb 17, 2019 at 1:06 AM Yong Wu wrote:
>
> This patch adds decriptions for mt8183 IOMMU and SMI.
>
> mt8183 has only one M4U like mt8173 and is also MTK IOMMU gen2 which
> uses ARM Short-Descriptor translation table format.
>
> The mt8183 M4U-SMI HW diagram is as below:
>
>
On Sun, Feb 17, 2019 at 1:08 AM Yong Wu wrote:
>
> Both mt8173 and mt8183 don't have this vld_pa_rng(valid physical address
> range) register while mt2712 have. Move it into the plat_data.
>
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
___
iommu m
On Sun, Feb 17, 2019 at 1:08 AM Yong Wu wrote:
>
> The protect memory setting is a little different in the different SoCs.
> In the register REG_MMU_CTRL_REG(0x110), the TF_PROT(translation fault
> protect) shift bit is normally 4 while it shift 5 bits only in the
> mt8173. This patch delete the c
On Sun, Feb 17, 2019 at 1:08 AM Yong Wu wrote:
>
> The M4U IP blocks in mt8183 is MediaTek's generation2 M4U which use
> the ARM Short-descriptor like mt8173, and most of the HW registers
> are the same.
>
> Here list main differences between mt8183 and mt8173/mt2712:
> 1) mt8183 has only one M4U
On Sun, Feb 17, 2019 at 1:08 AM Yong Wu wrote:
>
> In mt8173 and mt8183, 0x48 is REG_MMU_STANDARD_AXI_MODE while it is
> REG_MMU_CTRL in the other SoCs, and the bits meaning is completely
> different with the REG_MMU_STANDARD_AXI_MODE.
>
> This patch moves this property to plat_data, it's also a p
On Sun, Feb 17, 2019 at 1:07 AM Yong Wu wrote:
>
> MediaTek extend the arm v7s descriptor to support the dram over 4GB.
>
> In the mt2712 and mt8173, it's called "4GB mode", the physical address
> is from 0x4000_ to 0x1_3fff_, but from EMI point of view, it
> is remapped to high address fr
On Sun, Feb 17, 2019 at 1:09 AM Yong Wu wrote:
>
> There are 2 mmu cells in a M4U HW. we could adjust some larbs entering
> mmu0 or mmu1 to balance the bandwidth via the smi-common register
> SMI_BUS_SEL(0x220)(Each larb occupy 2 bits).
>
> In mt8183, For better performance, we switch larb1/2/5/7
On Sun, Feb 17, 2019 at 1:09 AM Yong Wu wrote:
>
> This patch only rename the variable name from enable_4GB to
> dram_is_4gb for readable.
>
> Signed-off-by: Yong Wu
Nice, this is clearer.
Reviewed-by: Evan Green
___
iommu mailing list
iommu@lists.li
On Sun, Feb 17, 2019 at 1:09 AM Yong Wu wrote:
>
> The "mediatek,larb-id" has already been parsed in MTK IOMMU driver.
> It's no need to parse it again in SMI driver. Only clean some codes.
> This patch is fit for all the current mt2701, mt2712, mt7623, mt8173
> and mt8183.
>
> After this patch, t
On Sun, Feb 17, 2019 at 1:09 AM Yong Wu wrote:
>
> In the 4GB mode, the physical address is remapped,
>
> Here is the detailed remap relationship.
> CPU PA ->HW PA
> 0x4000_ 0x1_4000_ (Add bit32)
> 0x8000_ 0x1_8000_ ...
> 0xc000_ 0x1_c000_
> From: Alex Williamson [mailto:alex.william...@redhat.com]
> Sent: Friday, February 15, 2019 4:15 AM
> To: Lu Baolu
> Subject: Re: [PATCH v6 0/9] vfio/mdev: IOMMU aware mediated device
>
> On Wed, 13 Feb 2019 12:02:52 +0800
> Lu Baolu wrote:
>
> > Hi,
> >
> > The Mediate Device is a framework
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