Hi Mark,
On 4/12/2018 7:56 AM, Marc Zyngier wrote:
On 12/04/18 11:17, Robin Murphy wrote:
On 11/04/18 17:54, Marc Zyngier wrote:
Hi Sammer,
On 11/04/18 16:58, Goel, Sameer wrote:
On 3/28/2018 9:00 AM, Marc Zyngier wrote:
On 2018-03-28 15:39, Timur Tabi wrote:
From: Sameer Goel
Set SMMU
capable of describing SMMU MSI topology (ACPI IORT prior to rev.C).
Remedy this by checking msi_domain before attempting to allocate SMMU
MSIs.
Signed-off-by: Nate Watterson
Signed-off-by: Sinan Kaya
---
drivers/iommu/arm-smmu-v3.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
di
.
Better reduce the message level.
Signed-off-by: Sinan Kaya
Signed-off-by: Nate Watterson
---
drivers/iommu/arm-smmu-v3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 744592d..2118fda 100644
--- a/drivers/iommu
Hi Robin,
On 11/29/2017 6:29 AM, Robin Murphy wrote:
Hi Nate,
On 29/11/17 07:07, Nate Watterson wrote:
Hi Robin,
On 11/28/2017 12:27 PM, Robin Murphy wrote:
Bring io-pgtable-arm in line with the ARMv8.2-LPA feature allowing
52-bit physical addresses when using the 64KB translation granule
Hi Robin,
On 11/28/2017 12:27 PM, Robin Murphy wrote:
Bring io-pgtable-arm in line with the ARMv8.2-LPA feature allowing
52-bit physical addresses when using the 64KB translation granule.
This will be supported by SMMUv3.1.
Signed-off-by: Robin Murphy
---
drivers/iommu/io-pgtable-arm.c | 65
from someone else.
Tested-by: Nate Watterson
Thanks,
Nate
iommu/arm-smmu: add support for unmap a memory range with only one tlb
sync
drivers/iommu/arm-smmu-v3.c| 52 ++
drivers/iommu/arm-smmu.c | 10
drivers/iommu/io-pgta
g the bool to callers is probably simpler. One nit, can you
document it in the kerneldoc comment too? With that:
Reviewed-by: Robin Murphy
Thanks,
Robin.
[1]:https://www.mail-archive.com/iommu@lists.linux-foundation.org/msg19758.html
This patch completely resolves the issue I reported in [1]!!
T
nce at ~95% of passthrough mode.
I also got similar results by altogether removing the 32-bit allocation
from iommu_dma_alloc_iova() which makes me wonder why we even bother.
What (PCIe) workloads have been shown to actually benefit from it?
Tested-by: Nate Watterson
-Nate
Robin.
Hi Robin,
On 8/18/2017 1:33 PM, Robin Murphy wrote:
Hi all,
Waiting for the command queue to drain for CMD_SYNC completion is likely
a contention hotspot on high-core-count systems. If the SMMU is coherent
and supports MSIs, though, we can use this cool feature (as suggested by
the architecture
Hi Robin,
On 7/31/2017 7:42 AM, Robin Murphy wrote:
Hi Nate,
On 29/07/17 04:57, Nate Watterson wrote:
Hi Robin,
I am seeing a crash when performing very basic testing on this series
with a Mellanox CX4 NIC. I dug into the crash a bit, and think this
patch is the culprit, but this rcache
Hi Robin,
I am seeing a crash when performing very basic testing on this series
with a Mellanox CX4 NIC. I dug into the crash a bit, and think this
patch is the culprit, but this rcache business is still mostly
witchcraft to me.
# ifconfig eth5 up
# ifconfig eth5 down
Unable to handle kernel
Hi Jonathan,
[...]
Hi All,
I'm a bit of late entry to this discussion. Just been running some more
detailed tests on our d05 boards and wanted to bring some more numbers to
the discussion.
All tests against 4.12 with the following additions:
* Robin's series removing the io-pgtable spin
Hi Jonathan,
On 7/17/2017 10:23 AM, Jonathan Cameron wrote:
On Mon, 17 Jul 2017 14:06:42 +0100
John Garry wrote:
+
On 29/06/2017 03:08, Leizhen (ThunderTown) wrote:
On 2017/6/28 17:32, Will Deacon wrote:
Hi Zhen Lei,
Nate (CC'd), Robin and I have been working on something very similar t
I should have removed the '-v3' since this revision of the patch adds
shutdown to arm-smmu.c as well. I'll fix that in a subsequent version
after waiting to see if there are additional changes that need to be
made.
On 6/29/2017 6:18 PM, Nate Watterson wrote:
The shutdown meth
The shutdown method disables the SMMU to avoid corrupting a new kernel
started with kexec.
Signed-off-by: Nate Watterson
---
drivers/iommu/arm-smmu-v3.c | 7 +++
drivers/iommu/arm-smmu.c| 6 ++
2 files changed, 13 insertions(+)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers
On 6/29/2017 2:34 PM, Will Deacon wrote:
On Thu, Jun 29, 2017 at 01:40:15PM -0400, Nate Watterson wrote:
The shutdown method disables the SMMU and its interrupts to avoid
potentially corrupting a new kernel started with kexec.
Signed-off-by: Nate Watterson
---
drivers/iommu/arm-smmu-v3.c
The shutdown method disables the SMMU and its interrupts to avoid
potentially corrupting a new kernel started with kexec.
Signed-off-by: Nate Watterson
---
drivers/iommu/arm-smmu-v3.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu
Hi Robin,
On 6/8/2017 7:51 AM, Robin Murphy wrote:
Hi all,
Here's the cleaned up nominally-final version of the patches everybody's
keen to see. #1 is just a non-critical thing-I-spotted-in-passing fix,
#2-#4 do some preparatory work (and bid farewell to everyone's least
favourite bit of code,
Hi Jean-Philippe,
On 5/24/2017 2:01 PM, Jean-Philippe Brucker wrote:
PCIe devices can implement their own TLB, named Address Translation Cache
(ATC). In order to support Address Translation Service (ATS), the
following changes are needed in software:
* Enable ATS on endpoints when the system su
Hi Lorenzo,
On 5/23/2017 5:26 AM, Lorenzo Pieralisi wrote:
On Tue, May 23, 2017 at 02:31:17PM +0530, Sricharan R wrote:
Hi Lorenzo,
On 5/23/2017 2:22 PM, Lorenzo Pieralisi wrote:
On Tue, May 23, 2017 at 02:26:10AM -0400, Nate Watterson wrote:
Hi Sricharan,
On 4/10/2017 7:21 AM, Sricharan R
Hi Sricharan,
On 4/10/2017 7:21 AM, Sricharan R wrote:
This is an equivalent to the DT's handling of the iommu master's probe
with deferred probing when the corrsponding iommu is not probed yet.
The lack of a registered IOMMU can be caused by the lack of a driver for
the IOMMU, the IOMMU device
On 5/16/2017 3:55 PM, Auger Eric wrote:
Hi,
On 13/04/2017 21:38, Nate Watterson wrote:
Hi Robin,
On 4/13/2017 7:21 AM, Robin Murphy wrote:
Hi Nate,
On 13/04/17 09:55, Nate Watterson wrote:
Currently, the __iommu_dma_{map/free} functions call iova_{offset/align}
making them unsuitable for
Hi Robin,
On 4/13/2017 7:21 AM, Robin Murphy wrote:
Hi Nate,
On 13/04/17 09:55, Nate Watterson wrote:
Currently, the __iommu_dma_{map/free} functions call iova_{offset/align}
making them unsuitable for use with iommu_domains having an IOMMU_DMA_MSI
cookie since the cookie's iova_domain m
p MSI IOVA allocation")
Signed-off-by: Nate Watterson
---
drivers/iommu/dma-iommu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index 8348f366..d7b0816 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-io
Hi Robin,
On 4/6/2017 2:56 PM, Robin Murphy wrote:
On 06/04/17 19:15, Manoj Iyer wrote:
On Fri, 31 Mar 2017, Robin Murphy wrote:
With IOVA allocation suitably tidied up, we are finally free to opt in
to the per-CPU caching mechanism. The caching alone can provide a modest
improvement over walk
{0, 0} /* Expected */
*good_iova == {2, 3} /* Expected */
*bad_iova == {-2, -1} /* Oh no... */
After the patch, bad_iova is NULL as expected since inadequate
space remains between limit_pfn and start_pfn after allocating
good_iova.
Signed-off-by: Nate Watterson
---
drivers/iommu/i
performance. As you
suspected would happen, contention has indeed moved to the
io-pgtable lock. I am looking forward to testing with the
lock-free io-pgtable implementation, however I suspect that
there will still be contention issues acquiring the (SMMUv3)
cmdq lock on the unmap path.
Reviewed/
Hi Will,
On 2017-03-10 15:49, Will Deacon wrote:
arm_smmu_install_ste_for_dev cannot fail and always returns 0, however
the fact that it returns int means that callers end up implementing
redundant error handling code which complicates STE tracking and is
never executed.
This patch changes the
Hi Will,
On 2017-03-10 15:49, Will Deacon wrote:
In preparation for allowing the default domain type to be overridden,
this patch adds support for IOMMU_DOMAIN_IDENTITY domains to the
ARM SMMUv3 driver.
An identity domain is created by placing the corresponding stream table
entries into "bypass
On 2017-02-01 13:52, Lorenzo Pieralisi wrote:
I debugged the issue and Nate's fix is correct, the fact that you
can't it hit it with mainline is just a matter of timing because it has
to do with the CTX pointer value (we OR it with the existing value), so
it may work or not depending on how the
On 2017-01-30 09:38, Will Deacon wrote:
On Mon, Jan 30, 2017 at 09:33:50AM -0500, Sinan Kaya wrote:
On 1/30/2017 9:23 AM, Nate Watterson wrote:
> On 2017-01-30 08:59, Sinan Kaya wrote:
>> On 1/30/2017 7:22 AM, Robin Murphy wrote:
>>> On 29/01/17 17:53, Sinan Kaya wrote:
>
On 2017-01-30 08:59, Sinan Kaya wrote:
On 1/30/2017 7:22 AM, Robin Murphy wrote:
On 29/01/17 17:53, Sinan Kaya wrote:
On 1/24/2017 7:37 AM, Lorenzo Pieralisi wrote:
[+hanjun, tomasz, sinan]
It is quite a key patchset, I would be glad if they can test on
their
respective platforms with IORT.
feature and whose first level table can
possibly contain more than a single entry.
Signed-off-by: Nate Watterson
---
drivers/iommu/arm-smmu-v3.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
To prevent corruption of the stage-1 context pointer field when
updating STEs, rebuild the entire containing dword instead of
clearing individual fields.
Signed-off-by: Nate Watterson
---
drivers/iommu/arm-smmu-v3.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a
To ensure that the stage-1 context ptr for an ste points to the
intended context descriptor, this patch adds code to clear away
the stale context ptr value prior to or'ing in the new one.
Signed-off-by: Nate Watterson
---
drivers/iommu/arm-smmu-v3.c | 2 ++
1 file changed, 2 insertions(+)
Currently, all l2 stream tables are being allocated with space for
(1<
---
drivers/iommu/arm-smmu-v3.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 4d6ec44..5dca671 100644
--- a/drivers/iommu/arm-smmu
On 2016-09-09 10:23, Lorenzo Pieralisi wrote:
DT based systems have a generic kernel API to configure IOMMUs
for devices (ie of_iommu_configure()).
On ARM based ACPI systems, the of_iommu_configure() equivalent can
be implemented atop ACPI IORT kernel API, with the corresponding
functions to map
. The granule can be used to check if the
domain was properly initialized because calling init_iova_domain
with a granule of zero would have already triggered a BUG statement
crashing the kernel.
Signed-off-by: Nate Watterson
---
drivers/iommu/iova.c | 4
1 file changed, 4 insertions(+)
diff
egion, this patch adds logic in __alloc_iova to
clip input dma_limit values that are out of bounds.
Signed-off-by: Nate Watterson
---
drivers/iommu/dma-iommu.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index ea
feature and whose first level table can
possibly contain more than a single entry.
Signed-off-by: Nate Watterson
---
drivers/iommu/arm-smmu-v3.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
feature and whose first level table can
possibly contain more than a single entry.
Signed-off-by: Nate Watterson
---
drivers/iommu/arm-smmu-v3.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index 5f6b3bc..742254c 100644
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