On Wed, Jan 22, 2020 at 3:48 AM Sai Prakash Ranjan
wrote:
>
> From: Jordan Crouse
>
> Some client devices want to directly map the IOMMU themselves instead
> of using the DMA domain. Allow those devices to opt in to direct
> mapping by way of a list of compatible strings.
>
> Signed-off-by: Jorda
On Tue, Mar 12, 2019 at 7:21 AM Matthias Brugger wrote:
>
>
>
> On 05/03/2019 20:03, Evan Green wrote:
> > On Wed, Feb 27, 2019 at 6:33 AM Yong Wu wrote:
> >>
> >> On Mon, 2019-02-25 at 15:53 -0800, Evan Green wrote:
> >>>
On Wed, Feb 27, 2019 at 6:33 AM Yong Wu wrote:
>
> On Mon, 2019-02-25 at 15:53 -0800, Evan Green wrote:
> > On Mon, Dec 31, 2018 at 8:52 PM Yong Wu wrote:
> > >
> > > DL_FLAG_AUTOREMOVE_CONSUMER/SUPPLIER means "Remove the link
> > > automatically on
On Wed, Feb 27, 2019 at 6:33 AM Yong Wu wrote:
>
> On Mon, 2019-02-25 at 15:54 -0800, Evan Green wrote:
> > On Mon, Dec 31, 2018 at 8:52 PM Yong Wu wrote:
> > >
> > > Normally, If the smi-larb HW need work, we should enable the smi-common
> > > HW power a
On Wed, Feb 27, 2019 at 6:33 AM Yong Wu wrote:
>
> On Mon, 2019-02-25 at 15:56 -0800, Evan Green wrote:
> > On Mon, Dec 31, 2018 at 8:53 PM Yong Wu wrote:
> > >
> > > MediaTek IOMMU should wait for smi larb which need wait for the
> > > power domain(mtk-sc
On Wed, Feb 27, 2019 at 6:34 AM Yong Wu wrote:
>
> On Mon, 2019-02-25 at 15:54 -0800, Evan Green wrote:
> > On Mon, Dec 31, 2018 at 8:52 PM Yong Wu wrote:
> > >
> > > The iommu consumer should use device_link to connect with the
> > > smi-larb(supplier).
ffany Lin
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
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On Mon, Dec 31, 2018 at 8:53 PM Yong Wu wrote:
>
> After adding device_link between the IOMMU consumer and smi,
> the mediatek,larb is unnecessary now.
>
> CC: Matthias Brugger
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
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seems fine
as-is to me.
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Hu
> CC: Philipp Zabel
> Signed-off-by: Yong Wu
Nice cleanup.
Reviewed-by: Evan Green
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u Tsai
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
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On Mon, Dec 31, 2018 at 8:53 PM Yong Wu wrote:
>
> After adding device_link between the IOMMU consumer and smi,
> the mediatek,larb is unnecessary now.
>
> CC: Matthias Brugger
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
___
On Mon, Dec 31, 2018 at 8:52 PM Yong Wu wrote:
>
> DL_FLAG_AUTOREMOVE_CONSUMER/SUPPLIER means "Remove the link
> automatically on consumer/supplier driver unbind", that means we should
> remove whole the device_link when there is no this driver no matter what
> the ref_count of the link is.
>
> CC
On Mon, Dec 31, 2018 at 8:53 PM Yong Wu wrote:
>
> MediaTek IOMMU should wait for smi larb which need wait for the
> power domain(mtk-scpsys.c) and the multimedia ccf who both are
> module init. Thus, subsys_initcall for MediaTek IOMMU is not helpful.
> Switch to builtin_platform_driver.
>
> Meanw
On Mon, Dec 31, 2018 at 8:52 PM Yong Wu wrote:
>
> MediaTek IOMMU don't have its power-domain. all the consumer connect
> with smi-larb, then connect with smi-common.
>
> M4U
> |
> smi-common
> |
> -
> | |...
> | |
> larb1 lar
On Mon, Dec 31, 2018 at 8:52 PM Yong Wu wrote:
>
> Normally, If the smi-larb HW need work, we should enable the smi-common
> HW power and clock firstly.
> This patch adds device-link between the smi-larb dev and the smi-common
> dev. then If pm_runtime_get_sync(smi-larb-dev), the pm_runtime_get_sy
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
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don't need the property.
>
> And IOMMU also know which larb this consumer connects with from
> iommu id in the "iommus=" property.
>
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
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On Mon, Dec 31, 2018 at 8:52 PM Yong Wu wrote:
>
> The iommu consumer should use device_link to connect with the
> smi-larb(supplier). then the smi-larb should run before the iommu
> consumer. Here we delay the iommu driver until the smi driver is
> ready, then all the iommu consumer always is aft
On Sun, Feb 17, 2019 at 1:09 AM Yong Wu wrote:
>
> In the 4GB mode, the physical address is remapped,
>
> Here is the detailed remap relationship.
> CPU PA ->HW PA
> 0x4000_ 0x1_4000_ (Add bit32)
> 0x8000_ 0x1_8000_ ...
> 0xc000_ 0x1_c000_
t;struct mtk_smi_iommu" could also
> be deleted.
>
> CC: Matthias Brugger
> Signed-off-by: Yong Wu
Thanks for the cleanup.
Reviewed-by: Evan Green
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On Sun, Feb 17, 2019 at 1:09 AM Yong Wu wrote:
>
> This patch only rename the variable name from enable_4GB to
> dram_is_4gb for readable.
>
> Signed-off-by: Yong Wu
Nice, this is clearer.
Reviewed-by: Evan Green
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>
> And, the base of smi-common is completely different with smi_ao_base
> of gen1, thus I add new variable for that.
>
> CC: Matthias Brugger
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
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> ---
> Comparing the previous version, I add MTK_4GB quirk always since mtk_iommu
> has already controlled the PA itself. Helped from Evan.
Thanks for all the explanation on this one. I think I understand it
now, and it looks good to me.
Reviewed-by
_data, it's also a preparing
> patch for mt8183.
>
> Signed-off-by: Yong Wu
> Reviewed-by: Nicolas Boichat
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83 need reset_axi like mt8173.
> 7) the larb-id in smi-common is remapped. M4U should add its larbid_remap.
>
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
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atch delete the complex MACRO and use a common if-else
> instead.
>
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
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On Sun, Feb 17, 2019 at 1:08 AM Yong Wu wrote:
>
> Both mt8173 and mt8183 don't have this vld_pa_rng(valid physical address
> range) register while mt2712 have. Move it into the plat_data.
>
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
_
uot;gals" clock for smi-larb.
>
> From the diagram above, IPU0/IPU1(Image Processor Unit) and CCU(Camera
> Control Unit) is connected with smi-common directly, we can take them
> as "larb2", "larb3" and "larb7", and their register spaces are
> different with the normal larb.
>
> Signed-off-by: Yong Wu
Reviewed-by: Evan Green
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On Fri, Feb 1, 2019 at 1:42 AM Yong Wu wrote:
>
> On Thu, 2019-01-31 at 11:23 -0800, Evan Green wrote:
> > On Wed, Jan 30, 2019 at 10:59 PM Yong Wu wrote:
> > >
> > > On Wed, 2019-01-30 at 10:28 -0800, Evan Green wrote:
> > > > On M
On Wed, Jan 30, 2019 at 10:59 PM Yong Wu wrote:
>
> On Wed, 2019-01-30 at 10:28 -0800, Evan Green wrote:
> > On Mon, Dec 31, 2018 at 7:57 PM Yong Wu wrote:
> > >
> > > MediaTek extend the arm v7s descriptor to support the dram over 4GB.
> > >
> > >
On Wed, Jan 30, 2019 at 7:22 PM Yong Wu wrote:
>
> On Wed, 2019-01-30 at 11:11 -0800, Evan Green wrote:
> > On Mon, Dec 31, 2018 at 7:59 PM Yong Wu wrote:
> > >
> > > The "mediatek,larb-id" has already been parsed in MTK IOMMU driver.
> > > I
On Wed, Jan 30, 2019 at 7:20 PM Yong Wu wrote:
>
> On Wed, 2019-01-30 at 10:30 -0800, Evan Green wrote:
> > On Mon, Dec 31, 2018 at 7:58 PM Yong Wu wrote:
> > >
> > > Both mt8173 and mt8183 don't have this vld_pa_rng(valid physical address
> > > ran
On Mon, Dec 31, 2018 at 8:00 PM Yong Wu wrote:
>
> Switch to SPDX license identifier for MediaTek iommu/smi and their
> header files.
>
> Signed-off-by: Yong Wu
> Reviewed-by: Rob Herring
Reviewed-by: Evan Green
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On Mon, Dec 31, 2018 at 7:59 PM Yong Wu wrote:
>
> The "mediatek,larb-id" has already been parsed in MTK IOMMU driver.
> It's no need to parse it again in SMI driver. Only clean some codes.
> This patch is fit for all the current mt2701, mt2712, mt7623, mt8173
> and mt8183.
>
> After this patch, t
d-off-by: Yong Wu
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unds unpleasant. Hopefully the reboot flow still continues properly
even in that case, since this shutdown code may not run during some
rougher resets.
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On Mon, Dec 31, 2018 at 7:59 PM Yong Wu wrote:
>
> There are 2 mmu cells in a M4U HW. we could adjust some larbs entering
> mmu0 or mmu1 to balance the bandwidth via the smi-common register
> SMI_BUS_SEL(0x220)(Each larb occupy 2 bits).
>
> In mt8183, For better performance, we switch larb1/2/5/7
the order is still:
1) mtk_smi_clk_enable(common)
2) mtk_smi_clk_enable(larb)
3) larb_gen->config_port()
And teardown still happens in the opposite order, except for
config_port, which they seem not to do in suspend.
So, looks good to me.
Reviewed-by: Evan Gre
ine F_INT_TLB_MISS_FAULT BIT(4)
> -#define F_INT_MISS_TRANSACTION_FIFO_FAULT BIT(5)
> -#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT BIT(6)
> +#define REG_MMU_INT_MAIN_CONTROL 0x124 /* mmu0 | mmu1 */
The comment being on that line is kind of
On Mon, Dec 31, 2018 at 7:58 PM Yong Wu wrote:
>
> In mt8173 and mt8183, 0x48 is REG_MMU_STANDARD_AXI_MODE while
> it is extended to REG_MMU_CTRL which contains _STANDARD_AXI_MODE in
> the other SoCs. I move this property to plat_data since both mt8173
> and mt8183 use this property.
>
> It is a p
On Mon, Dec 31, 2018 at 7:58 PM Yong Wu wrote:
>
> Both mt8173 and mt8183 don't have this vld_pa_rng(valid physical address
> range) register while mt2712 have. Move it into the plat_data.
>
> Signed-off-by: Yong Wu
> ---
> drivers/iommu/mtk_iommu.c | 3 ++-
> drivers/iommu/mtk_iommu.h | 1 +
>
rue,
> + .larbid_remap = {0, 1, 2, 3, 4, 5}, /* Linear mapping. */
I briefly considered bikeshedding about how to define these arrays in
a way that might save memory for linear-map devices, but then decided
this is fine.
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On Mon, Dec 31, 2018 at 7:59 PM Yong Wu wrote:
>
> The M4U IP blocks in mt8183 is MediaTek's generation2 M4U which use
> the ARM Short-descriptor like mt8173, and most of the HW registers
> are the same.
>
> Here list main differences between mt8183 and mt8173/mt2712:
> 1) mt8183 has only one M4U
On Mon, Dec 31, 2018 at 7:57 PM Yong Wu wrote:
>
> MediaTek extend the arm v7s descriptor to support the dram over 4GB.
>
> In the mt2712 and mt8173, it's called "4GB mode", the physical address
> is from 0x4000_ to 0x1_3fff_, but from EMI point of view, it
> is remapped to high address fr
On Mon, Dec 31, 2018 at 7:57 PM Yong Wu wrote:
>
> In some SoCs, M4U doesn't have its "bclk", it will use the EMI
> clock instead which has always been enabled when entering kernel.
>
> This also is a preparing patch for mt8183.
>
> Signed-off-b
mtk_smi_common_plat" before it is referred.
>
> This is a preparing patch for mt8183.
>
> Signed-off-by: Yong Wu
> Reviewed-by: Matthias Brugger
Reviewed-by: Evan Green
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On Mon, Dec 31, 2018 at 7:58 PM Yong Wu wrote:
>
> The protect memory setting is a little different in the different SoCs.
> In the register REG_MMU_CTRL_REG(0x110), the TF_PROT(translation fault
> protect) shift bit is normally 4 while it shift 5 bits only in the
> mt8173. This patch delete the c
; clock for smi-larb.
>
> This patch adds gals clock supporting in the SMI. Note that some larbs
> may still don't have the "gals" clock like larb1 and larb4 above.
>
> This is also a preparing patch for mt8183 which has GALS.
>
On Mon, Dec 31, 2018 at 7:57 PM Yong Wu wrote:
>
> Add two helper functions: paddr_to_iopte and iopte_to_paddr.
>
> Signed-off-by: Yong Wu
> Reviewed-by: Robin Murphy
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On Mon, Dec 31, 2018 at 7:56 PM Yong Wu wrote:
>
> Use a struct as the platform special data instead of the enumeration.
> This is a prepare patch for adding mt8183 iommu support.
>
> Signed-off-by: Yong Wu
> Reviewed-by: Matthias Brugger
Revie
.
>
> This is also a preparing patch for adding mt8183 SMI support.
>
> Signed-off-by: Yong Wu
> Reviewed-by: Matthias Brugger
Reviewed-by: Evan Green
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On Mon, Dec 31, 2018 at 7:56 PM Yong Wu wrote:
>
> This patch adds decriptions for mt8183 IOMMU and SMI.
>
> mt8183 has only one M4U like mt8173 and is also MTK IOMMU gen2 which
> uses ARM Short-Descriptor translation table format.
>
> The mt8183 M4U-SMI HW diagram is as below:
>
>
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