> -Original Message-
> From: Robin Murphy [mailto:robin.mur...@arm.com]
> Sent: 28 January 2016 22:59
> To: Anup Patel; Catalin Marinas; Joerg Roedel; Will Deacon; Sricharan R; Linux
> IOMMU; Linux ARM Kernel
> Cc: Rob Herring; Pawel Moll; Mark Rutland; Ian Campbell; Kumar Gala; Device
>
> -Original Message-
> From: Robin Murphy [mailto:robin.mur...@arm.com]
> Sent: 28 January 2016 22:41
> To: Anup Patel; Catalin Marinas; Joerg Roedel; Will Deacon; Robin Murphy;
> Sricharan R; Linux IOMMU; Linux ARM Kernel
> Cc: Mark Rutland; Device Tree; Scott Branden; Pawel Moll; Ian Ca
On 01/29/16 at 10:55am, Wan Zongshun wrote:
>
>
> Original Message
> >On 01/27/16 at 06:18pm, Wan Zongshun wrote:
> >>
> >>
> >> Original Message
> >>>In amd-vi spec the name of bit0 in DTE is V. But in code it's defined
> >>>as IOMMU_PTE_P. Here change it to IO
Original Message
On 01/27/16 at 07:03pm, Wan Zongshun wrote:
Original Message
alias = amd_iommu_alias_table[devid];
table = irq_lookup_table[alias];
@@ -3688,7 +3688,7 @@ static struct irq_remap_table *get_irq_table(u16 devid,
bool ioapi
Original Message
On 01/27/16 at 06:18pm, Wan Zongshun wrote:
Original Message
In amd-vi spec the name of bit0 in DTE is V. But in code it's defined
as IOMMU_PTE_P. Here change it to IOMMU_PTE_V to make it be consistent
with spec.
Hi, Baoquan
This shoul
On Tue, 2016-01-26 at 13:12 +, Eric Auger wrote:
> This series addresses KVM PCIe passthrough with MSI enabled on ARM/ARM64.
> It pursues the efforts done on [1], [2], [3]. It also aims at covering the
> same need on some PowerPC platforms.
>
> On x86 all accesses to the 1MB PA region [FEE0_00
On Thu, Jan 28, 2016 at 05:28:30PM +, Robin Murphy wrote:
> On 27/01/16 05:21, Anup Patel wrote:
> >To allow use of large memory (> 4Gb) with 32bit devices we need to use
> >some kind of iommu for such 32bit devices.
> >
> >This patch extends SMMUv1/SMMUv2 driver to support DMA domains which
>
On 27/01/16 05:21, Anup Patel wrote:
To allow use of large memory (> 4Gb) with 32bit devices we need to use
some kind of iommu for such 32bit devices.
This patch extends SMMUv1/SMMUv2 driver to support DMA domains which
in-turn will allows us to use iommu based DMA mappings for 32bit devices.
S
On 27/01/16 05:21, Anup Patel wrote:
We are saving pointer to iommu DT node in of_iommu_set_ops()
hence we should increment DT node ref count.
Oh man, shame on whoever wrote that code! :P
Reviewed-by: Robin Murphy
Signed-off-by: Anup Patel
Reviewed-by: Ray Jui
Reviewed-by: Scott Branden
On 27/01/16 05:21, Anup Patel wrote:
Currently, the SMMU driver by default provides unprivilege read-write
permission in page table entries of stage1 page table. For SMMUv2 with
aarch64 long descriptor format, a privilege instruction fetch will
generate context fault. To allow privilege instructi
On 27/01/16 01:16, Yong Wu wrote:
On Tue, 2016-01-26 at 17:13 +, Robin Murphy wrote:
Add a nearly-complete ARMv7 short descriptor implementation, omitting
only a few legacy and CPU-centric aspects which shouldn't be necessary
for IOMMU API use anyway.
Signed-off-by: Yong Wu
Signed-off-by:
On 28/01/16 04:54, Vijay Kumar wrote:
Hii all,
I am new to this mailing list and i need some help.I am trying
to add exynos iommu support for my board with exynos5250-soc for fimd.I am
getting this error at exynos_sysmmu_irq.I am pretty confused with it and
didn't know what to do.I st
On Tue, Jan 26, 2016 at 12:12 PM, Yong Wu wrote:
> This patch add the iommu/larbs nodes for mt8173
>
> Signed-off-by: Yong Wu
Reviewed-by: Daniel Kurtz
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On Thu, 2015-11-19 at 18:22 +0200, Andy Shevchenko wrote:
> There is already helper functions to do 64-bit I/O on 32-bit machines
> or buses,
> thus we don't need to reinvent the wheel.
>
Any comment on this?
> Signed-off-by: Andy Shevchenko
> ---
> Cahngelog v2:
> - rebase on top of recent lin
On Tue, Jan 26, 2016 at 12:12 PM, Yong Wu wrote:
> This patch add SMI(Smart Multimedia Interface) driver. This driver
> is responsible to enable/disable iommu and control the power domain
> and clocks of each local arbiter.
>
> Signed-off-by: Yong Wu
> Tested-by: Philipp Zabel
Reviewed-by: Dani
On 01/27/16 at 06:22pm, Wan Zongshun wrote:
>
>
> Original Message
> >In amd-vi spec bit[60:58] are only used to store the bit[14:12] of GCR3.
> >No any other useage is found in several versions of amd-vi spec. So remove
> >them in this patch.
>
> Also,this patch also made me c
On 01/27/16 at 07:03pm, Wan Zongshun wrote:
>
>
> Original Message
> >
> > alias = amd_iommu_alias_table[devid];
> > table = irq_lookup_table[alias];
> >@@ -3688,7 +3688,7 @@ static struct irq_remap_table *get_irq_table(u16
> >devid, bool ioapic)
> > /* Nothing ther
On 01/27/16 at 06:18pm, Wan Zongshun wrote:
>
>
> Original Message
> >In amd-vi spec the name of bit0 in DTE is V. But in code it's defined
> >as IOMMU_PTE_P. Here change it to IOMMU_PTE_V to make it be consistent
> >with spec.
>
> Hi, Baoquan
>
> This should be PR bit which m
On 01/27/16 at 07:23pm, Wan Zongshun wrote:
>
>
> Original Message
> >If irq table exists in old kernel create a new one and copy the content
> >of old irq table to the newly created.
> >
> >Signed-off-by: Baoquan He
> >---
> >diff --git a/drivers/iommu/amd_iommu_init.c b/drive
Thanks a lot for your review, Zongshun.
On 01/27/16 at 06:25pm, Wan Zongshun wrote:
>
>
> Original Message
> >These macro definitions are also needed by irq table copy function
> >later, so move them to amd_iommu_types.h.
>
> Typo for your subject (defitions?).
Yeah, this is
Hi Pavel,
On 01/28/2016 08:13 AM, Pavel Fedin wrote:
> Hello!
>
>> x86 isn't problem-free in this space. An x86 VM is going to know that
>> the 0xfee0 address range is special, it won't be backed by RAM and
>> won't be a DMA target, thus we'll never attempt to map it for an iova
>> address.
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