>-Original Message-
>From: Jiri Pirko
>Sent: Thursday, August 8, 2024 1:54 PM
>
>Thu, Aug 08, 2024 at 01:20:12PM CEST, arkadiusz.kubalew...@intel.com wrote:
>>Implement and document new pin attributes for providing Embedded SYNC
>>capabilities to the DPLL subsystem users through a netlink
>From: Jakub Kicinski
>Sent: Saturday, August 10, 2024 6:16 AM
>
>On Thu, 8 Aug 2024 13:20:12 +0200 Arkadiusz Kubalewski wrote:
>> +Device may provide ability to use Embedded SYNC feature. It allows
>> +to embed additional SYNC signal into the base frequency of a pin - a one
>> +special pulse of
>From: Jiri Pirko
>Sent: Thursday, August 22, 2024 12:22 PM
>
>Wed, Aug 21, 2024 at 11:32:17PM CEST, arkadiusz.kubalew...@intel.com wrote:
>>Implement and document new pin attributes for providing Embedded SYNC
>>capabilities to the DPLL subsystem users through a netlink pin-get
>>do/dump messages
>From: Jiri Pirko
>Sent: Thursday, August 22, 2024 12:29 PM
>
>Wed, Aug 21, 2024 at 11:32:18PM CEST, arkadiusz.kubalew...@intel.com wrote:
>>Allow the user to get and set configuration of Embedded SYNC feature
>>on the ice driver dpll pins.
>>
>>Reviewed-by: Aleksandr Loktionov
>>Signed-off-by: A
>From: Intel-wired-lan On Behalf Of
>Paul Menzel
>Sent: Thursday, December 14, 2023 10:31 AM
>
>Dear Arkadiusz,
>
>
>Thank you for your patch.
>
>Am 14.12.23 um 09:50 schrieb Arkadiusz Kubalewski:
>> Stop dividing the phase_offset value received from firmware, this is
>> fault introduced with the
>From: Nguyen, Anthony L
>Sent: Friday, February 9, 2024 7:52 PM
>
>On 2/7/2024 8:19 AM, Arkadiusz Kubalewski wrote:
>
>...
>
>> +static bool ice_dpll_is_reset(struct ice_pf *pf, struct netlink_ext_ack
>*extack)
>> +{
>> +if (ice_is_reset_in_progress(pf->state)) {
>> +NL_SET_ERR_MS
>From: Paul Menzel
>Sent: Wednesday, September 11, 2024 8:22 AM
>
>Dear Arkadiusz,
>
>
>Thank you for your patch. It’d be great if you made the summary more
>explicit. For example:
>
>ice: Disallow DPLL_PIN_STATE_SELECTABLE for dpll output pins
>
>Am 11.09.24 um 01:28 schrieb Arkadiusz Kubalewski:
>From: Paul Menzel
>Sent: Wednesday, September 11, 2024 8:41 AM
>
>Dear Arkadiusz,
>
>
>Thank you for your patch. It’d be great if you used a more specific
>summary. Maybe:
>
>ice: Allow full frequency range of 1 Hz–25 MHz for dpll pins
>
>Some more nits below:
>
>Am 11.09.24 um 01:29 schrieb Arka
>From: Vadim Fedorenko
>Sent: Wednesday, September 27, 2023 8:09 PM
>
>On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
>> Add callback op (get) for pin-dpll phase-offset measurment.
>> Add callback ops (get/set) for pin signal phase adjustment.
>> Add min and max phase adjustment values to pin pr
>From: Jiri Pirko
>Sent: Monday, October 2, 2023 5:04 PM
>
>Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalew...@intel.com wrote:
>>>From: Vadim Fedorenko
>>>Sent: Wednesday, September 27, 2023 8:09 PM
>>>
>>>On 27/09/2023 10:24, Arkadiusz Kubalewski wrote:
Add callback op (get) for pi
>From: Intel-wired-lan On Behalf Of
>Vadim Fedorenko
>Sent: Monday, October 2, 2023 5:09 PM
>
>On 02/10/2023 16:04, Jiri Pirko wrote:
>> Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalew...@intel.com
>> wrote:
From: Vadim Fedorenko
Sent: Wednesday, September 27, 2023 8:09 PM
>From: Jiri Pirko
>Sent: Tuesday, October 3, 2023 8:32 AM
>
>Tue, Oct 03, 2023 at 01:03:00AM CEST, arkadiusz.kubalew...@intel.com wrote:
>>>From: Jiri Pirko
>>>Sent: Monday, October 2, 2023 5:04 PM
>>>
>>>Mon, Oct 02, 2023 at 04:32:30PM CEST, arkadiusz.kubalew...@intel.com
>>>wrote:
>From: Va
>From: Jiri Pirko
>Sent: Tuesday, October 3, 2023 8:27 AM
>To: Kubalewski, Arkadiusz
>
>Tue, Oct 03, 2023 at 01:10:39AM CEST, arkadiusz.kubalew...@intel.com wrote:
>>>From: Intel-wired-lan On Behalf Of
>>>Vadim Fedorenko
>>>Sent: Monday, October 2, 202
>From: Jiri Pirko
>Sent: Tuesday, October 3, 2023 7:20 PM
>To: Kubalewski, Arkadiusz
>
>Tue, Oct 03, 2023 at 04:29:43PM CEST, arkadiusz.kubalew...@intel.com wrote:
>>>From: Jiri Pirko
>>>Sent: Tuesday, October 3, 2023 8:32 AM
>>>
>>>Tue,
>From: Jiri Pirko
>Sent: Tuesday, October 3, 2023 7:19 PM
>
>Tue, Oct 03, 2023 at 04:29:13PM CEST, arkadiusz.kubalew...@intel.com wrote:
>>>From: Jiri Pirko
>>>Sent: Tuesday, October 3, 2023 8:27 AM
>>>To: Kubalewski, Arkadiusz
>>>
>>&g
>From: Jiri Pirko
>Sent: Monday, October 2, 2023 4:53 PM
>
>Wed, Sep 27, 2023 at 11:24:33AM CEST, arkadiusz.kubalew...@intel.com wrote:
>>Add new pin's attributes to dpll netlink spec:
>>- phase-offset - measured difference between phase of signals on pin
>> and dpll
>>- phase-adjust - adjustable
>From: Jiri Pirko
>Sent: Wednesday, October 4, 2023 12:42 PM
>
>Wed, Oct 04, 2023 at 11:05:44AM CEST, arkadiusz.kubalew...@intel.com wrote:
>>Add attributes for providing the user with:
>>- measurement of signals phase offset between pin and dpll
>>- ability to adjust the phase of pin signal
>>
>>
>From: Jiri Pirko
>Sent: Friday, October 6, 2023 2:38 PM
>
>Fri, Oct 06, 2023 at 01:40:59PM CEST, arkadiusz.kubalew...@intel.com wrote:
>>Add callback ops for pin-dpll phase measurment.
>>Add callback for pin signal phase adjustment.
>>Add min and max phase adjustment values to pin proprties.
>>In
>From: Jiri Pirko
>Sent: Monday, October 2, 2023 5:01 PM
>
>Wed, Sep 27, 2023 at 11:24:32AM CEST, arkadiusz.kubalew...@intel.com wrote:
>>Add dpll documentation on new pin's attributes:
>>- phase-offset - measured difference between phase of signals on pin
>> and dpll
>>- phase-adjust - adjustabl
>From: Jiri Pirko
>Sent: Friday, October 6, 2023 2:30 PM
>
>Fri, Oct 06, 2023 at 01:40:58PM CEST, arkadiusz.kubalew...@intel.com wrote:
>>Add attributes for providing the user with:
>>- measurement of signals phase offset between pin and dpll
>>- ability to adjust the phase of pin signal
>>
>>Sign
>From: Jakub Kicinski
>Sent: Wednesday, October 11, 2023 4:35 AM
>
>On Tue, 10 Oct 2023 00:26:11 +0200 Arkadiusz Kubalewski wrote:
>> Improve monitoring and control over dpll devices.
>> Allow user to receive measurement of phase difference between signals
>> on pin and dpll (phase-offset).
>> All
>From: Michal Schmidt
>Sent: Wednesday, October 9, 2024 12:21 PM
>
>On Thu, Oct 3, 2024 at 11:26 AM Arkadiusz Kubalewski
> wrote:
>>
>> The E810 Lan On Motherboard (LOM) design is vendor specific. Intel
>> provides the reference design, but it is up to vendor on the final
>> product design. For so
>From: Richard Cochran
>Sent: Monday, October 7, 2024 6:07 PM
>
>On Thu, Oct 03, 2024 at 11:37:52PM +0200, Arkadiusz Kubalewski wrote:
>> HW support of PTP/timesync solutions in network PHY chips can be
>> achieved with two different approaches, the timestamp maybe latched
>> either in the beginni
>From: Richard Cochran
>Sent: Wednesday, October 23, 2024 4:13 AM
>
>On Mon, Oct 21, 2024 at 04:19:54PM +0200, Arkadiusz Kubalewski wrote:
>> Currently HW support of PTP/timesync solutions in network PHY chips
>> can be implemented with two different approaches, the timestamp maybe
>> latched eith
>From: Paul Menzel
>Sent: Monday, October 21, 2024 5:34 PM
>
>Dear Arkadiusz,
>
>
>Thank you for the patch.
Thank you for the review!
>
>Am 21.10.24 um 16:19 schrieb Arkadiusz Kubalewski:
>> Allow user to control the latch point of ptp HW timestamps in E825
>> devices.
>
>Please give an example
>From: Paul Menzel
>Sent: Monday, October 21, 2024 5:21 PM
>
>Dear Arkadiusz,
>
>
>Thank you for your patch.
Thank you for the review!
>
>Am 21.10.24 um 16:19 schrieb Arkadiusz Kubalewski:
>> Currently HW support of PTP/timesync solutions in network PHY chips can
>> be
>> implemented with two di
>From: Keller, Jacob E
>Sent: Tuesday, October 22, 2024 12:31 AM
>
>
>On 10/21/2024 7:19 AM, Arkadiusz Kubalewski wrote:
>> Currently HW support of PTP/timesync solutions in network PHY chips can
>> be
>> implemented with two different approaches, the timestamp maybe latched
>> either at the begin
>From: Simon Horman
>Sent: Tuesday, October 22, 2024 3:40 PM
>
>On Mon, Oct 21, 2024 at 04:19:55PM +0200, Arkadiusz Kubalewski wrote:
>> Allow user to control the latch point of ptp HW timestamps in E825
>> devices.
>>
>> Reviewed-by: Aleksandr Loktionov
>> Signed-off-by: Arkadiusz Kubalewski
>>
>From: Vadim Fedorenko
>Sent: Tuesday, October 29, 2024 12:30 PM
>
>On 28/10/2024 20:47, Arkadiusz Kubalewski wrote:
>> HW support of PTP/timesync solutions in network PHY chips can be
>> achieved with two different approaches, the timestamp maybe latched
>> either in the beginning or after the St
>From: Intel-wired-lan On Behalf Of
>Vadim Fedorenko
>Sent: Tuesday, October 29, 2024 5:17 PM
>
>On 29/10/2024 15:56, Kubalewski, Arkadiusz wrote:
>>> From: Vadim Fedorenko
>>> Sent: Tuesday, October 29, 2024 12:30 PM
>>>
>>> On 28/10/2024 20
>From: Kitszel, Przemyslaw
>Sent: Tuesday, October 29, 2024 9:25 AM
>Subject: Re: [PATCH net-next v2 1/2] ptp: add control over HW timestamp
>latch point
>
>On 10/28/24 21:47, Arkadiusz Kubalewski wrote:
>> Currently HW support of PTP/timesync solutions in network PHY chips
>> can be implemented w
>From: Kitszel, Przemyslaw
>Sent: Tuesday, October 29, 2024 9:22 AM
>
>On 10/28/24 21:47, Arkadiusz Kubalewski wrote:
>> Allow user to control the latch point of ptp HW timestamps in E825
>
>sometimes you write ptp, sometimes PTP, I would make it consistent
>(but subject line is fine as is)
>
>> d
>From: Nguyen, Anthony L
>Sent: Thursday, October 3, 2024 12:18 AM
>
>On 9/30/2024 11:40 AM, Arkadiusz Kubalewski wrote:
>> The E810 Lan On Motherboard (LOM) design is vendor specific. Intel
>> provides the reference design, but it is up to vendor on the final
>> product design. For some cases, li
>From: Intel-wired-lan On Behalf Of
>Andrew Lunn
>Sent: Wednesday, November 6, 2024 6:45 PM
>
>On Wed, Nov 06, 2024 at 02:07:55AM +0100, Arkadiusz Kubalewski wrote:
>> Currently HW support of ptp/timesync solutions in network PHY chips can
>>be
>> implemented with two different approaches, the tim
>From: Jakub Kicinski
>Sent: Wednesday, November 6, 2024 3:05 AM
>
>On Wed, 6 Nov 2024 02:07:55 +0100 Arkadiusz Kubalewski wrote:
>> +What: /sys/class/ptp/ptp/ts_point
>> +Date: October 2024
>> +Contact:Arkadiusz Kubalewski
>> +Description:
>> +This fi
>From: Intel-wired-lan On Behalf Of
>Simon Horman
>Sent: Tuesday, December 3, 2024 11:05 AM
>
>On Wed, Nov 20, 2024 at 08:51:12AM +0100, Arkadiusz Kubalewski wrote:
>> Mask admin command returned max phase adjust value for both input and
>> output pins. Only 31 bits are relevant, last released dat
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