On Tue, Apr 08, 2025 at 10:19:39AM +0800, luoxuanqiang wrote:
>
> 在 2025/4/7 22:02, Simon Horman 写道:
> > On Tue, Mar 25, 2025 at 10:01:49AM +0800, Xuanqiang Luo wrote:
> > > From: Xuanqiang Luo
> > >
> > > As mentioned in the commit baeb705fd6a7 ("ice: always check VF VSI
> > > pointer values"),
From: Sudheer Mogilappagari
Add opcodes and corresponding message structure to add and delete
flow steering rules. Flow steering enables configuration
of rules to take an action or subset of actions based on a match
criteria. Actions could be redirect to queue, redirect to queue
group, drop packe
This patch series introduces support for Precision Time Protocol (PTP) to
Intel(R) Infrastructure Data Path Function (IDPF) driver. PTP feature is
supported when the PTP capability is negotiated with the Control
Plane (CP). IDPF creates a PTP clock and sets a set of supported
functions.
During the
PTP capabilities are negotiated using virtchnl commands. There are two
available modes of the PTP support: direct and mailbox. When the direct
access to PTP resources is negotiated, virtchnl messages returns a set
of registers that allow read/write directly. When the mailbox access to
PTP resources
Add cross timestamp support through virtchnl mailbox messages and directly,
through PCIe BAR registers. Cross timestamping assumes that both system
time and device clock time values are cached simultaneously, what is
triggered by HW. Feature is enabled for both ARM and x86 archs.
Signed-off-by: Mi
Move virtchnl structures to the header file to expose them for the PTP
virtchnl file.
Reviewed-by: Alexander Lobakin
Reviewed-by: Willem de Bruijn
Signed-off-by: Milena Olech
Tested-by: Mina Almasry
Tested-by: Samuel Salin
---
v1 -> v2: fix commit message title
.../net/ethernet/intel/idpf/i
PTP capabilities are negotiated using virtchnl command. Add get
capabilities function, direct access to read the PTP clock.
Set initial PTP capabilities exposed to the stack.
Tested-by: Willem de Bruijn
Signed-off-by: Milena Olech
Tested-by: Mina Almasry
Tested-by: Samuel Salin
---
v9 -> v10:
Tx timestamp capabilities are negotiated for the uplink Vport.
Driver receives information about the number of available Tx timestamp
latches, the size of Tx timestamp value and the set of indexes used
for Tx timestamping.
Add function to get the Tx timestamp capabilities and parse the uplink
vpor
Add Rx timestamp function when the Rx timestamp value is read directly
from the Rx descriptor. In order to extend the Rx timestamp value to 64
bit in hot path, the PHC time is cached in the receive groups.
Add supported Rx timestamp modes.
Signed-off-by: Milena Olech
Tested-by: YiFei Zhu
Tested-
From: Victor Raj
Move intel specific header files into new folder
include/linux/intel.
Suggested-by: Alexander Lobakin
Reviewed-by: Sridhar Samudrala
Signed-off-by: Victor Raj
Signed-off-by: Larysa Zaremba
---
drivers/infiniband/hw/irdma/i40iw_if.c| 2 +-
drivers/inf
At the end of the probe, trigger hard reset, initialize and schedule the
after-reset task. If the reset is complete in a pre-determined time,
initialize the default mailbox, through which other resources will be
negotiated.
Co-developed-by: Amritha Nambiar
Signed-off-by: Amritha Nambiar
Reviewed
When the access to read PTP clock is specified as mailbox, the driver
needs to send virtchnl message to perform PTP actions. Message is sent
using idpf_mbq_opc_send_msg_to_peer_drv mailbox opcode, with the parameters
received during PTP capabilities negotiation.
Add functions to recognize PTP mess
PTP clock configuration operations - set time, adjust time and adjust
frequency are required to control the clock and maintain synchronization
process.
Extend get PTP capabilities function to request for the clock adjustments
and add functions to enable these actions using dedicated virtchnl
messa
From: Phani R Burra
Add memory related support functions for drivers to access MMIO space and
allocate/free dma buffers.
Reviewed-by: Maciej Fijalkowski
Signed-off-by: Phani R Burra
Co-developed-by: Victor Raj
Signed-off-by: Victor Raj
Co-developed-by: Sridhar Samudrala
Signed-off-by: Sridh
From: Maciej Fijalkowski
Date: Tue, 11 Mar 2025 17:08:22 +0100
> On Wed, Mar 05, 2025 at 05:21:31PM +0100, Alexander Lobakin wrote:
>> Use libeth XDP infra to implement .ndo_xdp_xmit() in idpf.
>> The Tx callbacks are reused from XDP_TX code. XDP redirect target
>> feature is set/cleared dependin
As the mailbox is setup, initialize the core. This makes use of the
send and receive mailbox message framework for virtchnl communication
between the driver and device Control Plane (CP).
To start with, driver confirms the virtchnl version with the CP. Once
that is done, it requests and gets the r
From: Maciej Fijalkowski
Date: Tue, 11 Mar 2025 15:05:38 +0100
> On Wed, Mar 05, 2025 at 05:21:19PM +0100, Alexander Lobakin wrote:
>> "Couple" is a bit humbly... Add the following functionality to libeth:
[...]
>> +struct libeth_rq_napi_stats {
>> +union {
>> +struct {
>> +
On Tue, Apr 08, 2025 at 02:22:43PM +, Marek Pazdan wrote:
> On Mon, 7 Apr 2025 22:30:54 +0200 Andrew Lunn wrote:
>
> > As the name get/set-phy-tunable suggests, these are for PHY
> > properties, like downshift, fast link down, energy detected power
> > down.
> >
> > What PHY are you using her
On Mon, 7 Apr 2025 22:30:54 +0200 Andrew Lunn wrote:
> As the name get/set-phy-tunable suggests, these are for PHY
> properties, like downshift, fast link down, energy detected power
> down.
>
> What PHY are you using here?
Thanks for review.
It's PHY E810-C in this case. According to spreadshee
On Tue, Apr 08, 2025 at 03:32:30PM +, Marek Pazdan wrote:
> On Mon, 7 Apr 2025 22:39:17 +0200 Andrew Lunn wrote:
> > How do you tell the kernel to stop managing the SFP? If you hit the
> > module with a reset from user space, the kernel is going to get
> > confused. And how are you talking to t
Previously control of the dpll SMA/U.FL pins was partially done through
ptp API, decouple pins control from both interfaces (dpll and ptp).
Allow the SMA/U.FL pins control over a dpll subsystem, and leave ptp
related SDP pins control over a ptp subsystem.
Arkadiusz Kubalewski (1):
ice: redesign
Add functions to request Tx timestamp for the PTP packets, read the Tx
timestamp when the completion tag for that packet is being received,
extend the Tx timestamp value and set the supported timestamping modes.
Tx timestamp is requested for the PTP packets by setting a TSYN bit and
index value in
On Mon Apr 07 2025, Simon Horman wrote:
> On Fri, Mar 21, 2025 at 02:52:38PM +0100, Kurt Kanzenbach wrote:
>> Limit netdev_tc calls to MQPRIO. Currently these calls are made in
>> igc_tsn_enable_offload() and igc_tsn_disable_offload() which are used by
>> TAPRIO and ETF as well. However, these are
In the SRIOV LAG Active-Active, the function ice_lag_cfg_pf_fltr's
content is moved to an earlier location in the source file. Along
with this change, the function is renamed, and the flow is changed.
To reduce the delta in the larger patch, move the original function
to its new location so that
This series will be touching on the LAG code in the ice driver,
to prevent moving or propagating casting on void pointers, clean
them up first.
This also allows for moving the variable initialization into the
variable declaration.
Reviewed-by: Aleksandr Loktionov
Reviewed-by: Przemek Kitszel
Si
From: Alexander Lobakin
Date: Tue, 8 Apr 2025 15:22:48 +0200
> From: Maciej Fijalkowski
> Date: Tue, 11 Mar 2025 15:05:38 +0100
>
>> On Wed, Mar 05, 2025 at 05:21:19PM +0100, Alexander Lobakin wrote:
>>> "Couple" is a bit humbly... Add the following functionality to libeth:
[...]
>>> +/**
>>>
Use Device Serial Number instead of PCI bus/device/function for
index of struct ice_adapter.
Functions on the same physical device should point to the very same
ice_adapter instance.
This is not only simplification, but also fixes things up when PF
is passed to VM (and thus has a random BDF).
Sug
On 4/8/2025 3:31 AM, Milena Olech wrote:
> +static void idpf_ptp_release_vport_tstamp(struct idpf_vport *vport)
> +{
> + struct idpf_ptp_tx_tstamp *ptp_tx_tstamp, *tmp;
> + struct list_head *head;
> +
> + /* Remove list with free latches */
> + spin_lock(&vport->tx_tstamp_caps->l
On 4/8/2025 3:31 AM, Milena Olech wrote:
> +/**
> + * idpf_ptp_tstamp_extend_32b_to_64b - Convert a 32b nanoseconds Tx or Rx
> + * timestamp value to 64b.
> + * @cached_phc_time: recently cached copy of PHC time
> + * @in_timestamp: Ingress/egress 32b nanoseconds
On 4/8/2025 3:31 AM, Milena Olech wrote:
> Add Rx timestamp function when the Rx timestamp value is read directly
> from the Rx descriptor. In order to extend the Rx timestamp value to 64
> bit in hot path, the PHC time is cached in the receive groups.
> Add supported Rx timestamp modes.
>
> Si
-14.2.0
arc randconfig-001-20250408gcc-14.2.0
arc randconfig-002-20250408gcc-14.2.0
arcvdk_hs38_smp_defconfiggcc-14.2.0
arm allmodconfiggcc-14.2.0
arm allyesconfiggcc
Remove code that isn't reached. There is no need to check for
adapter->req_vec_chunks, because if it isn't set idpf_set_mb_vec_id()
won't be called.
Only one path when idpf_set_mb_vec_id() is called:
idpf_intr_req()
-> idpf_send_alloc_vectors_msg() -> adapter->req_vec_chunk is allocated
here, ot
From: Maciej Fijalkowski
Date: Wed, 19 Mar 2025 17:29:37 +0100
> On Mon, Mar 17, 2025 at 03:50:11PM +0100, Alexander Lobakin wrote:
>> From: Maciej Fijalkowski
>> Date: Fri, 7 Mar 2025 14:27:13 +0100
>>
>>> On Wed, Mar 05, 2025 at 05:21:27PM +0100, Alexander Lobakin wrote:
From: Michal Kubi
DPLL-enabled E810 NIC driver provides user with list of input and output
pins. Hardware internal design impacts user control over SMA and U.FL
pins. Currently end-user view on those dpll pins doesn't provide any layer
of abstraction. On the hardware level SMA and U.FL pins are tied together
due to
From: Karol Kolacinski
This change aligns E810 PTP pin control to all other products.
Currently, SMA/U.FL port expanders are controlled together with SDP pins
connected to 1588 clock. To align this, separate this control by
exposing only SDP20..23 pins in PTP API on adapters with DPLL.
Clear er
From: Karol Kolacinski
Add a description of PTP pins support by the adapters to ice driver
documentation.
Reviewed-by: Milena Olech
Signed-off-by: Karol Kolacinski
Signed-off-by: Arkadiusz Kubalewski
---
v4: no changes
---
.../device_drivers/ethernet/intel/ice.rst | 13
On Mon, 7 Apr 2025 22:39:17 +0200 Andrew Lunn wrote:
> How do you tell the kernel to stop managing the SFP? If you hit the
> module with a reset from user space, the kernel is going to get
> confused. And how are you talking to the module? Are you going to
> hijack the i2c device via i2-dev? Again,
On Mon, 7 Apr 2025 15:32:03 +0200 Kory Maincent wrote:
> ETHTOOL_PHY_G/STUNABLE IOCTLs are targeting the PHY of the NIC but IIUC in
> your
> case you are targeting the reset of the QSFP module. Maybe phylink API is more
> appropriate for this feature.
>
> You have to add net-next prefix in the s
Unlike previous internal idpf ctlq implementation, idpf calls the default
message handler for all received messages that do not have a matching xn
transaction, not only for VIRTCHNL2_OP_EVENT. This leads to many error
messages printing garbage, because the parsing expected a valid event
message, bu
From: Pavan Kumar Linga
Control queues can utilize libeth_rx fill queues, despite working
outside of NAPI context. The only problem is standard fill queues requiring
NAPI that provides them with the device pointer.
Introduce a way to provide the device directly without using NAPI.
Suggested-by:
From: Amritha Nambiar
Enable initial support for the devlink interface with the ixd
driver. The ixd hardware is a single function PCIe device. So, the
PCIe adapter gets its own devlink instance to manage device-wide
resources or configuration.
$ devlink dev show
pci/:83:00.6
$ devlink dev i
From: Phani R Burra
All send control queue messages are allocated/freed in libeth itself
and tracked with the unique transaction (Xn) ids until they receive
response or time out. Responses can be received out of order, therefore
transactions are stored in an array and tracked though a bitmap.
Pr
From: Victor Raj
In the virtchnl header file, add the Control Plane software
version fields.
Signed-off-by: Victor Raj
Reviewed-by: Sridhar Samudrala
Signed-off-by: Larysa Zaremba
---
include/linux/intel/virtchnl2.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/in
From: Pavan Kumar Linga
While sending a create vport message to the device
control plane, a create vport virtchnl message is
prepared with all the required info to initialize
the vport. This info is stored in the adapter struct
but never used thereafter. So, remove the said field.
Signed-off-by:
This patch series adds the iXD driver, which supports the Intel(R)
Control Plane PCI Function on Intel E2100 and later IPUs and FNICs.
It facilitates a centralized control over multiple IDPF PFs/VFs/SFs
exposed by the same card. The reason for the separation is to be able
to offload the control pla
Add module register and probe functionality. Add the required support
to register IXD PCI driver, as well as probe and remove call backs.
Enable the PCI device and request the kernel to reserve the memory
resources that will be used by the driver. Finally map the BAR0
address space.
For now, use d
As a consequence of refactoring idpf code to use libeth APIs,
idpf_vc_xn_shutdown was merged with and replaced by idpf_deinit_dflt_mbx.
This does not affect the Tx path, as it checked for a presence of an xn
manager anyway. Rx processing is handled by the mbx_task that is not always
cancelled befor
From: Alexander Lobakin
Date: Tue, 1 Apr 2025 15:11:50 +0200
> From: Maciej Fijalkowski
> Date: Wed, 19 Mar 2025 17:19:44 +0100
[...]
>> Not sure what to say here. Your time dedicated for making this work easier
>> to swallow means less time dedicated for going through this by reviewer.
I thi
On 4/8/2025 3:30 AM, Milena Olech wrote:
> Since workqueues are created per CPU, the works scheduled to this
> workqueues are run on the CPU they were assigned. It may result in
> overloaded CPU that is not able to handle virtchnl messages in
> relatively short time. Allocating workqueue with WQ
On 4/8/2025 3:30 AM, Milena Olech wrote:
> PTP capabilities are negotiated using virtchnl commands. There are two
> available modes of the PTP support: direct and mailbox. When the direct
> access to PTP resources is negotiated, virtchnl messages returns a set
> of registers that allow read/writ
On 4/8/2025 3:30 AM, Milena Olech wrote:
> +static u64 idpf_ptp_read_src_clk_reg_direct(struct idpf_adapter *adapter,
> + struct ptp_system_timestamp *sts)
> +{
> + struct idpf_ptp *ptp = adapter->ptp;
> + u32 hi, lo;
> +
> + spin_lock(&ptp->re
On 4/8/2025 3:30 AM, Milena Olech wrote:
> +static int idpf_ptp_read_src_clk_reg_mailbox(struct idpf_adapter *adapter,
> + struct ptp_system_timestamp *sts,
> + u64 *src_clk)
> +{
> + struct idpf_ptp_dev_timers
On 4/8/2025 3:31 AM, Milena Olech wrote:
> Add cross timestamp support through virtchnl mailbox messages and directly,
> through PCIe BAR registers. Cross timestamping assumes that both system
> time and device clock time values are cached simultaneously, what is
> triggered by HW. Feature is en
On 4/8/2025 3:31 AM, Milena Olech wrote:
> PTP clock configuration operations - set time, adjust time and adjust
> frequency are required to control the clock and maintain synchronization
> process.
>
> Extend get PTP capabilities function to request for the clock adjustments
> and add function
On 4/8/2025 3:30 AM, Milena Olech wrote:
> Move virtchnl structures to the header file to expose them for the PTP
> virtchnl file.
>
> Reviewed-by: Alexander Lobakin
> Reviewed-by: Willem de Bruijn
> Signed-off-by: Milena Olech
> Tested-by: Mina Almasry
> Tested-by: Samuel Salin
> ---
> v1
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