Dear Paolo,
Thank you for your patch.
Am 10.09.24 um 00:09 schrieb Paolo Abeni:
This allows a more uniform implementation of non-dump and dump
operations, and will be used later in the series to avoid some
per-operation allocation.
Additionally rename the NL_ASSERT_DUMP_CTX_FITS macro, to
fit
> -Original Message-
> From: Fijalkowski, Maciej
> Sent: Tuesday, September 3, 2024 9:59 PM
> To: Loktionov, Aleksandr
> Cc: intel-wired-...@lists.osuosl.org; Nguyen, Anthony L
> ; net...@vger.kernel.org; Sokolowski, Jan
> ; Connolly, Padraig J
>
> Subject: Re: [PATCH iwl-next v3] i40
On 9/10/24 10:29, Loktionov, Aleksandr wrote:
From: Fijalkowski, Maciej
Sent: Tuesday, September 3, 2024 9:59 PM
To: Loktionov, Aleksandr
Cc: intel-wired-...@lists.osuosl.org; Nguyen, Anthony L
; net...@vger.kernel.org; Sokolowski, Jan
; Connolly, Padraig J
Subject: Re: [PATCH iwl-next v3] i40
Dear Paolo,
Thank you for the patch. Some minor nits below.
Am 10.09.24 um 00:09 schrieb Paolo Abeni:
Define the user-space visible interface to query, configure and delete
network shapers via yaml definition.
Add dummy implementations for the relevant NL callbacks.
set() and delete() opera
Fix leak of the FW blob (DDP pkg).
Make ice_cfg_tx_topo() const-correct, so ice_init_tx_topology() can avoid
copying whole FW blob. Copy just the topology section, and only when
needed. Reuse the buffer allocated for the read of the current topology.
This was found by kmemleak, with the following
From: Larysa Zaremba
[ Upstream commit f50c68763436bc8f805712a7c5ceaf58cfcf5f07 ]
If VSI rebuild is pending, .ndo_bpf() can attach/detach the XDP program on
VSI without applying new ring configuration. When unconfiguring the VSI, we
can encounter the state in which there is an XDP program but no
> > This was originally worked out by Doug Boom at Intel. It had to do
> > with autonegotiation not being the part of the SFP optics when the
> > Denverton X550 Si was released and was thus not POR for DNV. The
> > Juniper switches however won't exit their AN sequence unless an AN37
> > transac
On 9/10/2024 6:57 AM, Przemek Kitszel wrote:
> Fix leak of the FW blob (DDP pkg).
>
> Make ice_cfg_tx_topo() const-correct, so ice_init_tx_topology() can avoid
> copying whole FW blob. Copy just the topology section, and only when
> needed. Reuse the buffer allocated for the read of the current
-20240910 clang-18
i386 buildonly-randconfig-001-20240911 gcc-12
i386 buildonly-randconfig-002-20240910 clang-18
i386 buildonly-randconfig-002-20240911 gcc-12
i386 buildonly-randconfig-003-20240910 clang-18
i386 buildonly-randconfig-003-20240911 gcc
randconfig-001-20240910 gcc-13.2.0
arc randconfig-002-20240910 gcc-13.2.0
arm allnoconfig gcc-14.1.0
arm randconfig-001-20240910 clang-20
arm randconfig-002-20240910 gcc-14.1.0
arm
On Tue, 10 Sep 2024 00:10:08 +0200 Paolo Abeni wrote:
> + if (adapter->netdev->reg_state == NETREG_REGISTERED) {
> + mutex_lock(&adapter->netdev->lock);
> + devlock = true;
> + }
This leads to a false positive in cocci.
Any concerns about moving the mutex_init() /
Currently the user may request DPLL_PIN_STATE_SELECTABLE for an output
pin, and this would actually set the DISCONNECTED state instead.
It doesn't make any sense. SELECTABLE is valid only in case of input pins
(on AUTOMATIC type dpll), where dpll itself would select best valid input.
For the output
Dpll's pins frequencies were hardcoded in the driver to the 1Hz/10MHz.
Fix it be allowing users to set full range of supported frequencies
which is a range 1Hz-25MHz.
Fixes: 8a3a565ff210 ("ice: add admin commands to access cgu configuration")
Reviewed-by: Aleksandr Loktionov
Signed-off-by: Arkadi
On Thu, Sep 05, 2024 at 07:51:15AM +, Loktionov, Aleksandr wrote:
>
>
> > -Original Message-
> > From: Kamal Heib
> > Sent: Thursday, September 5, 2024 1:57 AM
> > To: Loktionov, Aleksandr
> > Cc: YangHang Liu ; Chao Yang
> > ; ivecera ;
> > net...@vger.kernel.org; Jakub Kicinski ;
Dear Arkadiusz,
Thank you for your patch. It’d be great if you made the summary more
explicit. For example:
ice: Disallow DPLL_PIN_STATE_SELECTABLE for dpll output pins
Am 11.09.24 um 01:28 schrieb Arkadiusz Kubalewski:
Currently the user may request DPLL_PIN_STATE_SELECTABLE for an output
Dear Arkadiusz,
Thank you for your patch. It’d be great if you used a more specific
summary. Maybe:
ice: Allow full frequency range of 1 Hz–25 MHz for dpll pins
Some more nits below:
Am 11.09.24 um 01:29 schrieb Arkadiusz Kubalewski:
Dpll's pins frequencies were hardcoded in the driver to
16 matches
Mail list logo
