[Intel-wired-lan] [PATCH iwl-net] ice: fix dpll's pins frequencies

[Arkadiusz Kubalewski]

Dpll's pins frequencies were hardcoded in the driver to the 1Hz/10MHz.
Fix it be allowing users to set full range of supported frequencies
which is a range 1Hz-25MHz.

Fixes: 8a3a565ff210 ("ice: add admin commands to access cgu configuration")
Reviewed-by: Aleksandr Loktionov <aleksandr.loktio...@intel.com>
Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalew...@intel.com>
---
 drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c 
b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
index 3a33e6b9b313..496bd588525b 100644
--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
@@ -9,8 +9,7 @@
 #include "ice_cgu_regs.h"
 
 static struct dpll_pin_frequency ice_cgu_pin_freq_common[] = {
-       DPLL_PIN_FREQUENCY_1PPS,
-       DPLL_PIN_FREQUENCY_10MHZ,
+       DPLL_PIN_FREQUENCY_RANGE(1, 25000000),
 };
 
 static struct dpll_pin_frequency ice_cgu_pin_freq_1_hz[] = {
@@ -63,9 +62,9 @@ static const struct ice_cgu_pin_desc 
ice_e810t_sfp_cgu_outputs[] = {
        { "PHY-CLK",        ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
        { "MAC-CLK",        ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
        { "CVL-SDP21",      ZL_OUT4, DPLL_PIN_TYPE_EXT,
-               ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
+               ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
        { "CVL-SDP23",      ZL_OUT5, DPLL_PIN_TYPE_EXT,
-               ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
+               ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
 };
 
 static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_outputs[] = {
@@ -77,9 +76,9 @@ static const struct ice_cgu_pin_desc 
ice_e810t_qsfp_cgu_outputs[] = {
        { "PHY2-CLK",       ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
        { "MAC-CLK",        ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
        { "CVL-SDP21",      ZL_OUT5, DPLL_PIN_TYPE_EXT,
-               ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
+               ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
        { "CVL-SDP23",      ZL_OUT6, DPLL_PIN_TYPE_EXT,
-               ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
+               ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
 };
 
 static const struct ice_cgu_pin_desc ice_e823_si_cgu_inputs[] = {
-- 
2.38.1