allmodconfig gcc
arc allnoconfig gcc
arc allyesconfig gcc
arc defconfig gcc
arc randconfig-001-20231006 gcc
arm allmodconfig gcc
arm
Update the "How are representors identified?" documentation
subchapter. For newer kernels driver developers should use
SET_NETDEV_DEVLINK_PORT instead of ndo_get_devlink_port()
callback.
Signed-off-by: Mateusz Polchlopek
Reviewed-by: Wojciech Drewek
---
Documentation/networking/representors.rst
>From: Jiri Pirko
>Sent: Monday, October 2, 2023 4:53 PM
>
>Wed, Sep 27, 2023 at 11:24:33AM CEST, arkadiusz.kubalew...@intel.com wrote:
>>Add new pin's attributes to dpll netlink spec:
>>- phase-offset - measured difference between phase of signals on pin
>> and dpll
>>- phase-adjust - adjustable
>From: Jiri Pirko
>Sent: Wednesday, October 4, 2023 12:42 PM
>
>Wed, Oct 04, 2023 at 11:05:44AM CEST, arkadiusz.kubalew...@intel.com wrote:
>>Add attributes for providing the user with:
>>- measurement of signals phase offset between pin and dpll
>>- ability to adjust the phase of pin signal
>>
>>
For performance reasons there is a need to have support for selectable
Tx scheduler topology. Currently firmware supports only the default
9-layer and 5-layer topology. This patch series enables switch from
default to 5-layer topology, if user decides to opt-in.
---
v2:
- updated documentation
- r
From: Raj Victor
There is a performance issue when the number of VSIs are not multiple
of 8. This is caused due to the max children limitation per node(8) in
9 layer topology. The BW credits are shared evenly among the children
by default. Assume one node has 8 children and the other has 1.
The p
From: Raj Victor
Adjust the VSI/Aggregator layers based on the number of logical layers
supported by the FW. Currently the VSI and Aggregator layers are
fixed based on the 9 layer scheduler tree layout. Due to performance
reasons the number of layers of the scheduler tree is changing from
9 to 5.
From: Michal Wilczynski
Introduce support for Tx scheduler topology change, based on user
selection, from default 9-layer to 5-layer.
Change requires NVM (version 3.20 or newer) and DDP package (OS Package
1.3.30 or newer - available for over a year in linux-firmware, since
commit aed71f296637 in
From: Lukasz Czapnik
It was observed that Tx performance was inconsistent across all queues
and/or VSIs and that it was directly connected to existing 9-layer
topology of the Tx scheduler.
Introduce new private devlink param - tx_scheduling_layers. This parameter
gives user flexibility to choose
From: Michal Wilczynski
New driver specific parameter 'tx_scheduling_layers' was introduced.
Describe parameter in the documentation.
Signed-off-by: Michal Wilczynski
Reviewed-by: Przemek Kitszel
Co-developed-by: Mateusz Polchlopek
Signed-off-by: Mateusz Polchlopek
---
Documentation/network
The hardware provides the indexes of the first and the last available
queue and VF. From the indexes, the driver calculates the numbers of
queues and VFs. In theory, a faulty device might say the last index is
smaller than the first index. In that case, the driver's calculation
would underflow, it
On Thu, Oct 05, 2023 at 04:57:02PM +0300, Dan Carpenter wrote:
> The adapter->vf_mvs.l list needs to be initialized even if the list is
> empty. Otherwise it will lead to crashes.
>
> Fixes: c6bda30a06d9 ("ixgbe: Reconfigure SR-IOV Init")
Hi Dan,
I see that the patch cited above added the line
On Thu, Oct 05, 2023 at 04:57:21PM +0300, Dan Carpenter wrote:
> When we exit a list_for_each_entry() without hitting a break statement,
> the list iterator isn't NULL, it just point to an offset off the
> list_head. In that situation, it wouldn't be too surprising for
> entry->free to be true and
On Thu, Oct 05, 2023 at 04:58:01PM +0300, Dan Carpenter wrote:
> The list iterator in a list_for_each_entry() loop can never be NULL.
> If the loop exits without hitting a break then the iterator points
> to an offset off the list head and dereferencing it is an out of
> bounds access.
>
> Before
Improve monitoring and control over dpll devices.
Allow user to receive measurement of phase difference between signals on
pin and dpll (phase-offset).
Allow user to receive and control adjustable value of pin's signal
phase (phase-adjust).
v2->v3:
- do not increase do version of uAPI header as it
Add documentation on:
- measurment of phase of signal between pin and dpll
- adjustment of pin signal phase
Signed-off-by: Arkadiusz Kubalewski
---
Documentation/driver-api/dpll.rst | 53 ++-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/Documentation/
Add attributes for providing the user with:
- measurement of signals phase offset between pin and dpll
- ability to adjust the phase of pin signal
Signed-off-by: Arkadiusz Kubalewski
---
Documentation/netlink/specs/dpll.yaml | 33 ++-
drivers/dpll/dpll_nl.c
Add callback ops for pin-dpll phase measurment.
Add callback for pin signal phase adjustment.
Add min and max phase adjustment values to pin proprties.
Invoke callbacks in dpll_netlink.c when filling the pin details to
provide user with phase related attribute values.
Signed-off-by: Arkadiusz Kuba
Implement new callback ops related to measurment and adjustment of
signal phase for pin-dpll in ice driver.
Signed-off-by: Arkadiusz Kubalewski
---
drivers/net/ethernet/intel/ice/ice_dpll.c | 224 +-
drivers/net/ethernet/intel/ice/ice_dpll.h | 10 +-
2 files changed, 230 ins
Align the aproach of pin frequency set behavior with the approach
introduced with pin phase adjust set.
Fail the request if any of devices did not registered the callback ops.
If callback op on any pin's registered device fails, return error and
rollback the value to previous one.
Signed-off-by: A
On Fri, Oct 06, 2023 at 01:11:39PM +0200, Michal Schmidt wrote:
> The hardware provides the indexes of the first and the last available
> queue and VF. From the indexes, the driver calculates the numbers of
> queues and VFs. In theory, a faulty device might say the last index is
> smaller than the
Fri, Oct 06, 2023 at 01:40:58PM CEST, arkadiusz.kubalew...@intel.com wrote:
>Add attributes for providing the user with:
>- measurement of signals phase offset between pin and dpll
>- ability to adjust the phase of pin signal
>
>Signed-off-by: Arkadiusz Kubalewski
>---
> Documentation/netlink/spec
On Fri, Oct 06, 2023 at 01:41:00PM +0200, Arkadiusz Kubalewski wrote:
> Implement new callback ops related to measurment and adjustment of
> signal phase for pin-dpll in ice driver.
>
> Signed-off-by: Arkadiusz Kubalewski
Hi Arkadiusz,
some minor feedback from my side.
If you do end up re-spin
Fri, Oct 06, 2023 at 01:41:01PM CEST, arkadiusz.kubalew...@intel.com wrote:
>Align the aproach of pin frequency set behavior with the approach
>introduced with pin phase adjust set.
>Fail the request if any of devices did not registered the callback ops.
>If callback op on any pin's registered devi
Fri, Oct 06, 2023 at 01:40:59PM CEST, arkadiusz.kubalew...@intel.com wrote:
>Add callback ops for pin-dpll phase measurment.
>Add callback for pin signal phase adjustment.
>Add min and max phase adjustment values to pin proprties.
>Invoke callbacks in dpll_netlink.c when filling the pin details to
Fri, Oct 06, 2023 at 02:33:34PM CEST, ho...@kernel.org wrote:
>On Fri, Oct 06, 2023 at 01:41:00PM +0200, Arkadiusz Kubalewski wrote:
>> Implement new callback ops related to measurment and adjustment of
>> signal phase for pin-dpll in ice driver.
>>
>> Signed-off-by: Arkadiusz Kubalewski
>
>Hi Ar
On Fri, Oct 06, 2023 at 01:16:27PM +0200, Simon Horman wrote:
> On Thu, Oct 05, 2023 at 04:57:02PM +0300, Dan Carpenter wrote:
> > The adapter->vf_mvs.l list needs to be initialized even if the list is
> > empty. Otherwise it will lead to crashes.
> >
> > Fixes: c6bda30a06d9 ("ixgbe: Reconfigure
The adapter->vf_mvs.l list needs to be initialized even if the list is
empty. Otherwise it will lead to crashes.
Fixes: a1cbb15c1397 ("ixgbe: Add macvlan support for VF")
Signed-off-by: Dan Carpenter
---
v2: Use the correct fixes tag. Thanks, Simon.
drivers/net/ethernet/intel/ixgbe/ixgbe_srio
On Fri, Oct 06, 2023 at 03:49:39PM +0300, Dan Carpenter wrote:
> On Fri, Oct 06, 2023 at 01:16:27PM +0200, Simon Horman wrote:
> > On Thu, Oct 05, 2023 at 04:57:02PM +0300, Dan Carpenter wrote:
> > > The adapter->vf_mvs.l list needs to be initialized even if the list is
> > > empty. Otherwise it w
On Fri, Oct 06, 2023 at 03:53:09PM +0300, Dan Carpenter wrote:
> The adapter->vf_mvs.l list needs to be initialized even if the list is
> empty. Otherwise it will lead to crashes.
>
> Fixes: a1cbb15c1397 ("ixgbe: Add macvlan support for VF")
> Signed-off-by: Dan Carpenter
> ---
> v2: Use the cor
On Fri, 6 Oct 2023 14:30:00 +0200 Jiri Pirko wrote:
> >+version: 2
>
> I'm confused. Didn't you say you'll remove this? If not, my question
> from v1 still stands.
Perhaps we should dis-allow setting version in non-genetlink-legacy
specs? I thought it may be a useful thing to someone, at some p
arc allnoconfig gcc
arc allyesconfig gcc
arc defconfig gcc
arc randconfig-001-20231006 gcc
arm allmodconfig gcc
arm
> -Original Message-
> From: Intel-wired-lan On Behalf Of
> Simon Horman
> Sent: Wednesday, October 4, 2023 3:46 PM
> To: Brandeburg, Jesse
> Cc: net...@vger.kernel.org; Christophe JAILLET
> ; intel-wired-...@lists.osuosl.org; Kitszel,
> Przemyslaw
> Subject: Re: [Intel-wired-lan] [PATCH
Fri, Oct 06, 2023 at 04:55:36PM CEST, k...@kernel.org wrote:
>On Fri, 6 Oct 2023 14:30:00 +0200 Jiri Pirko wrote:
>> >+version: 2
>>
>> I'm confused. Didn't you say you'll remove this? If not, my question
>> from v1 still stands.
>
>Perhaps we should dis-allow setting version in non-genetlink-le
On Fri, 6 Oct 2023 18:53:04 +0200 Jiri Pirko wrote:
> Fri, Oct 06, 2023 at 04:55:36PM CEST, k...@kernel.org wrote:
> >> I'm confused. Didn't you say you'll remove this? If not, my question
> >> from v1 still stands.
> >
> >Perhaps we should dis-allow setting version in non-genetlink-legacy
> >spe
If an attribute of an aggregate interface disqualifies it from supporting
SRIOV, the driver will unwind the SRIOV support. Currently the driver is
clearing the feature bit for all interfaces in the aggregate, but this is
not allowing the other interfaces to unwind successfully on driver unload.
O
> -Original Message-
> From: Mateusz Polchlopek
> Sent: Friday, October 6, 2023 2:14 AM
> To: intel-wired-...@lists.osuosl.org
> Cc: net...@vger.kernel.org; Polchlopek, Mateusz
> ; Drewek, Wojciech
>
> Subject: [Intel-wired-lan] [PATCH iwl-net v1] docs: update info about
> representor
Patch 1 adds the support at the Kernel level, allowing the user to set a
symmetric RSS hash for any flow type via:
# ethtool -N|-U eth0 rx-flow-hash s|d|f|n symmetric
Support for the new "symmetric" flag will be later sent to the "ethtool"
user-space tool.
Patch 2 fixes a long standing bug
Symmetric RSS hash functions are beneficial in applications that monitor
both Tx and Rx packets of the same flow (IDS, software firewalls, ..etc).
Getting all traffic of the same flow on the same RX queue results in
higher CPU cache efficiency.
Only fields that has counterparts in the other direct
Fix the values of the ICE_AQ_VSI_Q_OPT_RSS_* registers. Shifting is
already done when the values are used, no need to double shift. Bug was
not discovered earlier since only ICE_AQ_VSI_Q_OPT_RSS_TPLZ (Zero) is
currently used.
Also, rename ICE_AQ_VSI_Q_OPT_RSS_XXX to ICE_AQ_VSI_Q_OPT_RSS_HASH_XXX
f
From: Qi Zhang
Refactor the driver to use a communication data structure for RSS
config. To do so we introduce the new ice_rss_hash_cfg struct, and then
pass it as an argument to several functions.
Also introduce enum ice_rss_cfg_hdr_type to specify a more granular and
flexible RSS configuration
The flow director and RSS blocks use separate methods to generate a
unique 64 bit ID for the flow. This is not extendable, especially for
the RSS that already uses all 64 bit space.
Refactor the flow generation API so that the ID is generated within
ice_flow_add_prof(). The FD and RSS blocks cache
From: Jeff Guo
The hash function in the E800 NICs is set per-VSI and a specific AQ
command is needed to modify the hash function. Use the AQ command to
enable setting the symmetric Toeplitz RSS hash function for any VSI.
When the Symmetric Toeplitz hash function is used, the hardware sets the
in
Allow the VFs to support symmetric RSS for any flow type. The symmetric
RSS will not be supported on PFs not advertising the ADV RSS Offload
flag (ADV_RSS_SUPPORT()), for example the E700 series (i40e).
Reviewed-by: Madhu Chittim
Signed-off-by: Ahmed Zaki
---
.../net/ethernet/intel/iavf/iavf_ad
On Fri, 6 Oct 2023 16:47:21 -0600 Ahmed Zaki wrote:
> Symmetric RSS hash functions are beneficial in applications that monitor
> both Tx and Rx packets of the same flow (IDS, software firewalls, ..etc).
> Getting all traffic of the same flow on the same RX queue results in
> higher CPU cache effic
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