DPLL of type EEC for E825c,
- create recovered clock pin for each PF, and control them through
writing to registers,
- create pin to control clock 1588 for PF0, and control it through
writing to registers.
Reviewed-by: Milena Olech
Signed-off-by: Przemyslaw Korba
---
drivers/net/ethernet/intel
: 3a7496234d17 ("ice: implement basic E822 PTP support")
Reviewed-by: Milena Olech
Signed-off-by: Przemyslaw Korba
---
Changelog:
v2:
change commit message
v1:
https://lore.kernel.org/intel-wired-lan/20241126102311.344972-1-przemyslaw.ko...@intel.com/
---
drivers/net/ethernet/intel/ice/ice_pt
: 3a7496234d17 ("ice: implement basic E822 PTP support")
Reviewed-by: Milena Olech
Signed-off-by: Przemyslaw Korba
---
drivers/net/ethernet/intel/ice/ice_ptp_consts.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_consts.h
b/d
Fix incorrect PHY timestamp extraction for ETH56G.
It's better to use FIELD_PREP() than manual shift.
Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products")
Reviewed-by: Przemek Kitszel
Reviewed-by: Simon Horman
Signed-off-by: Przemyslaw Korba
---
Changelog
v
Fix incorrect PHY timestamp extraction for ETH56G.
It's better to use FIELD_PREP() than manual shift.
Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products")
Reviewed-by: Przemek Kitszel
Signed-off-by: Przemyslaw Korba
---
drivers/net/ethernet/intel/ice/i
Fix incorrect PHY timestamp extraction for ETH56G.
It's better to use FIELD_PREP() than manual shift.
Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products")
Reviewed-by: Przemek Kitszel
Signed-off-by: Przemyslaw Korba
---
drivers/net/ethernet/intel/ice/i