0,
'id': 39,
'module-name': 'ice',
'parent-device': [{'direction': 'output',
'parent-id': 9,
'state': 'connected'}],
'phase-adjust-max': 0,
'p
id': 28, 'state': 'disconnected'}],
'phase-adjust-max': 0,
'phase-adjust-min': 0,
'type': 'synce-eth-port'},
{'capabilities': {'state-can-change'},
'clock-id': 0,
'id': 34,
27;: 28, 'state': 'disconnected'}],
'phase-adjust-max': 0,
'phase-adjust-min': 0,
'type': 'synce-eth-port'},
{'capabilities': {'state-can-change'},
'clock-id': 0,
'id': 34,
'module-nam
27;: 28, 'state': 'disconnected'}],
'phase-adjust-max': 0,
'phase-adjust-min': 0,
'type': 'synce-eth-port'},
{'capabilities': {'state-can-change'},
'clock-id': 0,
'id': 34,
'module-na
abstraction to:
- create a DPLL of type EEC for E825c,
- create recovered clock pin for each PF, and control them through
writing to registers,
- create pin to control clock 1588 for PF0, and control it through
writing to registers.
Reviewed-by: Milena Olech
Co-developed-by: Grzegorz Nitka
Signed
abstraction to:
- create a DPLL of type EEC for E825c,
- create recovered clock pin for each PF, and control them through
writing to registers,
- create pin to control clock 1588 for PF0, and control it through
writing to registers.
Reviewed-by: Milena Olech
Co-developed-by: Grzegorz Nitka
Signed
abstraction to:
- create a DPLL of type EEC for E825c,
- create recovered clock pin for each PF, and control them through
writing to registers,
- create pin to control clock 1588 for PF0, and control it through
writing to registers.
Reviewed-by: Milena Olech
Co-developed-by: Grzegorz Nitka
Signed
abstraction to:
- create a DPLL of type EEC for E825c,
- create recovered clock pin for each PF, and control them through
writing to registers,
- create pin to control clock 1588 for PF0, and control it through
writing to registers.
Reviewed-by: Milena Olech
Co-developed-by: Grzegorz Nitka
Signed
0x5b/0x180
entry_SYSCALL_64_after_hwframe+0x76/0x7e
Testing hints (ethX is PF netdev):
- create at least one VF
echo 1 > /sys/class/net/ethX/device/sriov_numvfs
- trigger the reset
echo 1 > /sys/class/net/ethX/device/reset
Fixes: 415db8399d06 ("ice: make representor code generic")
Signed-off-by: G
0x5b/0x180
entry_SYSCALL_64_after_hwframe+0x76/0x7e
Testing hints (ethX is PF netdev):
- create at least one VF
echo 1 > /sys/class/net/ethX/device/sriov_numvfs
- trigger the reset
echo 1 > /sys/class/net/ethX/device/reset
Fixes: 415db8399d06 ("ice: make representor code generic")
Signed-off-by: G
This patch series adds full support for timesync operations for E8225C
devices which are configured in so called 2xNAC mode (Network
Acceleration Complex). 2xNAC mode is the mode in which IO die
is housing two complexes and each of them has its own PHY connected
to it. The complex which controls ti
ingle or dual), when accessing its own ports,
they're accessed always as 'phy_0' client. And referred as 'phy_0_peer'
when handling ports conneced to the other complex.
Reviewed-by: Simon Horman
Reviewed-by: Przemek Kitszel
Signed-off-by: Karol Kolacinski
Co-deve
veloped-by: Grzegorz Nitka
Signed-off-by: Grzegorz Nitka
---
drivers/net/ethernet/intel/ice/ice.h| 60 -
drivers/net/ethernet/intel/ice/ice_common.c | 6 ++-
drivers/net/ethernet/intel/ice/ice_ptp.c| 49 -
drivers/net/ethernet/intel/i
with older driver/kernel versions.
Reviewed-by: Michal Swiatkowski
Reviewed-by: Przemek Kitszel
Signed-off-by: Karol Kolacinski
Signed-off-by: Grzegorz Nitka
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 23 -
1 file changed, 23 deletions(-)
diff --git a/drivers/ne
ingle or dual), when accessing its own ports,
they're accessed always as 'phy_0' client. And referred as 'phy_0_peer'
when handling ports conneced to the other complex.
Reviewed-by: Simon Horman
Reviewed-by: Przemek Kitszel
Signed-off-by: Karol Kolacinski
Co-deve
#x27;dual' mode config (by adding fixed offset for PHY1
ports). Cache this value in ice_hw struct.
Introduce ice_get_primary_hw wrapper to get access to timesync register
not available from second NAC.
Reviewed-by: Przemek Kitszel
Signed-off-by: Karol Kolacinski
Co-developed-by: Grzegorz
This patch series adds full support for timesync operations for E8225C
devices which are configured in so called 2xNAC mode (Network
Acceleration Complex). 2xNAC mode is the mode in which IO die
is housing two complexes and each of them has its own PHY connected
to it. The complex which controls ti
.
Remove workaround as it's not needed anymore. The fix in autoload
procedure has been provided with NVM 3.80 version.
Reviewed-by: Michal Swiatkowski
Reviewed-by: Przemek Kitszel
Signed-off-by: Karol Kolacinski
Signed-off-by: Grzegorz Nitka
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
auto-negotiation: Yes
Supported FEC modes: None
Advertised link modes: 100baseT/Full
1000baseT/Full
1baseT/Full
...
Fixes: f64e189442332 ("ice: introduce new E825C devices family")
Signed-off-by
#x27;dual' mode config (by adding fixed offset for PHY1
ports). Cache this value in ice_hw struct.
Introduce ice_get_primary_hw wrapper to get access to timesync register
not available from second NAC.
Reviewed-by: Przemek Kitszel
Signed-off-by: Karol Kolacinski
Co-developed-by: Grzegorz
ingle or dual), when accessing its own ports,
they're accessed always as 'phy_0' client. And referred as 'phy_0_peer'
when handling ports conneced to the other complex.
Reviewed-by: Przemek Kitszel
Signed-off-by: Karol Kolacinski
Co-developed-by: Grzegorz Nitka
Signed-
workaround as it's not needed anymore. The fix in autoload
procedure has been provided with NVM 3.80 version.
Reviewed-by: Michal Swiatkowski
Reviewed-by: Przemek Kitszel
Signed-off-by: Karol Kolacinski
Signed-off-by: Grzegorz Nitka
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
This patch series adds full support for timesync operations for E8225C
devices which are configured in so called 2xNAC mode (Network
Acceleration Complex). 2xNAC mode is the mode in which IO die
is housing two complexes and each of them has its own PHY connected
to it. The complex which controls ti
amily")
Signed-off-by: Grzegorz Nitka
Reviewed-by: Aleksandr Loktionov
---
drivers/net/ethernet/intel/ice/ice_common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c
b/drivers/net/ethernet/intel/ice/ice_common.c
index 7a2a2e8da8fa..caf3af2a32c3 10
PHY lane assignment")
Co-developed-by: Karol Kolacinski
Signed-off-by: Karol Kolacinski
Signed-off-by: Grzegorz Nitka
Reviewed-by: Przemek Kitszel
Reviewed-by: Milena Olech
---
drivers/net/ethernet/intel/ice/ice_common.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/net/e
patch.
Reviewed-by: Simon Horman
Reviewed-by: Przemek Kitszel
Signed-off-by: Karol Kolacinski
Signed-off-by: Grzegorz Nitka
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 31 ++---
1 file changed, 14 insertions(+), 17 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice
From: Karol Kolacinski
Simplify ice_phy_reg_info_eth56g struct definition to include base
address for the very first quad. Use base address info and 'step'
value to determine address for specific PHY quad.
Reviewed-by: Przemek Kitszel
Signed-off-by: Karol Kolacinski
Signed-off-by
From: Karol Kolacinski
Refactor the code by changing ice_ptp_init_phc_eth56g function
name to ice_ptp_init_phc_e825, to be consistent with the naming pattern
for other devices.
Signed-off-by: Karol Kolacinski
Signed-off-by: Grzegorz Nitka
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 13
This patch series simplifies PTP code related to E825C products by
simplifying PHY register info definition.
Cleanup the code by removing unused register definitions.
v1->v2:
* remove sync delay adding from the series (patch 1/3). To be submitted as
separate patch.
* fix kdoc (patch 2/3) in ice_
patch.
Reviewed-by: Przemek Kitszel
Signed-off-by: Karol Kolacinski
Signed-off-by: Grzegorz Nitka
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 31 ++---
1 file changed, 14 insertions(+), 17 deletions(-)
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
b/drivers
From: Karol Kolacinski
Simplify ice_phy_reg_info_eth56g struct definition to include base
address for the very first quad. Use base address info and 'step'
value to determine address for specific PHY quad.
Reviewed-by: Przemek Kitszel
Signed-off-by: Karol Kolacinski
Signed-off-by
for other devices.
Reviewed-by: Przemek Kitszel
Signed-off-by: Karol Kolacinski
Signed-off-by: Grzegorz Nitka
---
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 14 +++---
drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 3 +++
2 files changed, 10 insertions(+), 7 deletions(-)
diff --git
This patch series simplifies PTP code related to E825C products by
simplifying PHY register info definition.
Cleanup the code by removing unused register definitions.
Also, add sync delay compensation between PHC and PHY for E825C.
Karol Kolacinski (3):
ice: Add sync delay for E825C
ice: Refac
x239/0x340
[] kthread+0xcc/0x100
[] ret_from_fork+0x2d/0x50
[] ret_from_fork_asm+0x1a/0x30
...
Fixes: 28bf26724fdb ("ice: Implement aRFS")
Reviewed-by: Michal Swiatkowski
Signed-off-by: Grzegorz Nitka
---
drivers/net/ethernet/intel/ice/ice_arfs.c | 2 +-
1 file changed, 1 inse
: 4409ea1726cb ("ice: Adjust PTP init for 2x50G E825C devices")
Reviewed-by: Przemek Kitszel
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
Signed-off-by: Grzegorz Nitka
---
V1 -> V3: Added checker for speed value in returned AQ Get Options
.../net/ethernet/intel/ice/ice
From: Karol Kolacinski
Fix ETH56G FC-FEC incorrect Rx offset value by changing it from -255.96
to -469.26 ns.
Those values are derived from HW spec and reflect internal delays.
Hex value is a fixed point representation in Q23.9 format.
Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E
SBQ destination device based on port.
Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products")
Reviewed-by: Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
Signed-off-by: Grzegorz Nitka
---
V3 -> V4: Removed unrelated refactor/cleanup code
V2 -> V3
Arkadiusz Kubalewski
Signed-off-by: Karol Kolacinski
Signed-off-by: Grzegorz Nitka
---
V1 -> V3: Removed net-next hunks,
add 'return' on PHY revision read failure
V1 -> V2: Removed net-next hunks
drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 22 +
1
E825 products have incorrect initialization procedure, which may lead to
initialization failures and register values.
Fix E825 products initialization by adding correct sync delay, checking
the PHY revision only for current PHY and adding proper destination
device when reading port/quad.
In addit
From: Karol Kolacinski
Quad registers are read/written incorrectly. E825 devices always use
quad 0 address and differentiate between the PHYs by changing SBQ
destination device (phy_0 or phy_0_peer).
Add helpers for reading/writing PTP registers shared per quad and use
correct quad address and S
From: Karol Kolacinski
Driver always naively assumes, that for PTP purposes, PHY lane to
configure is corresponding to PF ID.
This is not true for some port configurations, e.g.:
- 2x50G per quad, where lanes used are 0 and 2 on each quad, but PF IDs
are 0 and 1
- 100G per quad on 2 quads, whe
From: Karol Kolacinski
Current implementation checks revision of all PHYs on all PFs, which is
incorrect and may result in initialization failure. Check only the
revision of the current PHY.
Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products")
Reviewed-by: Arkadiusz Kubalew
From: Karol Kolacinski
Fix ETH56G FC-FEC incorrect Rx offset value by changing it from -255.96
to -469.26 ns.
Those values are derived from HW spec and reflect internal delays.
Hex value is a fixed point representation in Q23.9 format.
Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E
E825 products have incorrect initialization procedure, which may lead to
initialization failures and register values.
Fix E825 products initialization by adding correct sync delay, checking
the PHY revision only for current PHY and adding proper destination
device when reading port/quad.
In addit
;
Signed-off-by: Grzegorz Nitka
---
drivers/net/ethernet/intel/ice/ice_common.c | 6 ++
drivers/net/ethernet/intel/ice/ice_ddp.c| 4
2 files changed, 10 insertions(+)
diff --git a/drivers/net/ethernet/intel/ice/ice_common.c
b/drivers/net/ethernet/intel/ice/ice_common.c
index
s the idea/intention better. Also rework
ice_is_sbq_supported to use this new function.
As side-band queue is supported for E825C devices, it's mac_type is
considered as generic mac_type.
Co-developed-by: Anirudh Venkataramanan
Signed-off-by: Anirudh Venkataramanan
Signed-off-by: Grzegor
(R) Ethernet Connection E825-C for SGMII
Add helper function ice_is_e825c() to verify if the running device
belongs to E825C family.
Co-developed-by: Jan Glaza
Signed-off-by: Jan Glaza
Co-developed-by: Michal Michalik
Signed-off-by: Michal Michalik
Signed-off-by: Grzegorz Nitka
---
drivers
support for new PHY and NAC topology parser
will be added.
Grzegorz Nitka (3):
ice: introduce new E825C devices family
ice: Add helper function ice_is_generic_mac
ice: add support for 3k signing DDP sections for E825C
drivers/net/ethernet/intel/ice/ice_common.c | 37
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