From: Alex Dai
The HuC authentication is done by host2guc call. The HuC RSA keys
are sent to GuC for authentication.
Signed-off-by: Alex Dai
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/i915_guc_submission.c | 65 ++
drivers/gpu/drm/i915/intel_guc_fwif.h
From: Alex Dai
Add debugfs entry for HuC loading status check.
Signed-off-by: Alex Dai
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/i915_debugfs.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/
On 01/12/2016 04:11 AM, Dave Gordon wrote:
On 06/01/16 20:53, yu@intel.com wrote:
> From: Alex Dai
>
> During driver unloading, the guc_client created for command submission
> needs to be released to avoid memory leak.
>
> Signed-off-by: Alex Dai
> ---
> drivers/gpu/drm/i915/i915_guc_su
From: Alex Dai
During driver unloading, the guc_client created for command submission
needs to be released to avoid memory leak.
The struct_mutex needs to be held before tearing down GuC.
v1: Move i915_guc_submission_disable out of i915_guc_submission_fini and
take struct_mutex lock before
On 01/13/2016 10:15 AM, Dave Gordon wrote:
On 12/01/16 23:17, yu@intel.com wrote:
> From: Alex Dai
>
> During driver unloading, the guc_client created for command submission
> needs to be released to avoid memory leak.
>
> The struct_mutex needs to be held before tearing down GuC.
>
> v1:
From: Alex Dai
During driver unloading, the guc_client created for command submission
needs to be released to avoid memory leak.
The struct_mutex needs to be held before tearing down GuC.
v1: Move i915_guc_submission_disable out of i915_guc_submission_fini and
take struct_mutex lock before
This version resolved the issue (kernel bug check in
intel_lr_context_clean_ring) I reported on previous versions. Verified
by igt drv_module_reload_basic, gem_close_race and -t basic tests.
Reviewed-by: Alex Dai
On 01/13/2016 08:19 AM, Nick Hoath wrote:
Use the first retired request on a ne
Thanks for capture the typo. LGTM.
Reviewed-by: Alex Dai
On 01/18/2016 07:59 AM, Arun Siluvery wrote:
In GuC submission mode, driver has to provide a list of registers to be
save/restored during gpu reset, make the max no. of registers value consistent
with that of the value defined in FW. If
I am OK with change here. However, in i915_drv.h, please check
definition of HAS_GUC_UCODE() and HAS_GUC_SCHED(). I believe they are
disabled for KBL.
Thanks,
Alex
On 01/18/2016 06:41 AM, Peter Antoine wrote:
This patch added the loading of the GuC for Kabylake.
It loads a 2.4 firmware.
Sign
On 01/19/2016 01:25 PM, Daniel Vetter wrote:
On Tue, Jan 19, 2016 at 09:18:50PM +, Peter Antoine wrote:
> This reverts commit a92d3f32eafc57cca55e654ecfd916f283100365.
Shouldnt' this be patch 2/2? Enabling guc loading before it's fixed isn't
awesome.
Either way needs a proper commit messa
On 01/08/2016 07:03 AM, Peter Antoine wrote:
This patch resizes the GuC WOPCM to so that the GuC and the RC6 memory
spaces do not overlap.
Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signed-off-by: Peter Antoine
---
drivers/gpu/drm/i915/i915_guc_reg.h | 3 ++-
drivers/gpu/
From: Alex Dai
Previously GuC uses ring id as engine id because of same definition.
But this is not true since this commit:
commit de1add360522c876c25ef2ab1c94bdb509ab
Author: Tvrtko Ursulin
Date: Fri Jan 15 15:12:50 2016 +
drm/i915: Decouple execbuf uAPI from internal implementa
On 01/23/2016 10:25 AM, Chris Wilson wrote:
On Fri, Jan 22, 2016 at 03:06:28PM -0800, yu@intel.com wrote:
> From: Alex Dai
>
> Previously GuC uses ring id as engine id because of same definition.
> But this is not true since this commit:
>
> commit de1add360522c876c25ef2ab1c94bdb509ab
From: Alex Dai
Previously GuC uses ring id as engine id because of same definition.
But this is not true since this commit:
commit de1add360522c876c25ef2ab1c94bdb509ab
Author: Tvrtko Ursulin
Date: Fri Jan 15 15:12:50 2016 +
drm/i915: Decouple execbuf uAPI from internal implementa
From: "Yu(Alex) Dai"
Add "zorder" property to crtc to control Z-order of sprite and
primary planes. The alpha channel of the planes can be enabled
or disabled during Z-order change.
Signed-off-by: Yu(Alex) Dai
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h
From: "Yu(Alex) Dai"
Add "zorder" property to crtc to control Z-order of sprite and
primary planes. The alpha channel of the planes can be enabled
or disabled during Z-order change.
Signed-off-by: Yu(Alex) Dai
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h
From: "Yu(Alex) Dai"
Add code to check invalid z-order. Also, avoid z-order setting if there
is no change in z-order.
Yu(Alex) Dai (1):
drm/i915: add support for Z-order of planes.
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 10 +
drivers/gpu/drm/i
From: "Yu(Alex) Dai"
Add "zorder" property to crtc to control Z-order of sprite and
primary planes. The alpha channel of the planes can be enabled
or disabled during Z-order change.
This is enabled for Valleyview only.
Signed-off-by: Yu(Alex) Dai
---
drivers/gpu/drm/i915/i915_drv.h | 1
From: "Yu(Alex) Dai"
Add "zorder" property to crtc to control Z-order of sprite and
primary planes. The alpha channel of the planes can be enabled
or disabled during Z-order change.
Signed-off-by: Yu(Alex) Dai
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h
On 14-02-28 11:28 AM, Matt Roper wrote:
On Fri, Feb 28, 2014 at 06:03:11PM +0200, Ville Syrjälä wrote:
On Thu, Feb 27, 2014 at 03:44:04PM -0800, Matt Roper wrote:
On Thu, Feb 27, 2014 at 02:36:06PM -0800, Yu Dai wrote:
On 14-02-25 04:19 PM, Matt Roper wrote:
On Thu, Feb 20, 2014 at 04:11
Chris,
This looks like a hw specific value which is difficult to understand.
However, the definition of these values are just a list of available
options of z-order. On Intel VLV, there is only 6 options for the three
planes Primary, Sprite A and Sprite B. Cursor is always on top. For
example
All,
Thanks for the review of z-order patch. Based on that, we had some
internal discussion within our Display driver team. Here is the summary.
1. Re: define plane z-order combinations as an enum property
User mode needs extra work to understand the definition. The number of
combinations ex
From: "Yu(Alex) Dai"
Add "zorder" property to crtc to control Z-order of sprite and
primary planes. The plane tag is packed into the 64 bits value
in the order of from bottom (lower bits) to top (higher bits).
Four bits are used for each plane tag. It can support up to 16
planes.
The alpha chann
On 03/21/2014 04:03 PM, Matt Roper wrote:
On Thu, Mar 20, 2014 at 11:53:07AM -0700, Yu Dai wrote:
All,
Thanks for the review of z-order patch. Based on that, we had some
internal discussion within our Display driver team. Here is the
summary.
1. Re: define plane z-order combinations as an
From: "Michael H. Nguyen"
i915_gem_object_write() is a generic function to copy data from
user memory to gem object.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_gem.c | 30 ++
2 files changed, 33 in
From: Alex Dai
Add GuC firmware loader. It uses the unified firmware loader to
fetch firmware blob first, then load to hw in driver main thread.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_dma.c | 6 +
driver
From: Alex Dai
These functions will be used by GuC scheduler.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_lrc.c | 6 +++---
drivers/gpu/drm/i915/intel_lrc.h | 3 +++
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/dri
From: Alex Dai
Allocate a gem obj to hold GuC log data. Also a debugfs interface
(i915_guc_log_dump) is provided to print out the log content.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_debugfs.c| 29 +++
drivers/gpu/drm/i915/i915_drv.h
From: Dave Gordon
In order to fully initialise the default contexts, we have to execute
batchbuffer commands on the GPU engines. But we can't do that until any
required firmware has been loaded, which may not be possible during
driver load, because the filesystem(s) containing the firmware may no
From: Alex Dai
These are the subset of GuC interface that we are going to use to
enable command submission through GuC. The definition of these
struct and bit setting need to match those in firmware.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_guc_api.h | 217 +++
From: Dave Gordon
Factor out the common code of loading firmware into a new file,
leaving only the uC-specific parts in the GuC loaders.
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/Makefile | 3 +
drivers/gpu/drm/i915/intel_uc_loader.
From: Alex Dai
This series of patch is to enable ExecList submission via GuC. Here are some
key points related to this series, not in particular order.
*** i915_guc_client ***
We use the term client to avoid confusion with contexts. A i915_guc_client is
equivalent to GuC object guc_context_desc.
From: Alex Dai
Turn on interrupt steering to route necessary interrupts to GuC.
Issue: VIZ-4884
Signed-off-by: Dave Gordon
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_reg.h| 11 --
drivers/gpu/drm/i915/intel_guc.h | 7
drivers/gpu/drm/i915/intel_guc_s
From: Alex Dai
Implementation of GuC client. A GuC client has its own doorbell
and workqueue. It maintains the doorbell cache line, process
description object and work queue item.
A default guc_client is created to do the in-order legacy execlist
submission.
Issue: VIZ-4884
Signed-off-by: Alex
From: Sagar Kamble
Need to take forcewake before GuC loading.
Issue: VIZ-4884
Change-Id: Ie422fc1e122933b161ff63cab23622197e6bba54
Signed-off-by: Sagar Kamble
---
drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc_loade
From: Alex Dai
GuC firmware uses the one page after Ring Context as shared data.
However, GuC uses same offset to address this page for all rings.
So we have to allocate same size of lrc context for all rings.
Also, reduce ring buffer size to 4 pages. In GuC, work queue tail is
referenced by 11
From: Alex Dai
Whenever RC6 state (0xA210) is changed, driver needs to notify GuC
via guc_action.
Issue: VIZ-4884
Change-Id: I15c661a915c670691d020471ecaccb00f7afb624
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_guc_api.h | 1
From: "Michael H. Nguyen"
Move defines from intel_lrc.c to i915_reg.h so they are
accessible by the guc files
Issue: VIZ-4884
Signed-off-by: Michael H. Nguyen
---
drivers/gpu/drm/i915/i915_reg.h | 68
drivers/gpu/drm/i915/intel_lrc.c | 67 -
From: Alex Dai
Add functions to submit work queue item and ring the door bell.
GuC TLB needs to be invalided if LRC context changes.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_guc.h | 3 +
drivers/gpu/drm/i915/intel_guc_client.c| 175
From: Alex Dai
Set the firmware version that required by HW. Driver sets required
version according to platform. After firmware is loaded but before
send to HW, the major.minor version is read from CSS header field,
which is 17th DWORD currently. The major version must be same; the
minor version
From: Alex Dai
To enable GuC command submission / scheduling, we need to setup
firmware initializaion properly. i915.enable_guc_scheduling is
introduced to enable / disable GuC submission.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/g
From: Alex Dai
All gem objects used by GuC are pinned to ggtt space out of range
[0, WOPCM size]. In GuC address space mapping, [0, WPOCM size] is
used internally for its Boot ROM, SRAM etc. Currently this WPOCM
size is 512K. This is done by using of PIN_OFFSET_BIAS.
Issue: VIZ-4884
Signed-off-b
From: Alex Dai
Now print out Bootrom, uKernel and MIA Core status. The scratch reg
0 & 15 are used for communication between driver and firmware. Their
status is also printed out.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_debugfs.c | 73 +
On 03/27/2015 01:45 AM, Daniel Vetter wrote:
On Thu, Mar 26, 2015 at 12:41:13PM -0700, yu@intel.com wrote:
> From: Dave Gordon
>
> In order to fully initialise the default contexts, we have to execute
> batchbuffer commands on the GPU engines. But we can't do that until any
> required firm
From: Alex Dai
These are the subset of GuC interface that we are going to use to
enable command submission through GuC. The definition of these
struct and bit setting need to match those in firmware.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_guc_api.h | 217 +++
From: Alex Dai
v2:
1. Add kernel-doc patch. All comments here have been moved into source code.
2. Change the way to load fw because a signed firmware has different layout.
3. One previous patch to notify GuC about RC6 feature is dropped for future
submission. Need to double check the potentia
From: Alex Dai
Implementation of GuC client. A GuC client has its own doorbell
and workqueue. It maintains the doorbell cache line, process
description object and work queue item.
A default guc_client is created to do the in-order legacy execlist
submission.
Issue: VIZ-4884
Signed-off-by: Alex
From: "Michael H. Nguyen"
Move defines from intel_lrc.c to i915_reg.h so they are
accessible by the guc files
Issue: VIZ-4884
Signed-off-by: Michael H. Nguyen
---
drivers/gpu/drm/i915/i915_reg.h | 68
drivers/gpu/drm/i915/intel_lrc.c | 67 -
From: Alex Dai
Set the firmware version that required by HW. Driver sets required
version according to platform. After firmware is loaded but before
send to HW, the major.minor version is read from CSS header field,
which is 17th DWORD currently. The major version must be same; the
minor version
From: Alex Dai
Now print out Bootrom, uKernel and MIA Core status. The scratch reg
0 & 15 are used for communication between driver and firmware. Their
status is also printed out.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_debugfs.c | 73 +
From: Alex Dai
To enable GuC command submission / scheduling, we need to setup
firmware initializaion properly. i915.enable_guc_scheduling is
introduced to enable / disable GuC submission.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/g
From: Alex Dai
These functions will be used by GuC scheduler.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_lrc.c | 6 +++---
drivers/gpu/drm/i915/intel_lrc.h | 3 +++
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/dri
From: Alex Dai
Allocate a gem obj to hold GuC log data. Also a debugfs interface
(i915_guc_log_dump) is provided to print out the log content.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_debugfs.c| 29 +
drivers/gpu/drm/i915/i915_drv.h|
From: Alex Dai
All gem objects used by GuC are pinned to ggtt space out of range
[0, WOPCM size]. In GuC address space mapping, [0, WPOCM size] is
used internally for its Boot ROM, SRAM etc. Currently this WPOCM
size is 512K. This is done by using of PIN_OFFSET_BIAS.
Issue: VIZ-4884
Signed-off-b
From: Alex Dai
GuC firmware uses the one page after Ring Context as shared data.
However, GuC uses same offset to address this page for all rings.
So we have to allocate same size of lrc context for all rings.
Also, reduce ring buffer size to 4 pages. In GuC, work queue tail is
referenced by 11
From: Sagar Kamble
The firmware loader will use GuC DMA engine to move data from
ggtt to WOPCM. Need to take forcewake before GuC loading.
Issue: VIZ-4884
Change-Id: Ie422fc1e122933b161ff63cab23622197e6bba54
Signed-off-by: Sagar Kamble
---
drivers/gpu/drm/i915/intel_guc_loader.c | 3 +++
1 fil
From: Alex Dai
Add GuC firmware loader. It uses the unified firmware loader to
fetch firmware blob first, then load to hw in driver main thread.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/Makefile | 3 +-
drivers/gpu/drm/i915/i915_dma.c | 6 +
driver
From: Alex Dai
Turn on interrupt steering to route necessary interrupts to GuC.
Issue: VIZ-4884
Signed-off-by: Dave Gordon
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_reg.h| 11 --
drivers/gpu/drm/i915/intel_guc.h | 7
drivers/gpu/drm/i915/intel_guc_s
From: "Michael H. Nguyen"
i915_gem_object_write() is a generic function to copy data from
user memory to gem object.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/i915_gem.c | 30 ++
2 files changed, 33 in
From: Dave Gordon
Factor out the common code of loading firmware into a new file,
leaving only the uC-specific parts in the GuC loaders.
Issue: VIZ-4884
Signed-off-by: Alex Dai
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/Makefile | 3 +
drivers/gpu/drm/i915/intel_uc_loader.
From: Alex Dai
Add overview design of GuC, plus some key points related to
the implementation.
Signed-off-by: Alex Dai
---
Documentation/DocBook/drm.tmpl | 19 +++
1 file changed, 19 insertions(+)
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl
ind
From: Dave Gordon
In order to fully initialise the default contexts, we have to execute
batchbuffer commands on the GPU engines. But we can't do that until any
required firmware has been loaded, which may not be possible during
driver load, because the filesystem(s) containing the firmware may no
From: Alex Dai
Add functions to submit work queue item and ring the door bell.
GuC TLB needs to be invalided if LRC context changes.
Issue: VIZ-4884
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_guc.h | 3 +
drivers/gpu/drm/i915/intel_guc_client.c| 182
On 06/15/2015 01:30 PM, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:23PM +0100, Dave Gordon wrote:
snip
> + * Return true if get a success code from normal boot or RC6 boot
> + */
> +static inline bool i915_guc_get_status(struct drm_i915_private *dev_priv,
> +
On 06/23/2015 04:33 AM, Dave Gordon wrote:
On 17/06/15 13:41, Daniel Vetter wrote:
> On Wed, Jun 17, 2015 at 02:22:19PM +0200, Daniel Vetter wrote:
>> On Wed, Jun 17, 2015 at 09:20:44AM +0100, Dave Gordon wrote:
>>> On 16/06/15 10:24, Chris Wilson wrote:
On Mon, Jun 15, 2015 at 07:36:30PM
On 06/25/2015 07:40 AM, Dave Gordon wrote:
GuC submission is basically execlist submission, but with the GuC
handling the actual writes to the ELSP and the resulting context
switch interrupts. So to prepare a context for submission via the
GuC, we need some of the same functions used in execlist
On 07/06/2015 11:21 AM, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 05:07:31PM +0100, Dave Gordon wrote:
> On 06/07/15 15:14, Daniel Vetter wrote:
> >On Fri, Jul 03, 2015 at 01:30:33PM +0100, Dave Gordon wrote:
> >>Turn on interrupt steering to route necessary interrupts to GuC.
> >>
> >>Issue
On 07/07/2015 02:06 AM, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 05:00:52PM -0700, Yu Dai wrote:
>
>
> On 07/06/2015 11:21 AM, Daniel Vetter wrote:
> >On Mon, Jul 06, 2015 at 05:07:31PM +0100, Dave Gordon wrote:
> >> On 06/07/15 15:14, Daniel Vetter wrote:
> >
On 07/03/2015 07:09 AM, Mika Kuoppala wrote:
Pass around requests to carry context deeper in callchain.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 30 ++
1 file changed, 14 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i91
On 07/07/2015 09:49 AM, Yu Dai wrote:
On 07/03/2015 07:09 AM, Mika Kuoppala wrote:
> Pass around requests to carry context deeper in callchain.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/intel_lrc.c | 30 ++
> 1 file chan
On 07/03/2015 07:09 AM, Mika Kuoppala wrote:
Pass around requests to carry context deeper in callchain.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/dr
From: Alex Dai
The firmware layout changes that now it only has css header +
uCode + RSA signature. Plus, other trivial changes to support
GuC V4.3.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_guc_fwif.h | 11 ---
drivers/gpu/drm/i915/intel_guc_loader.c | 17 ++
From: Alex Dai
If rc6 is enabled, notify GuC so it can do proper forcewake before
command submission.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_guc_submission.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
b/driver
From: Alex Dai
Bit 16 of GuC status indicates resuming from RC6. The LAPIC_DONE
status is a reliable readiness flag only when resuming from RC6.
This fix a racing issue that allocation of doorbell fails whilst
GuC init is not finished.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_guc_
From: Alex Dai
By using information from GuC css header, we can eliminate some
hard code w.r.t size of some components of firmware.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/intel_guc.h| 2 +-
drivers/gpu/drm/i915/intel_guc_fwif.h | 36 +
drivers/gpu/drm/i915/inte
On 09/03/2015 12:36 AM, Jani Nikula wrote:
On Thu, 03 Sep 2015, yu@intel.com wrote:
> From: Alex Dai
>
> By using information from GuC css header, we can eliminate some
> hard code w.r.t size of some components of firmware.
>
> Signed-off-by: Alex Dai
> ---
> drivers/gpu/drm/i915/intel_g
From: Alex Dai
By using information from GuC css header, we can eliminate some
hard code w.r.t size of some components of firmware.
v1: 1) guc_css_header is defined as __packed now
2) Add and correct GuC related topics in kernel/Doc
Signed-off-by: Alex Dai
---
Documentation/DocBook/drm.tm
Jesse,
Will the patch here fix the issue? It should help other cases where
LRC_PPHWSP_PN is referenced on non-execlist / guc platforms.
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 4cc54b3..233a930 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/dr
Agree. The LRC prefix is confusing. Thanks for the patch. -Alex
On 09/10/2015 02:58 PM, Jesse Barnes wrote:
That looks like it would, but I think it's still confusing to reference LRC
state when we haven't initialized execlists at all...
Jesse
On 09/10/2015 02:56 PM, Yu Dai wrot
From: Sagar Arun Kamble
Due to flip interrupts GuC stays awake always and GT does not enter RC6.
Do not route those interrupts to GuC for now.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_guc_loader.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --g
From: Alex Dai
Bit 16 of GuC status indicates resuming from RC6. The LAPIC_DONE
status is a reliable readiness flag only when resuming from RC6.
This fix a racing issue that allocation of doorbell fails whilst
GuC init is not finished.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_guc_
From: Alex Dai
GuC expects two bits for Render and Media domain separately when
driver sends data via host2guc SAMPLE_FORCEWAKE. Bit 0 is for
Render and bit 1 is for Media domain.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_guc_submission.c | 3 ++-
1 file changed, 2 insertions(+), 1
From: Dave Gordon
This is to enable command submission via GuC.
Signed-off-by: Dave Gordon
---
drivers/gpu/drm/i915/i915_params.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_params.c
b/drivers/gpu/drm/i915/i915_params.c
index 05053e2..a509
From: Alex Dai
The first two had been submitted to upstream. They are collected here as a
summry of latest GuC changes.
drm/i915/guc: Fix a bug in GuC status check
drm/i915/guc: Add GuC css header parser
The others are
From: Alex Dai
Add host2guc interfaces to nofigy GuC power state changes when
enter or resume from power saving state.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_drv.c| 1 +
drivers/gpu/drm/i915/i915_gem.c| 1 +
drivers/gpu/drm/i915/i915_guc_submission.c |
From: Alex Dai
By using information from GuC css header, we can eliminate some
hard code w.r.t size of some components of firmware.
v1: 1) guc_css_header is defined as __packed now
2) Add and correct GuC related topics in kernel/Doc
Signed-off-by: Alex Dai
---
Documentation/DocBook/drm.tm
On 09/10/2015 11:16 PM, Kamble, Sagar A wrote:
Hi Alex,
Kindly incorporate changes in this patch in your patch at:
http://lists.freedesktop.org/archives/intel-gfx/2015-September/075668.html
- [PATCH 5/6] drm/i915/guc: Media domain bit needed when notify GuC rc6
state
This is because GuC sampl
From: Alex Dai
By using information from GuC css header, we can eliminate some
hard code w.r.t size of some components of firmware.
v2: Add indent into DOC to make fixed-width format rather than
change the tmpl.
v1: 1) guc_css_header is defined as __packed now
2) Add and correct GuC related
From: Alex Dai
Add host2guc interfaces to nofigy GuC power state changes when
enter or resume from power saving state.
v1: Change to a more flexible way when fill host to GuC scratch
data in order to remove hard coding.
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_drv.c|
From: Alex Dai
GuC expects two bits for Render and Media domain separately when
driver sends data via host2guc SAMPLE_FORCEWAKE. Bit 0 is for
Render and bit 1 is for Media domain.
v1: Add parameters definition to avoid magic value
Signed-off-by: Alex Dai
---
drivers/gpu/drm/i915/i915_guc_subm
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
From: Alex Dai
GuC expects two bits for Render and Media domain separately when
driver sends data via host2guc SAMPLE_FORCEWAKE when full coarse power
gating is enabled. Bit 0 is for Render and bit 1 is for Media domain.
Signed-off-by: Alex Da
Looks fine to me.
Reviewed by: Alex Dai .
On 08/23/2015 05:22 AM, Sagar Arun Kamble wrote:
On BXT, We Observe timeout for forcewake request completion with 2ms polling
period as given here:
[drm:fw_domains_get] ERROR render: timed out waiting for forcewake ack request.
Polling for 50ms is recom
Looks fine to me.
Reviewed by: Alex Dai .
On 08/23/2015 05:22 AM, Sagar Arun Kamble wrote:
Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD
exit.
Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel
On 08/23/2015 05:22 AM, Sagar Arun Kamble wrote:
WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and till SKL E0.
Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_p
Looks good to me.
Reviewed-by: Alex Dai
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
Enable TO mode for RC6 for SKL till D0 and BXT till A0.
Cc: Tom O'Rourke
Cc: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_pm.c | 13 ++---
1 file changed, 10 ins
This one can be discarded and I will amend a fix to my other patch series.
Thanks,
Alex
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
From: Alex Dai
GuC expects two bits for Render and Media domain separately when
driver sends data via host2guc SAMPLE_FORCEWAKE when full coarse power
gatin
Looks good to me.
Reviewed-by: Alex Dai
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD
exit.
Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_
Looks good to me.
Reviewed-by: Alex Dai
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.
v2: Added GT3/GT4 Check.
Change-Id: Ia3c4c16e050c88d3e259f601054875c812d
Looks good to me.
Reviewed-by: Alex Dai
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
It will be usefull to specify w/a that affects only SKL GT3 and GT4.
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/driver
Looks good to me.
Reviewed-by: Alex Dai
On 09/11/2015 09:47 PM, Sagar Arun Kamble wrote:
Cc: Alex Dai
Cc: Tom O'Rourke
Cc: Akash Goel
Signed-off-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_guc_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 4
2 files changed, 5 insertio
101 - 200 of 266 matches
Mail list logo
