From: Sourab Gupta
This patch introduces flags and adds support for having pid output with
the OA reports generated through the RCS commands.
When the stream is opened with pid sample type, the pid information is also
captured through the command stream samples and forwarded along with the
OA
From: Sourab Gupta
The OA reports contain the least significant 32 bits of the gpu timestamp.
This patch enables retrieval of the timestamp field from OA reports, to
forward as 64 bit raw gpu timestamps in the perf samples.
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/i915_drv.h | 1
From: Sourab Gupta
This patch extends the i915 perf framework to handle the perf sample
collection for any given gpu engine. Particularly, the support
for collecting timestamp sample type is added, which can be requested for
any engine.
With this, for RCS, timestamps and OA reports can be
From: Sourab Gupta
This series adds framework for collection of gpu performance metrics
associated with the command stream of a particular engine. These metrics
include OA reports for render stream and timestamps, mmio metrics, etc. for
other gpu engine streams. These metrics are are collected
From: Sourab Gupta
For the drivers to be able to use the cross timestamp framework,
they need the information of current clocksource being used by the
kernel timekeeping. This is needed since the callback given by driver
into the get_device_system_crosststamp(), in order to synchronously read
From: Sourab Gupta
This patch adds support for opening multiple concurrent perf streams for
different gpu engines, while having the restriction to open only a single
stream open for a particular gpu engine.
This enables userspace client to open multiple streams, one per engine,
at any time to
From: Sourab Gupta
This patch adds support for capturing MMIO register values through
i915 perf interface.
The userspace can request upto 8 MMIO register values to be dumped.
The addresses of these registers can be passed through the corresponding
property 'value' field while opening
From: Sourab Gupta
Currently, we have the ability to only forward the GPU timestamps in the
samples (which are generated via OA reports or PIPE_CONTROL commands
inserted in the ring). This limits the ability to correlate these samples
with the system events. If we scale the GPU timestamps
On Thu, 2017-03-16 at 00:49 -0700, Chris Wilson wrote:
> On Thu, Mar 16, 2017 at 11:50:06AM +0530, sourab.gu...@intel.com wrote:
> > From: Sourab Gupta
> >
> > This patch extends the i915 perf framework to handle the perf sample
> > collection for any given gpu engine
On Thu, 2017-03-16 at 01:10 -0700, Chris Wilson wrote:
> On Thu, Mar 16, 2017 at 11:44:10AM +0530, sourab.gu...@intel.com wrote:
> > @@ -3593,6 +3670,7 @@ void i915_oa_init_reg_state(struct intel_engine_cs
> > *engine,
> > void i915_oa_update_reg_state(struct intel_engine_cs *engine,
> >
On Thu, 2017-03-16 at 01:31 -0700, Chris Wilson wrote:
> On Thu, Mar 16, 2017 at 11:44:10AM +0530, sourab.gu...@intel.com wrote:
> > +static void i915_perf_command_stream_hook_oa(struct i915_perf_stream
> > *stream,
> > + struct drm_i915_gem_request *request)
> >
On Thu, 2017-03-16 at 02:03 -0700, Chris Wilson wrote:
> On Thu, Mar 16, 2017 at 02:24:55PM +0530, sourab gupta wrote:
> > On Thu, 2017-03-16 at 01:10 -0700, Chris Wilson wrote:
> > > On Thu, Mar 16, 2017 at 11:44:10AM +0530, sourab.gu...@intel.com wrote:
> > > &
On Thu, 2017-03-16 at 03:09 -0700, Chris Wilson wrote:
> On Thu, Mar 16, 2017 at 03:22:03PM +0530, sourab gupta wrote:
> > On Thu, 2017-03-16 at 02:03 -0700, Chris Wilson wrote:
> > > On Thu, Mar 16, 2017 at 02:24:55PM +0530, sourab gupta wrote:
> > > > On Thu, 20
On Thu, 2017-03-16 at 05:59 -0700, Robert Bragg wrote:
> On Thu, Mar 16, 2017 at 6:14 AM, wrote:
> > From: Sourab Gupta
> >
> > This series adds framework for collection of OA reports associated with the
> > render command stream, which are collected ar
e. Also WA added for full Gen7.
Signed-off-by: Sourab Gupta
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/i915_gem_context.c | 55 +++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_ringbuffer.c | 9 ++
drivers/gpu/drm/i915/intel_ri
From: Sourab Gupta
This patch is in continuation of and is dependent on earlier patch
series to 'reduce the time for which device mutex is kept locked'.
(http://lists.freedesktop.org/archives/intel-gfx/2014-May/044596.html)
This patch aims to reduce the allocation time of pages fro
From: Sourab Gupta
Using MMIO based flips on Gen5+ for Media power well residency optimization.
The blitter ring is currently being used just for command streamer based
flip calls. For pure 3D workloads, with MMIO flips, there will be no use
of blitter ring and this will ensure the 100
Reviewed the patch. Looks good.
Reviewed-by: "Sourab Gupta "
On Thu, May 15, 2014 at 8:16 PM, akash goel wrote:
>
>
> Reviewed the patch & it looks fine.
>
> Reviewed-by: "Akash Goel "
> On Tue, Apr 29, 2014 at 4:05 PM, wrote:
>
>> From: Vil
viewed-by: "Akash Goel "
>
>
> Reviewed the patch and looks fine. You can add my r-b tag:
Reviewed-by: "Sourab Gupta "
On Tue, Apr 29, 2014 at 4:05 PM, wrote:
>
>> From: Ville Syrjälä
>>
>> In interlaced modes, the pixel counter counts all pixels,
>>
+ * Summary:
> + * - most events happen at the start of horizontal sync
> + * - frame start happens at the start of horizontal blank, 1-4 lines
> + * (depending on PIPECONF settings) after the start of vblank
> + * - gen3/4 pixel and frame counter are synchronized with the start
> + *
have enough info about the initial scanline counter values for
HSW+ and gen2. Otherwise, you can add my r-b tag
Reviewed-by: "Sourab Gupta "
>
On Thu, May 15, 2014 at 10:53 PM, wrote:
>
>> From: Ville Syrjälä
>>
>> On gen2 the scanline counter behaves a bi
From: Sourab Gupta
Using MMIO based flips on Gen5+ for Media power well residency optimization.
The blitter ring is currently being used just for command streamer based
flip calls. For pure 3D workloads, with MMIO flips, there will be no use
of blitter ring and this will ensure the 100
From: Sourab Gupta
Using MMIO based flips for Media power well residency optimization.
The blitter ring is currently being used just for command streamer based
flip calls. For pure 3D workloads, with MMIO flips, there will be no use
of blitter ring and this will ensure the 100% residency for
From: Sourab Gupta
This patch fixes the race condition between flip done interrupt
from set base and mmio based page flip.
This patch is dependent on
http://lists.freedesktop.org/archives/intel-gfx/2014-April/043761.html
Also, for the details of the race condition please refer to the mentioned
From: Sourab Gupta
This patch is for using mmio flips by default on VLV.
The module parameter controlling use of MMIO flips allows us to
control the default behaviour, which is set true for VLV and false
elsewhere.
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/i915_params.c | 5
From: Sourab Gupta
Using MMIO based flips on Gen5+ for Media power well residency optimization.
The blitter ring is currently being used just for command streamer based
flip calls. For pure 3D workloads, with MMIO flips, there will be no use
of blitter ring and this will ensure the 100
Reviewed the code. Everything looks good, so
Reviewed-by: Sourab Gupta
On Wed, May 21, 2014 at 6:09 AM, Rodrigo Vivi wrote:
> needs a small rebase but everything looks good for me so
> Reviewed-by: Rodrigo Vivi
>
>
> On Tue, Apr 15, 2014 at 11:41 AM, wrote:
>
>
From: Sourab Gupta
This patch series replaces Blitter ring based flips with MMIO based flips.
This is useful for Media power well residency optimization. These may be
enabled on architectures where Render and Blitter engines reside in different
power wells.
The blitter ring is currently being
From: Sourab Gupta
Using MMIO based flips on Gen5+. The MMIO flips are useful for the Media power
well residency optimization. These maybe enabled on architectures where
Render and Blitter engines reside in different power wells.
The blitter ring is currently being used just for command streamer
From: Sourab Gupta
This patch fixes the race condition between flip done interrupt
from set base and mmio based page flip.
This patch is dependent on
http://lists.freedesktop.org/archives/intel-gfx/2014-April/043761.html
Also, for the details of the race condition please refer to the mentioned
From: Sourab Gupta
This patch is for using mmio flips by default on VLV.
The module parameter controlling use of MMIO flips allows us to
control the default behaviour, which is set true for VLV and false
elsewhere.
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/i915_params.c | 5
From: Sourab Gupta
This patch series replaces Blitter ring based flips with MMIO based flips.
This is useful for Media power well residency optimization. These may be
enabled on architectures where Render and Blitter engines reside in different
power wells.
The blitter ring is currently being
From: Sourab Gupta
This patch is for using mmio flips by default on VLV.
The module parameter controlling use of MMIO flips allows us to
control the default behaviour, which is set true for VLV and false
elsewhere.
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/i915_params.c | 5
From: Sourab Gupta
Using MMIO based flips on Gen5+. The MMIO flips are useful for the Media power
well residency optimization. These maybe enabled on architectures where
Render and Blitter engines reside in different power wells.
The blitter ring is currently being used just for command streamer
From: Sourab Gupta
This patch series enables the framework for using MMIO flips in place of
Blitter ring based flips.
This is useful for Media power well residency optimization. These may be
enabled on architectures where Render and Blitter engines reside in different
power wells.
The blitter
From: Sourab Gupta
This patch enables the framework for using MMIO based flip calls,
in contrast with the CS based flip calls which are being used currently.
MMIO based flip calls can be enabled on architectures where
Render and Blitter engines reside in different power wells. The
decision to
From: Sourab Gupta
This patch enhances the module parameter, 'use_mmio_flip' which
enables MMIO flips, to make it tristate. The values being-
0: Force CS flip
1: Force MMIO flip (Gen5+)
>1: Driver discretion is applied while selecting CS vs MMIO flip.
For Valleyview, this dri
From: Sourab Gupta
This patch enables the selection of MMIO flip vs CS flip at
page flip time. Earlier, this selection was done only at the
init time, so, once .queue_flip was set, it was used forever.
This patch enables this selection of flip mechanism at a time
when page flips is being issued
From: Sourab Gupta
This patch enables the framework for using MMIO based flip calls,
in contrast with the CS based flip calls which are being used currently.
MMIO based flip calls can be enabled on architectures where
Render and Blitter engines reside in different power wells. The
decision to
From: Sourab Gupta
This patch enables the framework for using MMIO based flip calls,
in contrast with the CS based flip calls which are being used currently.
MMIO based flip calls can be enabled on architectures where
Render and Blitter engines reside in different power wells. The
decision to
time
of individual power wells in C6 state.
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 53 -
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +--
2 files changed, 28 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915
From: Sourab Gupta
The testcases test the buffer objects created with the cpu_map_not_needed flag.
These are used to test the allocation, copy, truncation and non-cpu mappable
nature
of the buffer objects created with this flag.
Signed-off-by: Sourab Gupta
---
tests/Makefile.sources |1
From: Sourab Gupta
Renamed the 'pad' field to 'flags' of gem_create ioctl.
Also, added a new flag I915_CPU_MAP_NOT_NEEDED which can be passed with
gem_create ioctl.
Signed-off-by: Sourab Gupta
Signed-off-by: Akash Goel
---
include/drm/i915_drm.h |3 ++-
1 file c
From: Sourab Gupta
Added a new libdrm flag and a flag in the gem_create ioctl. This is used to
indicate
that cpu mapping is not required for the buffer object.
Sourab Gupta (2):
include/drm: Rename the 'pad' field to 'flags' of gem_create ioctl
int
From: Sourab Gupta
Added a new flag 'BO_ALLOC_CPU_MAP_NOT_NEEDED' flag which can be passed
to bo_alloc_tiled function. This is used to indicate that cpu mapping is
not required for the buffer object. This info will be passed to driver
in the gem_create ioctl.
Signed-off-by: So
From: Sourab Gupta
On VLV, 64MB of system memory was being reserved for stolen
area, but ~8MB of it was being utilized.
For the buffer objects which are not cpu mappable, we can allocate
the space from stolen memory, thus increasing the utilization of stolen
memory area.
Testcase: igt
From: Sourab Gupta
Adding the truncation logic for buffer objects with backing storage
from stolen memory. The objects will be truncated when user marks them
as purgeable and they are part of the inactive list.
Testcase: igt/gem_stolen_mem
Signed-off-by: Sourab Gupta
Signed-off-by: Akash
From: Sourab Gupta
Adding the flag 'I915_CPU_MAP_NOT_NEEDED' to gem_create ioctl.
This is to indicate the driver that direct cpu access to this
buffer object is not needed and hence Driver can opt to use Stolen
area as a backing store for it.
Testcase: igt/gem_stolen_mem
Signed-off-
From: Sourab Gupta
These patches are mainly for increasing the utilization
of stolen memory area on VLV.
Although similar patches were submitted earlier, but this time the
allocation from stolen area will be done based on user's input.
We have now exposed a new libdrm flag which user ca
From: Sourab Gupta
Adding the flag 'I915_CPU_MAP_NOT_NEEDED' to gem_create ioctl.
This is to indicate the driver that direct cpu access to this
buffer object is not needed and hence Driver can opt to use Stolen
area as a backing store for it. When this flag is set, try to
allocate t
From: Sourab Gupta
These patches are mainly for increasing the utilization
of stolen memory area on VLV.
Although similar patches were submitted earlier, this time truncation
is handled based on Chris and Daniel's input. Chris's patch handles
the truncation of purgeable stolen obje
From: Sourab Gupta
While we are freeing the purgeable stolen object, the memory node has
to be freed so as to make space for the new object.
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/i915_gem_stolen.c |4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers
From: Chris Wilson
If we run out of stolen memory when trying to allocate an object,
see if we can reap enough purgeable objects to free up enough contiguous
free space for the allocation. This is in principle very much like
evicting objects to free up enough contiguous space in the vma when
bind
From: Sourab Gupta
Using MMIO based flips on VLV for Media power well residency optimization.
The blitter ring is currently being used just for command streamer based
flip calls. For pure 3D workloads, with MMIO flips, there will be no use
of blitter ring and this will ensure the 100% residency
From: Sourab Gupta
Using MMIO based flips on VLV for Media power well residency optimization.
The blitter ring is currently being used just for command streamer based
flip calls. For pure 3D workloads, with MMIO flips, there will be no use
of blitter ring and this will ensure the 100% residency
ned-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 4eb3e06..2cc7ed5 100644
--- a/drivers/gp
From: Akash Goel
This patch Enables the bit for TLB invalidate in GFX Mode register.
According to bspec, When enabled this bit limits the invalidation
of the TLB only to batch buffer boundaries, to pipe_control
commands which have the TLB invalidation bit set and sync flushes.
If disabled, the
From: Akash Goel
Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for
VLV platform as it is not required.
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer
From: Akash Goel
In Valleyview, Operational flush cannot be enabled on
BWG A0 [Errata BWT006]
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/drivers
From: Akash Goel
For VLV, disabling L3 clock gating- MMIO 940c[25] = 1
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/intel_pm.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915
after every MI_SET_CONTEXT and after any
PIPELINE_SELECT that is enabling 3D mode".
v2: Modified the WA comment. (Ville)
v3: Added the vlv identifier with the WA name
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/i915_gem_cont
TLB caches are flushed for every full flush of
the pipeline.
v2: Explicitly enabling TLB invalidate bit instead of assuming
default 1 (Chris Wilson)
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 15 +++
1 file changed, 11
From: Sourab Gupta
Using MMIO based flips on VLV for Media power well residency optimization.
The blitter ring is currently being used just for command streamer based
flip calls. For pure 3D workloads, with MMIO flips, there will be no use
of blitter ring and this will ensure the 100% residency
From: Sourab Gupta
This patch series adds rendering specific HW workarounds for VLV platform.
These patches leads to stable behavior on VLV, especially
when playing 3D Apps, benchmarks.
Though, the patch set was submitter earlier, this new patch set is initiating
a clean thread. We have
From: Akash Goel
For VLV, disabling L3 clock gating- MMIO 940c[25] = 1
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/intel_pm.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915
From: Akash Goel
In Valleyview, Operational flush cannot be enabled on
BWG A0 [Errata BWT006]
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_pm.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/drivers
after every MI_SET_CONTEXT and after any
PIPELINE_SELECT that is enabling 3D mode".
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/i915_gem_context.c | 65 -
drivers/gpu/drm/i915/i915_reg.h | 3 ++
drivers/gp
From: Akash Goel
Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
Store data commands.
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/intel_ringbuf
From: Akash Goel
Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for
VLV platform as it is not required.
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer
disabled, the TLB caches are flushed for every full flush of
the pipeline.
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm
disabled, the TLB caches are flushed for every full flush of
the pipeline.
Tested only on vlv platform. Chris has tested on ivb and hsw
platforms.
v2: Adding the explicit enabling of this bit for all Gen7 platforms
instead of only vlv (Chris)
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
From: Sourab Gupta
This patch series adds rendering specific HW workarounds for VLV platform.
These patches leads to stable behavior on VLV, especially
when playing 3D Apps, benchmarks.
This patch series consolidates the earlier patch set in a clean thread
and adds the in-patch changelogs
rked based on Chris' comments (WA moved to gen7 ring flush func,
sending 6 dwords instead of 8)
Signed-off-by: Sourab Gupta
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drive
after every MI_SET_CONTEXT and after any
PIPELINE_SELECT that is enabling 3D mode".
v2: Modified the WA comment. (Ville)
v3: Added the vlv identifier with the WA name
v4: Check removed for scratch page initialization. (Chris/Daniel)
Signed-off-by: Sourab Gupta
Signed-off-by: Akash Goel
---
d
destroyed.
v2: Modifying the comments and the patch commit message (Chris)
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/intel_pm.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915
From: Akash Goel
In Valleyview, Operational flush cannot be enabled on
BWG A0 [Errata BWT006]
v2: Corrected the code regarding the wrong usage of
MASKED_BIT_DISABLE (Chris)
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm
From: Akash Goel
Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for
VLV platform as it is not required.
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer
From: Akash Goel
Removing the VS_TIMER_DISPATCH bit enable for MI MODE reg for
Gen7 platform as it is not required.
v2: Enhancing the scope of the patch to full Gen7 (Chris)
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
Tested-by: Chris Wilson # ivb, hsw -Chris
---
drivers/gpu/drm
: Enhancing the scope of WA to gen6, gen7. Having a common WA func being
called from gen6, gen7 flush functions. (Ville)
Signed-off-by: Sourab Gupta
Signed-off-by: Akash Goel
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 52 +
1 file changed, 52 insertions(+)
diff
8) (Chris)
v5: Enhancing the scope of WA to gen6, gen7. Having a common WA func being
called from gen6, gen7 flush functions. (Ville)
v6: WA is applicable only to render ring, earlier put for all rings in v5.
(Chris)
Signed-off-by: Sourab Gupta
Signed-off-by: Akash Goel
---
drive
of the patch to full Gen7 (Chris)
v3: Modifying the WA condition to the cover the applicable platforms,
and adding the WA name in comments. (Ville)
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
Tested-by: Chris Wilson # ivb, hsw -Chris
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++-
usage of
MASKED_BIT_DISABLE (Chris)
v3: Enhancing the scope of WA to Gen4+ platforms except BDW (Ville)
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 15 +++
2 files changed, 16 insertions(+)
diff
usage of
MASKED_BIT_DISABLE (Chris)
v3: Enhancing the scope of WA to Gen4+ platforms except BDW (Ville)
v4: Adding WA for g4x, crestline, broadwater (Ville)
Signed-off-by: Akash Goel
Signed-off-by: Sourab Gupta
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm
| 77 ++
> drivers/gpu/drm/i915/intel_display.c | 2 +
> drivers/gpu/drm/i915/intel_drv.h | 3 +
> drivers/gpu/drm/i915/intel_sprite.c | 195
> ++++---
> 5 files changed, 306 insertions(+), 108 deletions(-)
>
> Went through the patc
From: Sourab Gupta
This patch series introduces a new gem create ioctl for user specified
placement.
Despite being a unified memory architecture (UMA) some bits of memory
are more equal than others. In particular we have the thorny issue of
stolen memory, memory stolen from the system by the
From: Chris Wilson
This patch adds support for clearing buffer objects via blitter
engines. This is particularly useful for clearing out the memory
from stolen region.
testcase: igt/gem_create2
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915
From: Chris Wilson
If we run out of stolen memory when trying to allocate an object, see if
we can reap enough purgeable objects to free up enough contiguous free
space for the allocation. This is in principle very much like evicting
objects to free up enough contiguous space in the vma when bind
Chris Wilson
Signed-off-by: Sourab Gupta
---
drivers/gpu/drm/i915/i915_dma.c| 11 +-
drivers/gpu/drm/i915/i915_drv.h| 15 ++-
drivers/gpu/drm/i915/i915_gem.c| 208 ++---
drivers/gpu/drm/i915/i915_gem_tiling.c | 106 +
include/uap
From: Sourab Gupta
This patch adds the testcases for verifying the new gem_create2
ioctl. By means of this ioctl, we can specify number of parameters
during object creation time such as placement, cache domains,
caching, madvise, tiling etc.
These testcases include functional tests and interface
From: Sourab Gupta
This patch series add the bufmgr interfaces for exposing the
create2 ioctl.
By means of this ioctl, we can specify number of parameters
during object creation time such as placement, cache domains,
caching, madvise, tiling etc.
Signed-off-by: Sourab Gupta
---
include/drm
From: Sourab Gupta
This patch add the cacheing logic for the buffer objects created
using create2 ioctl. This cacheing logic is in principle similar
the cachecing employed in the earlier clear ioctl.
The cacheing is not employed if object is created in stolen region
or if the offset is specified
From: Sourab Gupta
This patch series add the bufmgr interfaces for exposing the
create2 ioctl.
By means of this ioctl, we can specify number of parameters
during object creation time such as placement, cache domains,
caching, madvise, tiling etc.
Sourab Gupta (2):
intel: Adding bufmgr
From: Chris Wilson
This patch adds support for clearing buffer objects via blitter
engines. This is particularly useful for clearing out the memory
from stolen region.
testcase: igt/gem_create2
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/
From: Chris Wilson
If we run out of stolen memory when trying to allocate an object, see if
we can reap enough purgeable objects to free up enough contiguous free
space for the allocation. This is in principle very much like evicting
objects to free up enough contiguous space in the vma when bind
From: Deepak S
On Gen8, COLOR BLT commands are different. Add gen8 specific command to clearing
buffer objects via blitter engines.
Signed-off-by: Deepak S
---
drivers/gpu/drm/i915/i915_gem_exec.c | 39 +++-
1 file changed, 29 insertions(+), 10 deletions(-)
dif
From: Chris Wilson
Despite being a unified memory architecture (UMA) some bits of memory
are more equal than others. In particular we have the thorny issue of
stolen memory, memory stolen from the system by the BIOS and reserved
for igfx use. Stolen memory is required for some functions of the GP
From: Sourab Gupta
This patch series introduces a new gem create ioctl for user specified
placement.
Despite being a unified memory architecture (UMA) some bits of memory
are more equal than others. In particular we have the thorny issue of
stolen memory, memory stolen from the system by the
From: Sourab Gupta
Currently the Graphics Driver provides an interface through which
one can get a snapshot of the overall Graphics memory consumption.
Also there is an interface available, which provides information
about the several memory related attributes of every single Graphics
buffer
From: Sourab Gupta
This patch introduces the data structures for capturing asynchronous OA
snapshots
The data captured will be organized into nodes. Each node has the field for OA
report alongwith metadata information such as ctx_id, pid, etc. The metadata
information can be extended to
From: Sourab Gupta
Currently the context ids are specific to a drm file instance, as opposed to
being globally unique. There are some usecases, which may require globally
unique context ids. For e.g. a system level GPU profiler tool may lean upon
the context ids to associate the performance
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