From: Akash Goel <akash.g...@intel.com>
Added a new rendering specific Workaround 'WaTlbInvalidateStoreDataBefore'.
In this WA, before pipecontrol with TLB invalidate set, need to add 2 MI
Store data commands.
v2: Modified the WA comment (Ville)
v3: Added the vlv identifier with WA name (Damien)
v4: Reworked based on Chris' comments (WA moved to gen7 ring flush func,
sending 6 dwords instead of 8)
Signed-off-by: Sourab Gupta <sourab.gu...@intel.com>
Signed-off-by: Akash Goel <akash.g...@intel.com>
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 87d1a2d..75cac4e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -309,6 +309,29 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring,
u32 scratch_addr = ring->scratch.gtt_offset + 128;
int ret;
+ if (invalidate_domains && IS_VALLEYVIEW(ring->dev)) {
+ /*
+ * WaTlbInvalidateStoreDataBefore:vlv
+ * This workaround is applicable in case the flush call has
+ * arrived in context of invalidate_all_caches function.
+ * Before pipecontrol with TLB invalidate set, need 2 store
+ * data commands (such as MI_STORE_DATA_IMM or
MI_STORE_DATA_INDEX)
+ * Without this, hardware cannot guarantee the command after the
+ * PIPE_CONTROL with TLB inv will not use the old TLB values.
+ * FIXME: should apply to snb, ivb
+ */
+ int i;
+ ret = intel_ring_begin(ring, 3 * 2);
+ if (ret)
+ return ret;
+ for (i = 0; i < 2; i++) {
+ intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
+ intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR);
+ intel_ring_emit(ring, 0);
+ }
+ intel_ring_advance(ring);
+ }
+
/*
* Ensure that any following seqno writes only happen when the render
* cache is indeed flushed.
--
1.8.5.1
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