Looks good to me.
Reviewed-by: Caz Yokoyama
-caz
On Tue, 2021-10-12 at 15:12 -0700, Matt Roper wrote:
> The I915_TILING_* values in our uapi header are intended solely for
> use
> with the old get_tiling/set_tiling ioctls that operate on hardware
> de-tiling fences; all other uapi c
On Tue, 2021-10-19 at 17:23 -0700, José Roberto de Souza wrote:
> Adding a structure to standardize access to IP versioning as future
> platforms will have this information populated at runtime.
>
> The constant platform display version is not using this new struct
> but
> the runtime variant will
Looks good to me.
Reviewed-by: Caz Yokoyama
-caz
On Tue, 2021-10-19 at 17:23 -0700, José Roberto de Souza wrote:
> As now graphics and media can have different steppings this patch is
> renaming all _GT_STEP macros to _GRAPHICS_STEP.
>
> Future platforms will properly choose between
Looks good to me.
Reviewed-by: Caz Yokoyama
-caz
On Tue, 2021-10-19 at 17:35 -0700, José Roberto de Souza wrote:
> This power domain to disable DC states will be used in places outside
> of DPLL, so making the name more generic.
>
> Cc: Radhakrishna Sripada
> Cc: Imre Deak
On Tue, 2021-10-19 at 17:35 -0700, José Roberto de Souza wrote:
> Right now the only user of psr_pause/resume is intel_cdclk but
> additional users will be added in the future and we may need
> do reference counting for PSR pause and resume, for now only adding a
do -> to do?
> warn_on so this cas
On Wed, 2021-10-20 at 19:19 +, Souza, Jose wrote:
> On Wed, 2021-10-20 at 15:00 +0000, Yokoyama, Caz wrote:
> > On Tue, 2021-10-19 at 17:23 -0700, José Roberto de Souza wrote:
> > > Adding a structure to standardize access to IP versioning as
> > > future
>
Reviewed-by: Caz Yokoyama
-caz
On Thu, 2021-10-28 at 21:08 +, Souza, Jose wrote:
> Reviewed-by: Caz Yokoyama
From: Caz Yokoyama
Do not overwrite registers that don't need to change from default
value to 0.
bspec 49213
Cc: Radhakrishna Sripada
Cc: José Roberto de Souza
Cc: Matt Roper
Signed-off-by: Caz Yokoyama
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +
1 file changed, 9 i
On Fri, 2021-09-17 at 10:08 -0700, Matt Roper wrote:
> From: Venkata Sandeep Dhanalakota
>
> Support for multiple GT's within a single i915 device will be
> arriving
> soon. Since each GT may have its own fusing and require different
> workarounds, we need to make the GT workaround functions and
On Fri, 2021-07-23 at 10:42 -0700, Matt Roper wrote:
> During a rebase the parameters were partially renamed, but not
> completely. Since the subsequent patches that start using this macro
> haven't landed on an upstream tree yet this didn't cause a build
> failure.
>
> Fixes: 086df54e20be ("drm/
On Tue, 2021-07-27 at 11:38 -0700, Matt Roper wrote:
> On Tue, Jul 27, 2021 at 11:34:28AM -0700, Yokoyama, Caz wrote:
> > On Fri, 2021-07-23 at 10:42 -0700, Matt Roper wrote:
> > > During a rebase the parameters were partially renamed, but not
> > > completely. Since
On Fri, 2021-07-23 at 10:42 -0700, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> Xe_HP is more modular then its predecessors and as a consequence it
then -> than
> has
> more types of replicated registers. As with l3bank regions on
> previous
> platforms, we may need to explicitly re-st
Reviewed-by: Caz Yokoyama
-caz
On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> For historical reasons, the GT forcewake domain used to be referred
> to
> as the "blitter" domain; that name is no longer accurate since the GT
> domain contains a lot of additional regis
Reviewed-by: Caz Yokoyama
-caz
On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> The forcewake read logic is identical between gen11 and gen12, only
> the
> forcewake table data (which is tracked separately) differs; there's
> no
> need to generate a separate set of
On Thu, 2021-07-29 at 08:21 -0700, Matt Roper wrote:
> Rather than defining our shadow tables as a list of individual
> registers, provide them as a list of register ranges; we'll have some
> ranges of multiple registers being added soon (and we already have a
> couple adjacent registers that we ca
Reviewed-by: az Yokoyama
-caz
On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> The list of shadowed registers on XeHP is identical to the set for
> earlier gen12 platforms, with additional ranges added for the new VCS
> and VECS engines. Since those register ranges were re
Reviewed-by: Caz Yokoyama
-caz
On Thu, 2021-07-29 at 14:59 -0700, Matt Roper wrote:
> On Thu, Jul 29, 2021 at 02:55:17PM -0700, Yokoyama, Caz wrote:
> > On Thu, 2021-07-29 at 08:21 -0700, Matt Roper wrote:
> > > Rather than defining our shadow tables as a list of individu
Reviewed-by: Caz Yokoyama
-caz
On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> The bspec lists many shadowed registers (i.e., registers for which we
> don't need to grab forcewake when writing) that we weren't tracking
> in
> the driver. Although we may not act
Reviewed-by: Caz Yokoyama
-caz
On Wed, 2021-07-28 at 22:41 -0700, Matt Roper wrote:
> The bspec lists many shadowed registers (i.e., registers for which we
> don't need to grab forcewake when writing) that we weren't tracking
> in
> the driver. Although we may not act
Reviewed-by: Caz Yokoyama
-caz
On Thu, 2021-08-05 at 09:36 -0700, Matt Roper wrote:
> From: Akeem G Abodunrin
>
> New LRI register offsets were introduced for DG2, this patch adds
> those extra registers, and create new register table for setting
> offsets
> to compare
On Fri, 2021-09-10 at 10:52 -0700, Lucas De Marchi wrote:
> On Wed, Sep 08, 2021 at 05:49:40PM -0700, Lucas De Marchi wrote:
> > We shouldn't be using debugfs_ namespace for this functionality.
> > Rename
> > debugfs_gt_pm.[ch] to intel_gt_pm_debugfs.[ch] and then make
> > functions, defines and st
On Fri, 2021-09-10 at 14:52 -0700, Lucas De Marchi wrote:
> On Fri, Sep 10, 2021 at 09:14:37PM +0000, Yokoyama, Caz wrote:
> > On Fri, 2021-09-10 at 10:52 -0700, Lucas De Marchi wrote:
> > > On Wed, Sep 08, 2021 at 05:49:40PM -0700, Lucas De Marchi wrote:
> > > >
Reviewed-by: Caz Yokoyama
-caz
On Tue, 2021-07-13 at 20:15 -0700, Matt Roper wrote:
> DG2 supports compute DSS and has the same maximum number of DSS and
> EU
> as XeHP SDV.
>
> Signed-off-by: Matt Roper
> ---
> drivers/gpu/drm/i915/gt/intel_sseu.c | 2 +-
> 1 file ch
Reviewed-by: Caz Yokoyama
-caz
On Tue, 2021-07-13 at 20:15 -0700, Matt Roper wrote:
> Due to the removal of legacy slices and the transition to a
> gslice/cslice/mslice/etc. design, we'll internally store all DSS
> under
> "slice0."
>
> Signed-off-by: Matt Rop
Please disregard. Wrong address. Sorry.
-caz
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Caz Yokoyama
Sent: Tuesday, March 19, 2019 09:25
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v4 1/1] i915_pm_rpm: remove
gem-e
: I0d3732a202fef90d192fb84baf8275eeadb59c02
Signed-off-by: Yokoyama, Caz
---
drivers/gpu/drm/i915/selftests/intel_lrc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_lrc.c
b/drivers/gpu/drm/i915/selftests/intel_lrc.c
index d61520ea03c1..16befd2a74c6 100644
On Thu, 2021-12-16 at 19:41 -0800, Madhumitha Tolakanahalli Pradeep
wrote:
> Replace GEN with DISPLAY_VER, in line with the naming
> convention
> followed in the i915 driver code.
>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep <
> madhumitha.tolakanahalli.prad...@intel.com>
> ---
> drivers/g
Reviewed-by: Caz Yokoyama
-caz
On Thu, 2021-12-23 at 03:18 +, Tolakanahalli Pradeep, Madhumitha
wrote:
> On Fri, 2021-12-17 at 21:37 +0000, Yokoyama, Caz wrote:
> > On Thu, 2021-12-16 at 19:41 -0800, Madhumitha Tolakanahalli Pradeep
> > wrote:
> > > Replace GEN with D
Reviewed-by: Caz Yokoyama
-caz
On Fri, 2021-11-05 at 17:37 -0700, Radhakrishna Sripada wrote:
> The earlier update to BW formulae broke ADL-P. Include
> GEN13 to use TGL path for BW parameters.
>
> Fixes: c64a9a7c05be drm/i915: Update memory bandwidth formulae
> Cc: Matt Roper
Reviewed-by: Caz Yokoyama
-caz
On Tue, 2022-02-15 at 13:45 -0800, Matt Roper wrote:
> DG2 hardware will start showing up in CI shortly; let's make sure
> it's
> recognized by the driver.
>
> Bspec: 44477
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Joo
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