Hi Rodrigo,
We will use HuC on BXT.
Thanks
Haihao
> vaapi-intel-driver, the userspace component here is only using HuC
> for
> SKL for now, so I believe this one will be on hold for now, right?
>
>
>
> On Wed, 2016-07-06 at 15:24 +0100, Peter Antoine wrote:
> > This patch adds the HuC Loadin
rom: Thierry, Michel
> > Sent: Thursday, June 23, 2016 3:48 AM
> > To: Antoine, Peter ; Xiang, Haihao
> > ; daniel.vet...@ffwll.ch
> > Cc: Kelley, Sean V ; intel-
> > g...@lists.freedesktop.org; Li, Lawrence T
> > ; Vivi,
> > Rodrigo
> > Subject: Re: [Inte
On Tue, 2016-08-30 at 08:59 +0800, Randy Li wrote:
> Hi all:
> When I just doing the driver for us chip, we would request the
> Nalu
> header present in the data to be process. But I found the data be
> Rendered to with type VASliceDataBufferType is removed the Nalu start
> code. Is there any
Hi Peter,
Besides debugfs, could you add a IOCTL to check HuC loading status?
Userspace media driver needs to advertise the features based on HuC to
user.
Thanks
Haihao
> From: Alex Dai
>
> Add debugfs entry for HuC loading status check.
>
> Signed-off-by: Alex Dai
> Signed-off-by: Peter A
This interface is the same as drm_intel_bo_alloc except the allocated
size isn't rounded up, so it bypasses the cache bucket.
The size of the BO created by drm_intel_bo_alloc for a 1920x800,4:2:0 YUV
planar surface is 4M, it is about 2.2M if using drm_intel_bo_alloc_direct.
Signed-off-by:
On Thu, 2010-05-27 at 04:52 +0800, Eric Anholt wrote:
> On Tue, 25 May 2010 13:06:50 +0800, "Xiang, Haihao"
> wrote:
> > This interface is the same as drm_intel_bo_alloc except the allocated
> > size isn't rounded up, so it bypasses the cache bucket.
>
On Fri, 2010-05-28 at 22:04 +0800, Daniel Vetter wrote:
> On Tue, May 25, 2010 at 01:06:50PM +0800, Xiang, Haihao wrote:
> > This interface is the same as drm_intel_bo_alloc except the allocated
> > size isn't rounded up, so it bypasses the cache bucket.
> >
> &g
On Sat, 2010-06-05 at 08:16 +0800, Eric Anholt wrote:
> We had two cases recently where the rounding to powers of two hurt
> badly: 4:2:0 YUV HD video frames would round up from 2.2MB to 4MB,
> Urban Terror was hitting aperture size limitations. Mipmap trees for
> power of two sizes will land righ
On Mon, 2010-06-07 at 10:28 +0800, Xiang, Haihao wrote:
> On Sat, 2010-06-05 at 08:16 +0800, Eric Anholt wrote:
> > We had two cases recently where the rounding to powers of two hurt
> > badly: 4:2:0 YUV HD video frames would round up from 2.2MB to 4MB,
> > Urban Terror was
_CACHE &&
> $9 != GEN7_SFID_DATAPORT_DATA_CACHE &&
> $9 != HSW_SFID_DATAPORT_DATA_CACHE1) {
> error (&@9, "error: wrong cache type\n");
It is OK for me
Reviewed-by: Xiang, Haihao
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Thu, 2014-03-13 at 16:38 -0400, mengdong@intel.com wrote:
> From: Mengdong Lin
>
> This patch fixes the reversed CTS/M value index when dumping the
> 'audio M/CTS programing enable' register.
>
> Signed-off-by: Mengdong Lin
>
> diff --git a/tools/intel_audio_dump.c b/tools/intel_audio_
On Tue, 2013-11-26 at 20:35 +0100, Daniel Vetter wrote:
> Hi Brad,
>
> On Tue, Nov 26, 2013 at 08:51:17AM -0800, bradley.d.vol...@intel.com wrote:
> > From: Brad Volkin
> >
> > Certain OpenGL features (e.g. transform feedback, performance monitoring)
> > require userspace code to submit batches
On Wed, 2013-11-27 at 09:10 +0100, Daniel Vetter wrote:
> On Wed, Nov 27, 2013 at 09:32:32AM +0800, ykzhao wrote:
> > On Tue, 2013-11-26 at 13:24 -0700, Volkin, Bradley D wrote:
> > > On Tue, Nov 26, 2013 at 11:35:38AM -0800, Daniel Vetter wrote:
> > > > Hi Brad,
> > > >
> > > > On Tue, Nov 26, 2
On Wed, 2013-11-27 at 09:31 +0100, Daniel Vetter wrote:
> On Wed, Nov 27, 2013 at 9:23 AM, Xiang, Haihao wrote:
> >> So are these 2nd level batches constructed by the gpu in some cases? That
> >> would be fairly horribly to take into account with the batch checker ...
> &
On Wed, 2013-11-27 at 09:47 +0100, Daniel Vetter wrote:
> On Wed, Nov 27, 2013 at 04:42:11PM +0800, Xiang, Haihao wrote:
> > On Wed, 2013-11-27 at 09:31 +0100, Daniel Vetter wrote:
> > > On Wed, Nov 27, 2013 at 9:23 AM, Xiang, Haihao
> > > wrote:
> > &g
From: "Xiang, Haihao"
The code is for reference only
Signed-off-by: Xiang, Haihao
---
shaders/media/README |6 ++
shaders/media/media_fill.gxa | 30 ++
2 files changed, 36 insertions(+)
create mode 100644 shaders/media/README
create m
From: "Xiang, Haihao"
Signed-off-by: Xiang, Haihao
---
lib/Makefile.sources |2 +
lib/gen7_media.h | 323 +
lib/media_fill.c |2 +
lib/media_fill.h |7 +
lib/media_fill_gen
From: "Xiang, Haihao"
Signed-off-by: Xiang, Haihao
---
lib/Makefile.sources |2 +
lib/gen8_media.h | 371 +
lib/media_fill.c |3 +
lib/media_fill.h |7 +
lib/media_fill_gen
From: "Xiang, Haihao"
It is to check whether media pipeline on render ring works. Codes
are copied and modified from the rendercopy case which uses 3D pipeline.
However media pipeline is simpler than 3D pipeline and there is few changes
between gen6,gen7 and gen8
Signed-off-by: Xia
> On Thu, 2013-11-28 at 23:57 -0700, Xiang, Haihao wrote:
> > From: "Xiang, Haihao"
> >
> > The code is for reference only
> >
> > Signed-off-by: Xiang, Haihao
> > ---
> > shaders/media/README |6 ++
> > shaders/medi
On Fri, 2013-11-29 at 09:02 +0100, Daniel Vetter wrote:
> On Fri, Nov 29, 2013 at 02:57:13PM +0800, Xiang, Haihao wrote:
> > From: "Xiang, Haihao"
> >
> > It is to check whether media pipeline on render ring works. Codes
> > are copied and modified f
From: "Xiang, Haihao"
It is to check whether media pipeline on render ring works. Codes
are copied and modified from the rendercopy case which uses 3D pipeline.
However media pipeline is simpler than 3D pipeline and there is few changes
between gen6,gen7 and gen8
Signed-off-by: Xia
From: "Xiang, Haihao"
The code is for reference only
v2: Fixed the source register used for the send with EOT
Fixed the posted destination operand for the send with EOT
Signed-off-by: Xiang, Haihao
---
shaders/media/README |6 ++
shaders/media/media_fill.
From: "Xiang, Haihao"
v2: Fixed the source register used for the send with EOT
Fixed the posted destination operand for the send with EOT
Signed-off-by: Xiang, Haihao
---
lib/Makefile.sources |2 +
lib/gen8_media.h | 371
From: "Xiang, Haihao"
v2: Fixed the source register used for the send with EOT
Fixed the posted destination operand for the send with EOT
Signed-off-by: Xiang, Haihao
---
lib/Makefile.sources |2 +
lib/gen7_media.h | 323
From: "Xiang, Haihao"
It is to check whether media pipeline on render ring works. Codes
are copied and modified from the rendercopy case which uses 3D pipeline.
However media pipeline is simpler than 3D pipeline and there is few changes
between gen6,gen7 and gen8
Reviewed-by: Zhao Yak
From: "Xiang, Haihao"
v2: Fixed the source register used for the send with EOT
Fixed the posted destination operand for the send with EOT
v3: Workaround: Insert MEDIA_STATE_FLUSH after MEDIA_OBJECT.
Fixed the cache agent used in media_block_write message
Set Instruction B
From: "Xiang, Haihao"
v2: Fixed the source register used for the send with EOT
Fixed the posted destination operand for the send with EOT
Reviewed-by: Zhao Yakui
Signed-off-by: Xiang, Haihao
---
lib/Makefile.sources |2 +
lib/gen7_media.h
From: "Xiang, Haihao"
The code is for reference only
v2: Fixed the source register used for the send with EOT
Fixed the posted destination operand for the send with EOT
v3: Fixed the cache agent used in media_block_write message on GEN8
Reviewed-by: Zhao Yakui
Signed-off
From: "Xiang, Haihao"
write(...) is used for Render Target Write and Media Block Write.
The two message types no longer share the same cache agent on GEN8,
So a parameter is needed for cache agent. The 4th parameter of write()
is used for write commit bit which has been removed since G
From: "Xiang, Haihao"
Otherwise it may result in GPU hang
Signed-off-by: Xiang, Haihao
---
lib/rendercopy_gen8.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c
index 43e962c..1a137dd 100644
--- a/lib/rendercopy_ge
From: "Xiang, Haihao"
Emit PIPELINE_SELECT twice and make sure the commands in
the first batch buffer have been done.
However I don't know why this works !!!
Signed-off-by: Xiang, Haihao
---
lib/rendercopy_gen8.c | 19 +--
1 file changed, 17 insertions(
From: "Xiang, Haihao"
This reverts commit e41928e6c9bb3f24833a827903f1afeda83592d6.
Now the case no longer causes GPU hang on GEN
---
lib/rendercopy_i830.c |6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/lib/rendercopy_i830.c b/lib/rendercopy_i830.c
ind
From: "Xiang, Haihao"
Otherwise the stale data in the buffer
Signed-off-by: Xiang, Haihao
---
lib/intel_batchbuffer.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 06a5437..9ce7424 100644
--- a/lib/intel_batchbuff
On Fri, 2013-12-06 at 13:30 +, Damien Lespiau wrote:
> On Fri, Dec 06, 2013 at 04:54:46PM +0800, Xiang, Haihao wrote:
> > From: "Xiang, Haihao"
> >
> > Emit PIPELINE_SELECT twice and make sure the commands in
> > the first batch buffer have been done.
&
On Tue, 2013-12-10 at 09:04 -0800, Kenneth Graunke wrote:
> On 12/10/2013 03:40 AM, Damien Lespiau wrote:
> > On Mon, Dec 09, 2013 at 11:29:35PM -0800, Kenneth Graunke wrote:
> >> We don't want depth/stencil fast clears or HiZ resolves; we want normal
> >> drawing. Without this, the pixel pipelin
On Thu, 2013-12-12 at 15:28 -0800, Ben Widawsky wrote:
> I stumbled on to some unimplemented errata. To be honest, I am not
> really sure of the impact, just that the docs say to do.
>
> No w/a name for this one.
>
> Cc: Kenneth Graunke
> Signed-off-by: Ben Widawsky
> ---
> drivers/gpu/drm/i9
From: "Xiang, Haihao"
CC eudb.o
In file included from eudb.c:44:0:
../lib/drmtest.h:34:19: fatal error: cairo.h: No such file or directory
compilation terminated.
make[3]: *** [eudb.o] Error 1
Signed-off-by: Xiang, Haihao
---
debugger/Makefile.am |3 ++-
1 file changed, 2
The libva driver for Intel doesn't support GM35.
Thanks
Haihao
> Howdy,
>
> Xorg says:
> [ 36196.880] (II) Loading /usr/lib/xorg/modules/drivers/intel_drv.so
> [ 36196.880] drmOpenDevice: node name is /dev/dri/card0
> [ 36196.880] drmOpenDevice: open result is 9, (OK)
> [ 36196.880] drmOpenByBu
On Thu, 2012-05-24 at 08:40 +0800, 袁竞杰 wrote:
> At last,I found the answer.
> I used libdrm-2.4.27 which does not support IVYBRIDGE_S_GT2. Using the
> latest libdrm-2.4.34 to solve this problem.
> VAAPI still complains "cannot open i965_drv_video.so",I find the
> latest intel-driver-1.0.17 doesn't
Hi, Angela
Could you file a bug and provide more details how to reproduce this
issue ?
Thanks
Haihao
> > Am Mittwoch, den 13.06.2012, 00:09 +0200 schrieb Angela:
> > > >> >For gpu hangs the important thing is the i915_error_state file
> > > >> >from sysfs
> > > >> (the files you've attached are
On Mon, 2012-07-02 at 18:49 +, Christophe Oosterlynck wrote:
> Hi,
>
> Is there any update on this issue or has a bug been reported?
>
> I seem to have a similar issue ("[drm:i915_hangcheck_hung] *ERROR* Hangcheck
> timer") when using vaapi with gstreamer.
>
https://bugs.freedesktop.org/s
The support for Main/High profile has been done in the staging branch.
We will merge the interfaces for Main/High profile back into the master
branch.
Thanks
Haihao
> Hello my name is Charlie Good and I am the CTO of Wowza Media System.
> We are the authors of Wowza Media Server. Our product in
No, you don't need to modify the drm kernel for the decoded output data.
You can directly map the corresponding buffer (GEM buffer) after
executing the batchbuffer.
BTW The decoded frame is specified in MFX_PIPE_BUF_ADDR_STATE too.
Thanks
Haihao
> Hi all,
>
>
>
> Anybody has any suggesti
From: Zhao Yakui
Signed-off-by: Zhao Yakui
---
include/drm/i915_drm.h |2 ++
1 file changed, 2 insertions(+)
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 7e9e9bd..8b069ac 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -303,6 +303,8 @@ typedef stru
From: "Xiang, Haihao"
v2: Fix the test for has_vebox
Signed-off-by: Xiang, Haihao
---
include/drm/i915_drm.h |2 ++
intel/intel_bufmgr_gem.c |9 +
2 files changed, 11 insertions(+)
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 8b069ac..2341
From: "Xiang, Haihao"
Xiang, Haihao (2):
tests: storedw on VEBOX
Update gem_ring_sync_loop to support VEBOX ring (the 4th ring) on
Haswell
lib/intel_chipset.h|2 +
tests/Makefile.am |1 +
tests/gem_ring_sync_loop.c | 18 ++
From: "Xiang, Haihao"
Signed-off-by: Xiang, Haihao
---
lib/intel_chipset.h|2 +
tests/Makefile.am |1 +
tests/gem_storedw_loop_vebox.c | 153
3 files changed, 156 insertions(+)
create mode 10
From: "Xiang, Haihao"
Signed-off-by: Xiang, Haihao
---
tests/gem_ring_sync_loop.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/tests/gem_ring_sync_loop.c b/tests/gem_ring_sync_loop.c
index b689bcd..199dcfd 100644
--- a/tests/gem_ring_s
From: "Xiang, Haihao"
Signed-off-by: Xiang, Haihao
---
tests/gem_ring_sync_loop.c | 37 ++---
1 file changed, 34 insertions(+), 3 deletions(-)
diff --git a/tests/gem_ring_sync_loop.c b/tests/gem_ring_sync_loop.c
index b689bcd..2875cf3 100644
-
On Wed, 2012-11-14 at 08:23 +, Chris Wilson wrote:
> On Wed, 14 Nov 2012 12:55:54 +0800, "Xiang, Haihao"
> wrote:
> > From: "Xiang, Haihao"
> >
> > Xiang, Haihao (2):
> > tests: storedw on VEBOX
> > Update gem_ring_sync_loop
From: "Xiang, Haihao"
The code is surround by a #ifdef...#endif to avoid to break compiling against
the current libdrm release
Signed-off-by: Xiang, Haihao
---
tests/gem_ring_sync_loop.c | 12
1 file changed, 12 insertions(+)
diff --git a/tests/gem_ring_sync_loop
On Thu, 2012-11-15 at 12:30 +0100, Daniel Vetter wrote:
> On Wed, Nov 14, 2012 at 12:46:38PM +0800, Xiang, Haihao wrote:
> > From: Zhao Yakui
> >
> > Signed-off-by: Zhao Yakui
>
> Fyi the best way is to simply run
>
> $ make headers_install
>
>
Hi,
I know what is the problem. For some reason, the native pixel format
for MPEG-2 decoding on Clarkdale is I420, however the input pixel format
of deinterlacing is NV12 in the driver, so the driver doesn't support
deinterlacing for MPEG-2 on Clardale. We will try to fix this issue but
don't
On Tue, 2012-01-31 at 17:32 +0100, Christoph Evers wrote:
> Hi folks,
>
> i am not sure whether this issue belongs to the libva mailinglist or
> this one. I'll give it a try :-)
You can send all VAAPI related mail to li...@lists.freedesktop.org
> For testing purpose I switched to vaapi-ext bra
> Please, can anyone tell me if there is a list for user questions about
> VAAPI? I have several questions...
The list for VAAPI is li...@lists.freedesktop.org
As for brightness property, the driver doesn't support it.
Thanks
Haihao
>
> Greets,
> Kiste
>
>
>
> Am 09.03.2012 08:04, schrieb
Add set_tail hook to struct intel_ring_buffer
Signed-off-by: Xiang, Haihao
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 22 +-
drivers/gpu/drm/i915/intel_ringbuffer.h |2 ++
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915
This ring buffer is used for video decoding/encoding on Sandybridge.
Signed-off-by: Xiang, Haihao
---
drivers/gpu/drm/i915/i915_drv.h |2 +-
drivers/gpu/drm/i915/i915_gem.c |6 ++-
drivers/gpu/drm/i915/i915_irq.c | 15 +++--
drivers/gpu/drm/i915/i915_reg.h
On Thu, 2010-09-02 at 15:16 +0800, Chris Wilson wrote:
> Comments inline.
Thanks for your comments.
>
> On Thu, 2 Sep 2010 21:46:54 +0800, "Xiang, Haihao"
> wrote:
> > This ring buffer is used for video decoding/encoding on Sandybridge.
> >
On Thu, 2010-09-02 at 22:56 +0800, Daniel Vetter wrote:
> On Thu, Sep 02, 2010 at 09:46:54PM +0800, Xiang, Haihao wrote:
> > /*
> > + * video command stream instruction and interrupt control register defines
> > + * for GEN6
> > + */
> > +#define GEN6_BSD_RING_
Some little changes:
Add set_tail hook to struct intel_ring_buffer
fix HAS_BSD with a device info flag
Don't export the initialiser of struct intel_ring_buffer
Signed-off-by: Xiang, Haihao
---
drivers/gpu/drm/i915/i915_drv.c |4 ++
drivers/gpu/drm/i915/i915_
This ring buffer is used for video decoding/encoding on Sandybridge.
Signed-off-by: Xiang, Haihao
---
drivers/gpu/drm/i915/i915_drv.c |2 +
drivers/gpu/drm/i915/i915_irq.c | 15 +++-
drivers/gpu/drm/i915/i915_reg.h | 26 ++-
drivers/gpu/drm/i915
On Mon, 2010-09-13 at 17:52 +0800, Chris Wilson wrote:
> On Mon, 13 Sep 2010 15:17:05 +0800, "Xiang, Haihao"
> wrote:
> > Some little changes:
> > Add set_tail hook to struct intel_ring_buffer
> > fix HAS_BSD with a device info flag
> >
Signed-off-by: Xiang, Haihao
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c |4
drivers/gpu/drm/i915/i915_drv.h |3 ++-
2 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index dffc1bc
Introduce intel_init_render_ring_buffer(), intel_init_bsd_ring_buffer
for ring initialization.
Signed-off-by: Xiang, Haihao
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 14 ++
drivers/gpu/drm/i915/intel_ringbuffer.c | 29
This is prepared for video codec ring buffer on Sandybridge. It is
needed to read/write more than one register to move the tail pointer of
the video codec ring on Sandybridge.
Signed-off-by: Xiang, Haihao
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 22
This ring buffer is used for video decoding/encoding on Sandybridge.
Signed-off-by: Xiang, Haihao
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c |2 +
drivers/gpu/drm/i915/i915_irq.c | 15 +++-
drivers/gpu/drm/i915/i915_reg.h | 26 ++-
drivers
On Thu, 2010-09-16 at 12:21 +0800, Zhenyu Wang wrote:
> On 2010.09.16 10:43:12 +0800, Xiang, Haihao wrote:
> > This is prepared for video codec ring buffer on Sandybridge. It is
> > needed to read/write more than one register to move the tail pointer of
> > the video code
On Thu, 2010-09-16 at 13:37 +0800, Zhenyu Wang wrote:
> On 2010.09.16 13:10:29 +0800, Xiang, Haihao wrote:
> > > Or can't that be done in init function by using advance_ring?
> > advance_ring uses ring->tail to set TAIL register, i965_reset() also
> > invokes rin
Here is a set of patches for GFX assembler to support Sandybridge. We will
try to re-use all existing render shaders with these fixes. Note these patches
don't support for some Sandybridge ISA changes such as math instructions,
IF/ELSE/ENDIF etc.
___
Signed-off-by: Xiang, Haihao
---
src/main.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/main.c b/src/main.c
index 2757e96..7c0b579 100644
--- a/src/main.c
+++ b/src/main.c
@@ -49,7 +49,7 @@ static const struct option longopts[] = {
static void usage(void
It is same as Ironlake.
Signed-off-by: Xiang, Haihao
---
src/main.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/main.c b/src/main.c
index 7c0b579..12901a7 100644
--- a/src/main.c
+++ b/src/main.c
@@ -130,7 +130,7 @@ int main(int argc, char **argv
Signed-off-by: Xiang, Haihao
---
src/brw_structs.h |4 ++--
src/gram.y|2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/brw_structs.h b/src/brw_structs.h
index ba20547..32a52df 100644
--- a/src/brw_structs.h
+++ b/src/brw_structs.h
@@ -1102,7 +1102,7
Signed-off-by: Xiang, Haihao
---
src/brw_defines.h |3 +++
src/brw_structs.h |3 ++-
src/gram.y|6 +-
src/lex.l |1 +
4 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/brw_defines.h b/src/brw_defines.h
index 7812d72..4921d34 100644
--- a/src
Send doesn't have implied move on Sandybridge, the SFID moves to bits[24,27]
which
is used as the destination of the implied move on Prev GEN6.
Signed-off-by: Xiang, Haihao
---
src/brw_structs.h |2 +-
src/disasm.c |4 ++--
src/gram.y| 20 +---
3
Signed-off-by: Xiang, Haihao
---
src/brw_structs.h | 13 +
src/gram.y| 14 +-
2 files changed, 26 insertions(+), 1 deletions(-)
diff --git a/src/brw_structs.h b/src/brw_structs.h
index 92a398e..6a29f37 100644
--- a/src/brw_structs.h
+++ b/src/brw_structs.h
Signed-off-by: Xiang, Haihao
---
src/brw_structs.h | 12
src/gram.y|9 -
2 files changed, 20 insertions(+), 1 deletions(-)
diff --git a/src/brw_structs.h b/src/brw_structs.h
index 6a29f37..9b1cd92 100644
--- a/src/brw_structs.h
+++ b/src/brw_structs.h
Signed-off-by: Xiang, Haihao
---
src/gram.y | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/gram.y b/src/gram.y
index ffb0851..9258ac7 100644
--- a/src/gram.y
+++ b/src/gram.y
@@ -557,7 +557,7 @@ post_dst: dst
msgtarget: NULL_TOKEN
Sandybridge doesn't have math funtion, instead it supports a set of math
instructions. The support for math instructions will be added later.
Signed-off-by: Xiang, Haihao
---
src/gram.y |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/src/gram.y b/src/gram.y
Signed-off-by: Xiang, Haihao
---
src/gram.y |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gram.y b/src/gram.y
index e61e9db..a57e4e9 100644
--- a/src/gram.y
+++ b/src/gram.y
@@ -1612,8 +1612,10 @@ instoption_list
Here is the set of patches to enable texture adaptor on Sandybridge.
Currently you need to turn off shadow in /etc/xorg.conf to use texture
video on Sandybridge
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mail
To prepare for Xv on Sandybridge. It is easy to fill the binding
table without relocation and make sure that the pointer to binding
table only uses bits[15:0].
Signed-off-by: Xiang, Haihao
---
src/i965_video.c | 141 +
1 files changed, 67
The two fragments will be reused for sampling YUV surface
and send doesn't have implied move on Sandybridge
Signed-off-by: Xiang, Haihao
---
src/render_program/exa_wm_src_sample_argb.g4a |3 ++-
src/render_program/exa_wm_src_sample_argb.g4b |3 ++-
src/render_pr
Need to update intel-gen4asm to build these fragments
Signed--off-by: Xiang, Haihao
---
configure.ac|2 +-
src/render_program/Makefile.am | 27 +++-
src/render_program/exa_wm_src_affine.g6a| 47 +
src
Signed-off-by: Xiang, Haihao
---
src/brw_structs.h | 100
src/i965_reg.h | 98
src/i965_video.c| 624 +++
src/intel.h |4 +
src/intel_batchbuffer.c | 25 ++-
src/intel_video.h |7
Signed-off-by: Xiang, Haihao
---
src/intel_video.c |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/intel_video.c b/src/intel_video.c
index 5d16778..afc2405 100644
--- a/src/intel_video.c
+++ b/src/intel_video.c
@@ -364,7 +364,6 @@ void I830InitVideo(ScreenPtr
MI_LOAD_SCAN_LINE_INCL command is not available on sandybridge.
Signed-off-by: Xiang, Haihao
---
src/intel_video.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/intel_video.c b/src/intel_video.c
index afc2405..cdff149 100644
--- a/src/intel_video.c
+++ b/src
On Thu, 2010-10-21 at 17:31 +0800, Chris Wilson wrote:
> On Thu, 21 Oct 2010 16:55:40 +0800, "Xiang, Haihao"
> wrote:
> > Here is the set of patches to enable texture adaptor on Sandybridge.
> > Currently you need to turn off shadow in /etc/xorg.conf to use text
Here is the set of patches to enable texture adaptor on Sandybridge.
Currently you need to turn off shadow in /etc/xorg.conf to use texture
video on Sandybridge
v2: refresh the patches, fix a conflict with a recent commit on master
___
Intel-gfx mailing
To prepare for Xv on Sandybridge. It is easy to fill the binding
table without relocation and make sure that the pointer to binding
table only uses bits[15:0].
Signed-off-by: Xiang, Haihao
---
src/i965_video.c | 141 +
1 files changed, 67
The two fragments will be reused for sampling YUV surface
and send doesn't have implied move on Sandybridge
Signed-off-by: Xiang, Haihao
---
src/render_program/exa_wm_src_sample_argb.g4a |3 ++-
src/render_program/exa_wm_src_sample_argb.g4b |3 ++-
src/render_pr
Need to update intel-gen4asm to build these fragments
Signed--off-by: Xiang, Haihao
---
configure.ac|2 +-
src/render_program/Makefile.am | 27 +++-
src/render_program/exa_wm_src_affine.g6a| 47 +
src
Signed-off-by: Xiang, Haihao
---
src/brw_structs.h | 100
src/i965_reg.h | 98
src/i965_video.c| 627 +++
src/intel.h |4 +
src/intel_batchbuffer.c | 25 ++-
src/intel_video.h |7
Signed-off-by: Xiang, Haihao
---
src/intel_video.c |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/intel_video.c b/src/intel_video.c
index 5d16778..afc2405 100644
--- a/src/intel_video.c
+++ b/src/intel_video.c
@@ -364,7 +364,6 @@ void I830InitVideo(ScreenPtr
MI_LOAD_SCAN_LINE_INCL command is not available on sandybridge.
Signed-off-by: Xiang, Haihao
---
src/intel_video.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/intel_video.c b/src/intel_video.c
index afc2405..cdff149 100644
--- a/src/intel_video.c
+++ b/src
It is the same as commit 73d4c7d7
Signed-off-by: Xiang, Haihao
---
src/i965_render.c | 75 +
1 files changed, 24 insertions(+), 51 deletions(-)
diff --git a/src/i965_render.c b/src/i965_render.c
index c0c5de4..885889e 100644
--- a/src
To prepare for composite on Sandybridge
Signed-off-by: Xiang, Haihao
---
src/render_program/exa_wm_mask_sample_a.g4a|3 ++-
src/render_program/exa_wm_mask_sample_a.g4b|3 ++-
src/render_program/exa_wm_mask_sample_a.g4b.gen5 |3 ++-
src/render_program
Signed-off-by: Xiang, Haihao
---
src/render_program/Makefile.am | 18 +++
src/render_program/exa_wm_ca.g6a |1 +
src/render_program/exa_wm_ca.g6b |4 ++
src/render_program/exa_wm_ca_srcalpha.g6a |1 +
src/render_program
Signed-off-by: Xiang, Haihao
---
src/i965_render.c | 686 +++--
1 files changed, 670 insertions(+), 16 deletions(-)
diff --git a/src/i965_render.c b/src/i965_render.c
index 885889e..e2b67c3 100644
--- a/src/i965_render.c
+++ b/src/i965_render.c
It is weird that some rendercheck cases only work fine with headerless write.
Need to update intel-gen4asm to support headerless write
Signed-off-by: Xiang, Haihao
---
src/render_program/exa_wm_write.g6a | 10 --
src/render_program/exa_wm_write.g6b |4 +---
2 files changed, 5
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