On Thu, 2013-12-12 at 15:28 -0800, Ben Widawsky wrote: > I stumbled on to some unimplemented errata. To be honest, I am not > really sure of the impact, just that the docs say to do. > > No w/a name for this one. > > Cc: Kenneth Graunke <kenn...@whitecape.org> > Signed-off-by: Ben Widawsky <b...@bwidawsk.net> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_pm.c | 7 +++++++ > 2 files changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e8cc27c..3259e83 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4167,6 +4167,10 @@ > #define GEN7_L3SQCREG4 0xb034 > #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27) > > +/* GEN8 chicken */ > +#define HDC_CHICKEN0 0x7300 > +#define HDC_FORCE_NON_COHERENT (1<<4) > + > /* WaCatErrorRejectionIssue */ > #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030 > #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index ac9dd46..7e2a0e9 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -5279,6 +5279,13 @@ static void gen8_init_clock_gating(struct drm_device > *dev) > I915_READ(CHICKEN_PIPESL_1(i) | > DPRS_MASK_VBLANK_SRD)); > } > + > + /* Use Force Non-Coherent whenever executing a 3D context. This is a > + * workaround for for a possible hang in the unlikely event a TLB > + * invalidation occurs during a PSD flush. > + */ > + I915_WRITE(HDC_FORCE_NON_COHERENT,
It should be HDC_CHICKEN0 instead of HDC_FORCE_NON_COHERENT > + I915_READ(HDC_CHICKEN0) | HDC_FORCE_NON_COHERENT); It has a mask bit which should be set for writing > } > > static void haswell_init_clock_gating(struct drm_device *dev) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
